Similar to Bug 417452, where the instruction selector sometimes attempted
to generate vector stores with a 20-bit displacement, the same problem has
now been reported with vector loads.
The problem is caused in s390_isel_vec_expr_wrk(), where the addressing
mode is generated with s390_isel_amode() instead of
s390_isel_amode_short(). This is fixed.
Mark
LD3/ST3 (multiple 3-elem structs to/from 3 regs
LD4/ST4 (multiple 4-elem structs to/from 4 regs
as "verbose", since they can generate so much IR that a long sequence
of them causes later stages of the JIT to run out of space.
faccessat2 is a new syscall in linux 5.8 and will be used by glibc 2.33.
faccessat2 is simply faccessat with a new flag argument. It has
a common number across all linux arches.
https://bugs.kde.org/427787
Add support for:
vdivesd Vector Divide Extended Signed Doubleword
vdivesw Vector Divide Extended Signed Word
vdiveud Vector Divide Extended Unsigned Doubleword
vdiveuw Vector Divide Extended Unsigned Word
vdivsd Vector Divide Signed Doubleword
vdivsw Vector Divide Signed Word
vdivud Vector Divide Unsigned Doubleword
vdivuw Vector Divide Unsigned Word
vmodsd Vector Modulo Signed Doubleword
vmodsw Vector Modulo Signed Word
vmodud Vector Modulo Unsigned Doubleword
vmoduw Vector Modulo Unsigned Word
vmulhsd Vector Multiply High Signed Doubleword
vmulhsw Vector Multiply High Signed Word
vmulhud Vector Multiply High Unsigned Doubleword
vmulhuw Vector Multiply High Unsigned Word
vmulld Vector Multiply Low Doubleword
Add support for the new ISA 3.1 load and store
instructions:
lxvpx Load VSX Vector Paired Indexed
plxvp Prefixed Load VSX Vector Paired
pstxvp Prefixed Store VSX Vector Paired
stxvpx Store VSX Vector Paired Indexed
Update the parsing of the lxvp and stxvp instructions that
were previously added.
lxvp Load VSX Vector Paired
stxvp Store VSX Vector Paired
A couple of format changes for the arguments to the
calculate_prefix_EA function.
Add comments to the else if and case statement to
clarify which instructions meet this condition.
Add support for the new ISA 3.1 set boolean condition
word instructions:
setbc Set Boolean Condition
setbcr Set Boolean Condition Reverse
setnbc Set Negative Boolean Condition
setnbcr Set Negative Boolean Condition Reverse.
On ppc64 [old big endian] altivec.h can not be included directly.
Move the HAS_ISA_3_1 guard around so the include is only done when
the full test (and test_list_t) are build.
Apparently on Fedora 33 the POSIX thread functions exist in both libc and
libpthread. Hence this patch that intercepts the pthread functions in
libc. See also https://bugs.kde.org/show_bug.cgi?id=426144 .
This is necessary to avoid some false positives in code compiled by clang 10
at -O2. Some very crude measurements suggest the increase in generated code
size is around 0.2%, viz, insignificant.
In the IR optimiser (ir_opt.c): Recognise the following IROps as
dependency-breaking ops that generate an all-ones output: Iop_CmpEQ16x4
Iop_CmpEQ32x2 Iop_CmpEQ64x2 Iop_CmpEQ8x32 Iop_CmpEQ16x16 Iop_CmpEQ64x4. I
think this fixes all the known cases for sizes 32 bits to 256 bits. It also
fixes bug 425820.
This commit implements amd64 RDSEED instruction, on hosts that have it
and adds the new test case - none/tests/amd64/rdseed based on the existing
rdrand support.
https://bugs.kde.org/show_bug.cgi?id=424298
Newer glibc have alternate ld.so _ld_runtime_resolve functions.
Namely _dl_runtime_resolve_xsave and _dl_runtime_resolve_xsavec
This patch recognizes the xsave, xsvec and fxsave variants and
changes callgrind so that any variant counts as _dl_runtime_resolve.
Original patch by paulo.cesar.pereira.de.andrade@gmail.comhttps://bugs.kde.org/show_bug.cgi?id=415293
The NET Core runtime might generate a JMP with a REX prefix.
For Jv (32bit offset) and Jb (8bit offset) this is valid.
Prefixes that change operand size are ignored for such JMPs.
So remove the check for sz == 4 and force sz = 4 for Jv.
https://bugs.kde.org/show_bug.cgi?id=422174
m_syswrap/syswrap-linux.c:3716:10: warning: format '%ld' expects argument of type 'long int', but argument 4 has type 'RegWord' {aka 'long unsigned int'} [-Wformat=]
struct vki_epoll_event is packed on x86_64, but not on other 64bit
arches. This means that on 64bit arches there can be padding in the
epoll_event struct. Seperately the data field is only used by user
space (which might not set the data field if it doesn't need to).
Only check the events field on epoll_ctl. But assume both events
and data are both written to by epoll_[p]wait (exclude padding).
https://bugs.kde.org/show_bug.cgi?id=422623
The only "special" thing about these syscalls is that the given
struct sched_attr determines its own size for future expansion.
Original fix by "ISHIKAWA,chiaki" <ishikawa@yk.rim.or.jp>
https://bugs.kde.org/show_bug.cgi?id=369029
Replace the gsl16test script under auxprogs that you run by hand
with a new make target auxchecks which fetches the source code,
patches, reconfigures and builds all tests. Then run all tests
under valgrind.
The L field is currently a two bit[22:21] field in ISA 3.0. The size of the
L field has changed over time.
Currently the ISA 3.0 Valgrind sync instruction support code sets the
flag_L for the instruction L field to a five bit value that includes bits
that are marked reserved the sync instruction. This patch fixes the issue for ISA 3.0
to only setting flag_L the specified two bits.
Valgrind bugzilla: https://bugs.kde.org/show_bug.cgi?id=422677
When generating HTML it is useful if every element that can be referenced
has a stable id. If it doesn't a random one is generated which makes it
harder to link to parts of the manual on the website. It also generates
spurious diffs. Explicitly add an id tag for the sect2 and sect3 elements
in dh-manual, a unique id for each legalnotice element and for each
FAQ question and answer.
