mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-07 12:44:45 +00:00
Set boolean support tests
This commit is contained in:
parent
ba7b334361
commit
5fcffeabeb
@ -58,6 +58,406 @@ static void test_brw (void) {
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static void test_brd (void) {
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__asm__ __volatile__ ("brd %0, %1" : "=r" (ra) : "r" (rs) );
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}
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static void test_setbc_0_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setbc 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_0_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setbc 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_0_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setbc 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_0_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setbc 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_3_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setbc 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_3_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setbc 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_3_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setbc 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_3_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setbc 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_7_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setbc 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_7_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setbc 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_7_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setbc 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_7_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setbc 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_8_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setbc 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_8_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setbc 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_8_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setbc 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_8_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setbc 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_31_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setbc 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_31_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setbc 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_31_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setbc 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbc_31_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setbc 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_0_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setbcr 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_0_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setbcr 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_0_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setbcr 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_0_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setbcr 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_3_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setbcr 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_3_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setbcr 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_3_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setbcr 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_3_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setbcr 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_7_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setbcr 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_7_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setbcr 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_7_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setbcr 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_7_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setbcr 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_8_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setbcr 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_8_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setbcr 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_8_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setbcr 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_8_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setbcr 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_31_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setbcr 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_31_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setbcr 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_31_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setbcr 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setbcr_31_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setbcr 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_0_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setnbc 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_0_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setnbc 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_0_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setnbc 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_0_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setnbc 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_3_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setnbc 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_3_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setnbc 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_3_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setnbc 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_3_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setnbc 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_7_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setnbc 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_7_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setnbc 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_7_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setnbc 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_7_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setnbc 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_8_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setnbc 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_8_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setnbc 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_8_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setnbc 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_8_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setnbc 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_31_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setnbc 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_31_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setnbc 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_31_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setnbc 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbc_31_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setnbc 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_0_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setnbcr 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_0_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setnbcr 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_0_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setnbcr 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_0_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setnbcr 26, 0");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_3_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setnbcr 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_3_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setnbcr 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_3_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setnbcr 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_3_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setnbcr 26, 3");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_7_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setnbcr 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_7_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setnbcr 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_7_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setnbcr 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_7_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setnbcr 26, 7");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_8_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setnbcr 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_8_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setnbcr 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_8_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setnbcr 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_8_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setnbcr 26, 8");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_31_cr0s (void) {
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SET_CR(0x00000000);
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__asm__ __volatile__ ("setnbcr 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_31_cr1s (void) {
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SET_CR(0xffffffff);
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__asm__ __volatile__ ("setnbcr 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_31_creb (void) {
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SET_CR(0xaaaaaaaa);
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__asm__ __volatile__ ("setnbcr 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_setnbcr_31_crob (void) {
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SET_CR(0x55555555);
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__asm__ __volatile__ ("setnbcr 26, 31");
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GET_CR(current_cr); SET_CR_ZERO;
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}
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static void test_plbz_off0 (void) {
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__asm__ __volatile__ ("plbz %0, 0(%1), 0" : "=r" (rt) : "r" (ra) );
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}
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@ -307,6 +707,86 @@ static test_list_t testgroup_generic[] = {
|
||||
{ &test_pstw_off8, "pstw off8", "RS,D(RA),R"}, /* bcwp */
|
||||
{ &test_pstw_off16, "pstw off16", "RS,D(RA),R"}, /* bcwp */
|
||||
{ &test_pstw_off32, "pstw off32", "RS,D(RA),R"}, /* bcwp */
|
||||
{ &test_setbcr_0_cr0s, "setbcr 0_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_0_cr1s, "setbcr 0_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_0_creb, "setbcr 0_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_0_crob, "setbcr 0_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_3_cr0s, "setbcr 3_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_3_cr1s, "setbcr 3_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_3_creb, "setbcr 3_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_3_crob, "setbcr 3_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_7_cr0s, "setbcr 7_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_7_cr1s, "setbcr 7_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_7_creb, "setbcr 7_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_7_crob, "setbcr 7_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_8_cr0s, "setbcr 8_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_8_cr1s, "setbcr 8_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_8_creb, "setbcr 8_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_8_crob, "setbcr 8_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_31_cr0s, "setbcr 31_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_31_cr1s, "setbcr 31_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_31_creb, "setbcr 31_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbcr_31_crob, "setbcr 31_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_0_cr0s, "setbc 0_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_0_cr1s, "setbc 0_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_0_creb, "setbc 0_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_0_crob, "setbc 0_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_3_cr0s, "setbc 3_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_3_cr1s, "setbc 3_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_3_creb, "setbc 3_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_3_crob, "setbc 3_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_7_cr0s, "setbc 7_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_7_cr1s, "setbc 7_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_7_creb, "setbc 7_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_7_crob, "setbc 7_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_8_cr0s, "setbc 8_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_8_cr1s, "setbc 8_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_8_creb, "setbc 8_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_8_crob, "setbc 8_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_31_cr0s, "setbc 31_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_31_cr1s, "setbc 31_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_31_creb, "setbc 31_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setbc_31_crob, "setbc 31_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_0_cr0s, "setnbcr 0_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_0_cr1s, "setnbcr 0_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_0_creb, "setnbcr 0_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_0_crob, "setnbcr 0_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_3_cr0s, "setnbcr 3_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_3_cr1s, "setnbcr 3_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_3_creb, "setnbcr 3_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_3_crob, "setnbcr 3_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_7_cr0s, "setnbcr 7_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_7_cr1s, "setnbcr 7_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_7_creb, "setnbcr 7_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_7_crob, "setnbcr 7_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_8_cr0s, "setnbcr 8_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_8_cr1s, "setnbcr 8_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_8_creb, "setnbcr 8_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_8_crob, "setnbcr 8_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_31_cr0s, "setnbcr 31_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_31_cr1s, "setnbcr 31_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_31_creb, "setnbcr 31_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbcr_31_crob, "setnbcr 31_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_0_cr0s, "setnbc 0_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_0_cr1s, "setnbc 0_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_0_creb, "setnbc 0_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_0_crob, "setnbc 0_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_3_cr0s, "setnbc 3_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_3_cr1s, "setnbc 3_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_3_creb, "setnbc 3_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_3_crob, "setnbc 3_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_7_cr0s, "setnbc 7_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_7_cr1s, "setnbc 7_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_7_creb, "setnbc 7_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_7_crob, "setnbc 7_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_8_cr0s, "setnbc 8_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_8_cr1s, "setnbc 8_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_8_creb, "setnbc 8_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_8_crob, "setnbc 8_crob", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_31_cr0s, "setnbc 31_cr0s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_31_cr1s, "setnbc 31_cr1s", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_31_creb, "setnbc 31_creb", "RT,BI"}, /* bcwp */
|
||||
{ &test_setnbc_31_crob, "setnbc 31_crob", "RT,BI"}, /* bcwp */
|
||||
{ NULL, NULL },
|
||||
};
|
||||
|
||||
|
||||
@ -166,4 +166,164 @@ pstw off16 (&buffer) 102030405060708 => [ - - 7ff0000005060708 - - - -
|
||||
|
||||
pstw off32 (&buffer) 102030405060708 => [ - - - - 5a05a05a05060708 - - - ]
|
||||
|
||||
All done. Tested 64 different instruction groups
|
||||
setbcr 0_cr0s => [00000000] 1
|
||||
|
||||
setbcr 0_cr1s => [ffffffff] 0
|
||||
|
||||
setbcr 0_creb => [aaaaaaaa] 0
|
||||
|
||||
setbcr 0_crob => [55555555] 1
|
||||
|
||||
setbcr 3_cr0s => [00000000] 1
|
||||
|
||||
setbcr 3_cr1s => [ffffffff] 0
|
||||
|
||||
setbcr 3_creb => [aaaaaaaa] 1
|
||||
|
||||
setbcr 3_crob => [55555555] 0
|
||||
|
||||
setbcr 7_cr0s => [00000000] 1
|
||||
|
||||
setbcr 7_cr1s => [ffffffff] 0
|
||||
|
||||
setbcr 7_creb => [aaaaaaaa] 1
|
||||
|
||||
setbcr 7_crob => [55555555] 0
|
||||
|
||||
setbcr 8_cr0s => [00000000] 1
|
||||
|
||||
setbcr 8_cr1s => [ffffffff] 0
|
||||
|
||||
setbcr 8_creb => [aaaaaaaa] 0
|
||||
|
||||
setbcr 8_crob => [55555555] 1
|
||||
|
||||
setbcr 31_cr0s => [00000000] 1
|
||||
|
||||
setbcr 31_cr1s => [ffffffff] 0
|
||||
|
||||
setbcr 31_creb => [aaaaaaaa] 1
|
||||
|
||||
setbcr 31_crob => [55555555] 0
|
||||
|
||||
setbc 0_cr0s => [00000000] 0
|
||||
|
||||
setbc 0_cr1s => [ffffffff] 1
|
||||
|
||||
setbc 0_creb => [aaaaaaaa] 1
|
||||
|
||||
setbc 0_crob => [55555555] 0
|
||||
|
||||
setbc 3_cr0s => [00000000] 0
|
||||
|
||||
setbc 3_cr1s => [ffffffff] 1
|
||||
|
||||
setbc 3_creb => [aaaaaaaa] 0
|
||||
|
||||
setbc 3_crob => [55555555] 1
|
||||
|
||||
setbc 7_cr0s => [00000000] 0
|
||||
|
||||
setbc 7_cr1s => [ffffffff] 1
|
||||
|
||||
setbc 7_creb => [aaaaaaaa] 0
|
||||
|
||||
setbc 7_crob => [55555555] 1
|
||||
|
||||
setbc 8_cr0s => [00000000] 0
|
||||
|
||||
setbc 8_cr1s => [ffffffff] 1
|
||||
|
||||
setbc 8_creb => [aaaaaaaa] 1
|
||||
|
||||
setbc 8_crob => [55555555] 0
|
||||
|
||||
setbc 31_cr0s => [00000000] 0
|
||||
|
||||
setbc 31_cr1s => [ffffffff] 1
|
||||
|
||||
setbc 31_creb => [aaaaaaaa] 0
|
||||
|
||||
setbc 31_crob => [55555555] 1
|
||||
|
||||
setnbcr 0_cr0s => [00000000] ffffffffffffffff
|
||||
|
||||
setnbcr 0_cr1s => [ffffffff] 0
|
||||
|
||||
setnbcr 0_creb => [aaaaaaaa] 0
|
||||
|
||||
setnbcr 0_crob => [55555555] ffffffffffffffff
|
||||
|
||||
setnbcr 3_cr0s => [00000000] ffffffffffffffff
|
||||
|
||||
setnbcr 3_cr1s => [ffffffff] 0
|
||||
|
||||
setnbcr 3_creb => [aaaaaaaa] ffffffffffffffff
|
||||
|
||||
setnbcr 3_crob => [55555555] 0
|
||||
|
||||
setnbcr 7_cr0s => [00000000] ffffffffffffffff
|
||||
|
||||
setnbcr 7_cr1s => [ffffffff] 0
|
||||
|
||||
setnbcr 7_creb => [aaaaaaaa] ffffffffffffffff
|
||||
|
||||
setnbcr 7_crob => [55555555] 0
|
||||
|
||||
setnbcr 8_cr0s => [00000000] ffffffffffffffff
|
||||
|
||||
setnbcr 8_cr1s => [ffffffff] 0
|
||||
|
||||
setnbcr 8_creb => [aaaaaaaa] 0
|
||||
|
||||
setnbcr 8_crob => [55555555] ffffffffffffffff
|
||||
|
||||
setnbcr 31_cr0s => [00000000] ffffffffffffffff
|
||||
|
||||
setnbcr 31_cr1s => [ffffffff] 0
|
||||
|
||||
setnbcr 31_creb => [aaaaaaaa] ffffffffffffffff
|
||||
|
||||
setnbcr 31_crob => [55555555] 0
|
||||
|
||||
setnbc 0_cr0s => [00000000] 0
|
||||
|
||||
setnbc 0_cr1s => [ffffffff] ffffffffffffffff
|
||||
|
||||
setnbc 0_creb => [aaaaaaaa] ffffffffffffffff
|
||||
|
||||
setnbc 0_crob => [55555555] 0
|
||||
|
||||
setnbc 3_cr0s => [00000000] 0
|
||||
|
||||
setnbc 3_cr1s => [ffffffff] ffffffffffffffff
|
||||
|
||||
setnbc 3_creb => [aaaaaaaa] 0
|
||||
|
||||
setnbc 3_crob => [55555555] ffffffffffffffff
|
||||
|
||||
setnbc 7_cr0s => [00000000] 0
|
||||
|
||||
setnbc 7_cr1s => [ffffffff] ffffffffffffffff
|
||||
|
||||
setnbc 7_creb => [aaaaaaaa] 0
|
||||
|
||||
setnbc 7_crob => [55555555] ffffffffffffffff
|
||||
|
||||
setnbc 8_cr0s => [00000000] 0
|
||||
|
||||
setnbc 8_cr1s => [ffffffff] ffffffffffffffff
|
||||
|
||||
setnbc 8_creb => [aaaaaaaa] ffffffffffffffff
|
||||
|
||||
setnbc 8_crob => [55555555] 0
|
||||
|
||||
setnbc 31_cr0s => [00000000] 0
|
||||
|
||||
setnbc 31_cr1s => [ffffffff] ffffffffffffffff
|
||||
|
||||
setnbc 31_creb => [aaaaaaaa] 0
|
||||
|
||||
setnbc 31_crob => [55555555] ffffffffffffffff
|
||||
|
||||
All done. Tested 144 different instruction groups
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user