mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
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valgrind isa 3.1 foundation
header files and other common parts associated with the initial isa v3.1 support
This commit is contained in:
Carl Love
parent
459d52ec1f
commit
2a88a98f5b
22
configure.ac
22
configure.ac
@ -1455,7 +1455,9 @@ AC_HWCAP_CONTAINS_FLAG([arch_2_05],[HWCAP_HAS_ISA_2_05])
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AC_HWCAP_CONTAINS_FLAG([arch_2_06],[HWCAP_HAS_ISA_2_06])
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AC_HWCAP_CONTAINS_FLAG([arch_2_07],[HWCAP_HAS_ISA_2_07])
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AC_HWCAP_CONTAINS_FLAG([arch_3_00],[HWCAP_HAS_ISA_3_00])
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AC_HWCAP_CONTAINS_FLAG([arch_3_01],[HWCAP_HAS_ISA_3_1])
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AC_HWCAP_CONTAINS_FLAG([htm],[HWCAP_HAS_HTM])
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AC_HWCAP_CONTAINS_FLAG([mma],[HWCAP_HAS_MMA])
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# ISA Levels
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AM_CONDITIONAL(HAS_ISA_2_05, [test x$HWCAP_HAS_ISA_2_05 = xyes])
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@ -1624,7 +1626,7 @@ AM_CONDITIONAL(SUPPORTS_HTM, test x$ac_compiler_supports_htm = xyes \
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-a x$ac_compiler_sees_htm_builtins = xyes \
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-a x$HWCAP_HAS_HTM = xyes )
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# isa 3.0 checking
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# isa 3.0 checking. (actually 3.0 or newer)
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AC_MSG_CHECKING([that assembler knows ISA 3.00 ])
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AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[
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@ -1638,9 +1640,27 @@ ac_asm_have_isa_3_00=no
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AC_MSG_RESULT([no])
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])
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# isa 3.01 checking
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AC_MSG_CHECKING([that assembler knows ISA 3.1 ])
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AC_COMPILE_IFELSE([AC_LANG_PROGRAM([[
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]], [[
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__asm__ __volatile__("brh 1,2 ");
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]])], [
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ac_asm_have_isa_3_1=yes
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AC_MSG_RESULT([yes])
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], [
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ac_asm_have_isa_3_1=no
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AC_MSG_RESULT([no])
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])
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AM_CONDITIONAL(HAS_ISA_3_00, [test x$ac_asm_have_isa_3_00 = xyes \
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-a x$HWCAP_HAS_ISA_3_00 = xyes])
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AM_CONDITIONAL(HAS_ISA_3_1, [test x$ac_asm_have_isa_3_1 = xyes \
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-a x$HWCAP_HAS_ISA_3_1 = xyes])
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# Check for pthread_create@GLIBC2.0
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AC_MSG_CHECKING([for pthread_create@GLIBC2.0()])
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@ -3,7 +3,7 @@ include $(top_srcdir)/Makefile.tool-tests.am
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dist_noinst_SCRIPTS = filter_stderr
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noinst_HEADERS = ppc64_helpers.h
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noinst_HEADERS = ppc64_helpers.h isa_3_1_helpers.h
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EXTRA_DIST = \
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jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest jm-int.stdout.exp-LE \
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@ -51,6 +51,11 @@ EXTRA_DIST = \
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test_isa_3_0_other.stdout.exp-LE test_isa_3_0_other.vgtest \
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subnormal_test.stderr.exp subnormal_test.stdout.exp \
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subnormal_test.vgtest
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# test_isa_3_1_RT.vgtest test_isa_3_1_RT.stderr.exp test_isa_3_1_RT.stdout.exp
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# test_isa_3_1_XT.vgtest test_isa_3_1_XT.stderr.exp test_isa_3_1_XT.stdout.exp
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# test_isa_3_1_VRT.vgtest test_isa_3_1_VRT.stderr.exp test_isa_3_1_VRT.stdout.exp
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# test_isa_3_1_Misc.vgtest test_isa_3_1_Misc.stderr.exp test_isa_3_1_Misc.stdout.exp
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# test_isa_3_1_AT.vgtest test_isa_3_1_AT.stderr.exp test_isa_3_1_AT.stdout.exp
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check_PROGRAMS = \
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allexec \
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@ -63,7 +68,8 @@ check_PROGRAMS = \
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test_tm test_touch_tm ldst_multiple data-cache-instructions \
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power6_mf_gpr std_reg_imm \
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twi_tdi tw_td power6_bcmp
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# test_isa_3_1_RT test_isa_3_1_XT
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# test_isa_3_1_Misc test_isa_3_1_VRT test_isa_3_1_AT
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AM_CFLAGS += @FLAG_M64@
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AM_CXXFLAGS += @FLAG_M64@
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@ -71,6 +77,12 @@ AM_CCASFLAGS += @FLAG_M64@
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allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
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#test_isa_3_1_XT_SOURCES = test_isa_3_1_XT.c test_isa_3_1_common.c
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#test_isa_3_1_RT_SOURCES = test_isa_3_1_RT.c test_isa_3_1_common.c
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#test_isa_3_1_VRT_SOURCES = test_isa_3_1_VRT.c test_isa_3_1_common.c
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#test_isa_3_1_AT_SOURCES = test_isa_3_1_AT.c test_isa_3_1_common.c
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#test_isa_3_1_Misc_SOURCES = test_isa_3_1_Misc.c test_isa_3_1_common.c
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if HAS_ALTIVEC
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BUILD_FLAG_ALTIVEC = -maltivec
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ALTIVEC_FLAG = -DHAS_ALTIVEC
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@ -128,6 +140,14 @@ BUILD_FLAGS_ISA_3_00 =
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ISA_3_00_FLAG =
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endif
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if HAS_ISA_3_1
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BUILD_FLAGS_ISA_3_1 = -mcpu=power10
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ISA_3_1_FLAG = -DHAS_ISA_3_1
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else
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BUILD_FLAGS_ISA_3_1 =
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ISA_3_1_FLAG =
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endif
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test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
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@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
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@ -161,6 +181,9 @@ test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG)
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test_isa_3_0_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_00_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_ISA_3_00)
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test_isa_3_1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_3_1_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_ISA_3_1)
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subnormal_test_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) $(ISA_2_06_FLAG) \
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@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX) $(BUILD_FLAGS_ISA_2_06)
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112
none/tests/ppc64/isa_3_1_helpers.h
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112
none/tests/ppc64/isa_3_1_helpers.h
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@ -0,0 +1,112 @@
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/* isa_3_1_helpers.h */
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#include "isa_3_1_register_defines.h"
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extern unsigned long a_iters,b_iters,c_iters, m_iters;
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extern unsigned long vrai,vrbi,vrci,vrmi;
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extern unsigned long a_inc, b_inc, c_inc, m_inc;
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extern unsigned long a_limit,b_limit,c_limit;
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extern vector unsigned long long vrt, vra, vrb, vrc;
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extern vector unsigned long long vrm;
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extern vector unsigned long long vec_xa;
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extern vector unsigned long long vec_xb;
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extern vector unsigned long long vec_xc;
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extern vector unsigned long long vec_xs;
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extern vector unsigned long long vec_xt;
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extern unsigned long long dcmx;
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extern unsigned long current_cr;
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extern unsigned long current_fpscr;
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typedef void (*test_func_t) (void);
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struct test_list_t {
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test_func_t func;
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const char *name;
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const char *form;
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unsigned long mask; /* holds SP or DP indicators. */
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};
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typedef struct test_list_t test_list_t;
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extern struct test_list_t current_test;
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typedef void (*test_group_t) (const char *name, test_func_t func,
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unsigned int unused, char * cur_form);
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/* Misc options for debug. */
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/* setup_only indicates to do all of the register initializations,
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but skip the instruction test. */
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extern unsigned long setup_only;
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extern int verbose;
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extern unsigned long prefix_override;
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extern unsigned long vrm_override;
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extern unsigned long mc_override;
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extern unsigned long enable_setjmp;
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extern unsigned long dump_tables;
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extern void debug_show_form(const char *, char *);
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extern void debug_show_current_iteration();
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extern void debug_dump_buffer();
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extern void identify_form_components(const char *, const char *);
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extern void dump_vsxargs();
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extern void generic_prologue();
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extern void build_args_table();
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extern void build_vsx_table();
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extern void print_register_header();
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extern void print_register_footer();
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extern void debug_show_iter_ranges();
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extern void print_result_buffer();
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extern void dump_float_vsx_tables();
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extern void build_float_vsx_tables();
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extern void initialize_target_registers();
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extern void initialize_source_registers();
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extern void set_up_iterators();
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extern void initialize_buffer(int);
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extern int verbose;
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#define debug_printf(X) if (verbose>0) printf(X);
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#define debug_show_labels (verbose>0)
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#define debug_show_iters (verbose>1)
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#define debug_show_raw_values (verbose>2)
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#define debug_show_all_regs (verbose>5)
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#define debug_show_tables (verbose>6)
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#define CHECK_OVERRIDES { \
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if (vrm_override && vrmi > 0) continue; \
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if (prefix_override && strncmp("p", instruction_name, 1) == 0) { \
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if (verbose) printf("Skipping prefix insn test %s\n",instruction_name); \
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continue; \
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} \
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}
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/* CR helpers. */
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#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
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#define SET_CR(_arg) \
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__asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
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#define SET_CR0_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x80,%0 " : : "b" (_arg):"cr0");
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#define SET_CR1_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x40,%0 " : : "b" (_arg):"cr1");
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#define SET_CR2_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x20,%0 " : : "b" (_arg):"cr2");
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#define SET_CR3_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x10,%0 " : : "b" (_arg):"cr3");
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#define SET_CR4_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x08,%0 " : : "r" (_arg):"cr4");
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#define SET_CR5_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x04,%0 " : : "r" (_arg):"cr5");
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#define SET_CR6_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x02,%0 " : : "r" (_arg):"cr6");
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#define SET_CR7_FIELD(_arg) __asm__ __volatile__ ("mtocrf 0x01,%0 " : : "r" (_arg):"cr7");
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#define SET_XER(_arg) __asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
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#define GET_CR(_lval) __asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
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#define GET_XER(_lval) __asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
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#define SET_CR_ZERO SET_CR(0)
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/* ************** */
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/* FPSCR helpers. */
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#define SET_FPSCR_ZERO \
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do { \
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double _d = 0.0; \
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__asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
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} while (0);
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#define GET_FPSCR(_arg) \
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__asm__ __volatile__ ("mffs %0" : "=f"(_arg) );
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50
none/tests/ppc64/isa_3_1_register_defines.h
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50
none/tests/ppc64/isa_3_1_register_defines.h
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@ -0,0 +1,50 @@
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/* register definitions used in tests for isa_3_1. */
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/* ACC / Accumulator.
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An ACC is associated with a set of four VSR registers.
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Each ACC contains four 128-bit rows.
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Each row of each ACC is aliased to a specific VSR in the following manner.
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ACC[0][0] == VSR[0]; ACC[0][1] == VSR[1]; ACC[0][2] == VSR[2]; ACC[0][3] == VSR[3]
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...
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ACC[7][0] == VSR[28]; ACC[7][0] == VSR[28]; ACC[7][0] == VSR[28]; ACC[7][0] == VSR[28]
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*/
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#define ACCNUM 4
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register vector long long TEST_ACC0 __asm__ ("vs16");
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register vector long long TEST_ACC1 __asm__ ("vs17");
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register vector long long TEST_ACC2 __asm__ ("vs18");
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register vector long long TEST_ACC3 __asm__ ("vs19");
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/* XSp and XTp use the same register pair, defined here as 20 and 21.
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{ also XSp,XTp in scripts } */
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register vector long long XTp0 __asm__ ("vs20"); // XTp[0];XSp[0];
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register vector long long XTp1 __asm__ ("vs21"); // XTp[1];XSp[1];
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// xa,xb,xc references are mapped to a specific vector register.
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// out of order to allow xap mapped over xa and xc.
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register vector long long xa __asm__ ("vs22"); // also xap.
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register vector long long xc __asm__ ("vs23"); // also 2nd half of xap.
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register vector long long xb __asm__ ("vs24");
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register vector long long xt __asm__ ("vs25");
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/* frs,frb (variable named frsb) both use the same register pair.
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(top half of vs26,vs27) */
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register double frsb __asm__ ("fr26");
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register double frsbp __asm__ ("fr27");
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/* frt,frtp register pair. (top half of vs28,vs29) */
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register double frt __asm__ ("vs28");
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register double frtp __asm__ ("vs29");
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register uint64_t ra __asm__ ("r20");
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register uint64_t rb __asm__ ("r21");
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register uint64_t rc __asm__ ("r22");
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register uint64_t rs __asm__ ("r24"); /* rsp part 1 */
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register uint64_t rsp __asm__ ("r25"); /* rsp part 2 */
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register uint64_t rt __asm__ ("r26"); /* rtp part 1 */
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register uint64_t rtp __asm__ ("r27"); /* rtp part 2 */
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extern unsigned long long vsrd;
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extern unsigned long get_vsrhd_vs26();
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extern unsigned long get_vsrhd_vs27();
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extern unsigned long get_vsrhd_vs28();
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extern unsigned long get_vsrhd_vs29();
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3
none/tests/ppc64/test_isa_3_1_AT.vgtest
Normal file
3
none/tests/ppc64/test_isa_3_1_AT.vgtest
Normal file
@ -0,0 +1,3 @@
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prereq: ../../../tests/check_ppc64_auxv_cap arch_3_1
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prereq: ../../../tests/check_ppc64_auxv_cap mma
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prog: test_isa_3_1_AT
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2
none/tests/ppc64/test_isa_3_1_Misc.vgtest
Normal file
2
none/tests/ppc64/test_isa_3_1_Misc.vgtest
Normal file
@ -0,0 +1,2 @@
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prereq: ../../../tests/check_ppc64_auxv_cap arch_3_1
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prog: test_isa_3_1_Misc
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2
none/tests/ppc64/test_isa_3_1_RT.vgtest
Normal file
2
none/tests/ppc64/test_isa_3_1_RT.vgtest
Normal file
@ -0,0 +1,2 @@
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prereq: ../../../tests/check_ppc64_auxv_cap arch_3_1
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prog: test_isa_3_1_RT
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2
none/tests/ppc64/test_isa_3_1_VRT.vgtest
Normal file
2
none/tests/ppc64/test_isa_3_1_VRT.vgtest
Normal file
@ -0,0 +1,2 @@
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prereq: ../../../tests/check_ppc64_auxv_cap arch_3_1
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prog: test_isa_3_1_VRT
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2
none/tests/ppc64/test_isa_3_1_XT.vgtest
Normal file
2
none/tests/ppc64/test_isa_3_1_XT.vgtest
Normal file
@ -0,0 +1,2 @@
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prereq: ../../../tests/check_ppc64_auxv_cap arch_3_1
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prog: test_isa_3_1_XT
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2188
none/tests/ppc64/test_isa_3_1_common.c
Normal file
2188
none/tests/ppc64/test_isa_3_1_common.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -15,8 +15,10 @@ P_HWCAP_1=" vsx arch_2_06 power6x dfp pa6t arch_2_05 ic_snoop smt booke"
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P_HWCAP_2=" cellbe power5+ power5 power4 notb efpdouble efpsingle spe"
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P_HWCAP_3=" ucache 4xxmac mmu fpu altivec ppc601 ppc64 ppc32 "
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P_HWCAP2_1=" tar isel ebb dscr htm arch_2_07 arch_3_00 "
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# Additional entries as of ... future
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P_HWCAP2_2=" arch_3_1 mma "
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CAPABILITY_FOUND="no"
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for POTENTIAL_CAP in $P_HWCAP_1 $P_HWCAP_2 $P_HWCAP_3 $P_HWCAP2_1 ; do
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for POTENTIAL_CAP in $P_HWCAP_1 $P_HWCAP_2 $P_HWCAP_3 $P_HWCAP2_1 $P_HWCAP2_2 ; do
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if [ "x$CAPABILITY_WORD" = "x$POTENTIAL_CAP" ]; then
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CAPABILITY_FOUND="yes"
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break
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