The patch was submitted by Will Schmidt (will_schmidt@vnet.ibm.com).
A handful of cosmetic changes to the ppc32 and ppc64 makefiles.
Cleans up some whitespace issues, spaces/tabs/etc,
Rearranges some of the contents so they are logically group, and
more consistent between the 32- and 64- bit versions of the same.
Bugzilla 34979
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15425
The patch was submitted by Will Schmidt (will_schmidt@vnet.ibm.com).
Patches 4 and 5 need to be applied together. Add convenience function
for processing hwcap entries. Add logic to check for HTM support in compiler.
Bugzilla 34979
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15423
The patch was submitted by Will Schmidt (will_schmidt@vnet.ibm.com).
Update all vgtest files to reference the new capability check helper.
This includes a few adjustments to ensure the test is checking for
the specific capability. I.e. isa_2_07 is a requirement for htm, but
does not indicate htm support is actually present.
Bugzilla 34979
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15421
The new script (tests/check_ppc64_auxv_cap) in the first patch was
written for the bash shell. I was told by fkrohm that there was an
issue with bash sometime ago and the decision was to use sh instead.
sh maps to bash on a lot of systems but on some it maps to dash. The
script is not compatible with dash.
In retesting the second patch with a fresh svn pull, I found that I
forgot to do the svn add for the new script file. Which causes the
regression test to fail with the second patch applied.
So, I have decided it will be best to just back out patch 1 and 2 for now.
I will fix the script and do this again.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15390
Update all vgtest files to reference the new capability check helper.
This includes a few adjustments to ensure the test is checking for
the proper capability. (i.e. htm versus isa_2_07).
Patch 1 valgrind commit id 15388.
The bugzilla for this commit is 349790
Patch submitted by Will Schmidt <will_schmidt@vnet.ibm.com>
Reviewed and tested by Carl Love <cel@ibm.com>
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15389
Add a helper script to determine if the platform is ppc64le.
This is specifically used to help exclude the 32-bit tests from being
run on a ppc64LE (ABIV2) platform. The 32-bit targets, specifically ppc32/*
is not built on LE.
This patch fixes Vagrind bugzilla 347322.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15188
are aligned with GCC 5.0. The compiler generates a "note" about this starting
with GCC 4.9. To avoid generating the "note", the passing of the arguments
were changed to a pointer to make it pass by reference rather then pass by
value.
bugzilla 346487.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15136
One of the expect files was missing. Also found that there
was a bug in the stq, stqcx, lq and lqarx instructions for LE.
The VEX commit for the instruction fix was 3138.
This commit updates the expect files for the corrected instructions
and adds the missing expect files.
The bugzilla for the orginal issue of the missing instructions
is 346324.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15120
The instructions are part of the ISA 2.06 but were not implemented
in all versions of hardware. The four instructions are all supported
in ISA 2.07. The instructions were put under the ISA 2.07 category
of supported instructions in this patch.
The VEX commit for this fix is r3137.
The bugzilla for this issue is 346324.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15106
none/tests/ppc32/jm-insns.c and none/tests/ppc64/jm-insns.c.
The BE and LE output expect files are updated as well.
There is no Bugzilla related to this update. The issue
was found and the initial patch and BE output update
was done by Florian Krohm <florian@eich-krohm.de>.
Carl Love <cel@us.ibm.com> added the LE output update.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14466
There are two copies of the round test in none/tests/ppc32/round.c
and none/tests/ppc64/round.c. The two source files should be
identical. The LE functional test commit updated the round.c test for
ppc64 but was missing the ppc32 round updates. The round.c test was
updated to fix an issue where we were getting different outputs
depending on the compiler. The output is now consistent for the
compilers allowing the removal of the additional expect files for
ppc32 and ppc64.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14278
to add PPC64 LE support. The other two patches can be found in Bugzillas
334384 and 334834. Note, there are no VEX changes in this patch.
PP64 Little Endian test case fixes.
This patch adds new LE and BE expect files where needed. In other
cases, the test was fixed to run correctly on LE and BE using based on
testing to see which platform is being used.
Where practical, the test cases have been changed so that the output
produced for BE and LE will be identical. The test cases that require
a major rewrite to make the output identical for BE and LE simply
had an additional expect file added.
Signed-off-by: Carl Love <carll@us.ibm.com>
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14240
Other functions already explicitly omitted the frame pointer. Also
do that for main to prevent gcc 4.8.2 complaining:
ldst_multiple.c: In function ‘main’:
ldst_multiple.c:180:5: error: frame pointer required, but reserved
int main(void)
^
ldst_multiple.c:31:18: note: for ‘r31’
register HWord_t r31 asm("r31");
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14173
instruction: dcbzl" submitted by Anmol P. Paralkar <paralkar@freescale.com>
The patch adds the following files:
none/tests/ppc64/data-cache-instructions.vgtest
none/tests/ppc64/data-cache-instructions.c
none/tests/ppc64/data-cache-instructions.stdout.exp
none/tests/ppc64/data-cache-instructions.stderr.exp
none/tests/ppc32/data-cache-instructions.stdout.exp
none/tests/ppc32/data-cache-instructions.c
none/tests/ppc32/data-cache-instructions.vgtest
none/tests/ppc32/data-cache-instructions.stderr.exp
tests/power_insn_available.c
The following files are modified:
none/tests/ppc32/Makefile.am
none/tests/ppc64/Makefile.am
tests/Makefile.am
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13791
instructions.
The patch also adds ppc32 and ppc64 test cases for the instructions.
The patch is a fix for bugzilla 329956 "valgrind crashes when lmw/stmw instructions are used on ppc64".
The VEX code commit is 2802
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13780
vaddcuq, vadduqm, vaddecuq, vaddeuqm,
vsubcuq, vsubuqm, vsubecuq, vsubeuqm,
vbpermq and vgbbd.
The completes adding the Power ISA 2.07 support.
Bugzilla 325816
VEX commit id 2790
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13653
This commit adds the testcases for the following instructions:
vpmsumb, vpmsumh, vpmsumw, vpmsumd, vpermxor, vcipher, vcipherlast,
vncipher, vncipherlast, vsbox,
vclzb, vclzw, vclzh, vclzd,
vpopcntb, vpopcnth, vpopcntw, vpopcntd,
vnand, vorc, veqv,
vshasigmaw, vshasigmad,
bcdadd, bcdsub
The VEX commit that added the support for the above instructions was
commit 2789.
The patch is for Bugzilla 325628
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13646
The initial Transactional Memory instruction patch did not include the two
privileged (OS) instructions treclaim and trechkpt. VEX commit 2784 added
the support for these two instructions.
This patch adds a touch test to make sure all of the POWER Transactional
memory instrutions are recognized by Valgrind. All of the the Transactional
Memory instructions, with the exception of tbegin, are treated as NOPs in the
first implementation. The tbegin instruction causes the transaction to fail
thus no additional Transactional Memory instructions on the successful
transaction path would be executed in a real program. This test just makes
sure each instruction is actually recognized by Valgrind.
The patch if for Bugzilla 325751.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13630
This patch adds testcases for the following instructions added
in phase 4. The instructions are for doing various arithmetic,
logic, and load/store VSX operations:
xscvsxdsp xscvuxdsp xsaddsp xssubsp xsdivsp xsmaddasp xsmaddmsp
xsmsubasp xsmsubmsp xsnmaddasp xsnmaddmsp xsnmsubasp xsnmsubmsp
xsmulsp xssqrtsp xsresp xsrsqrtesp xsrsp xxlorc xxlnand xxleqv
lxsiwzx lxsiwax lxsspx stxsiwx stxsspx
Signed-off-by: Maynard Johnson <maynardj@us.ibm.com>
VEX commit for the instruction support r2781
Bugzilla 325477
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13611
compilers as the -mhtm flag is not known. The patch fixes the makefile
issue and addes #defines to the testcase code.
The testcase was added in valgrind commit 13607.
The bugzilla for adding the TM instruction support is 323803
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13608
The test case for the transaction memory instructions executes the
failure path when run under valgrind. This is since the initial
Transaction Memory implemnetation is to simply fail the TBEGIN instruction
forcing the execution flow to take the failure path. When the
test case is executed on the real hardware, the success path will
be taken. Only the TBEGIN instruction actually does anything. All other
transactional memory instructions are NOPs since only failure path is executed
and it assumed to not have any transactional memory instructions on it.
Signed-off-by: Carl Love <cel@us.ibm.com>
VEX commit revision 2780
Bugzilla 323803
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13607
This patch adds testcases to an existing testcase
source file to test the new instructions which were
added to VEX support in the phase 3 ISA 2.07 code patch.
The patch also makes a small change to memcheck's
vbit tester code to allow successful execution.
Signed-off-by: Maynard Johnson <maynardj@us.ibm.com>
Bugzilla 324894. Corresponding VEX commit 2779
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13594
The assembly of these instructions is not alwasy being done correctly as
described in the following email reply.
Re: Assembling Power instructions: dcbtst/dcbt.
From: Peter Bergner <bergner at vnet dot ibm dot com>
To: Paralkar Anmol-B07584 <B07584 at freescale dot com>
Cc: "amodra at bigpond dot net dot au" <amodra at bigpond dot net dot au>, "binutils at sourceware dot org" <binutils at sourceware dot org>
Date: Fri, 13 Sep 2013 15:22:35 -0500
Subject: Re: Assembling Power instructions: dcbtst/dcbt.
Authentication-results: sourceware.org; auth=none
References: <DC6D7B34688246489A6578981A5ADEB9302A07 at 039-SN2MPN1-012 dot 039d dot mgd dot msft dot net>
On Fri, 2013-09-13 at 18:32 +0000, Paralkar Anmol-B07584 wrote:
> Hello,
>
> Per Power ISA Version 2.07 (May 3, 2013) "4.3.2 Data Cache Instructions",
> the assembly language syntax for the dcbtst instruction (pp. 771) is:
>
> dcbtst RA,RB,TH [Category: Server]
> dcbtst TH,RA,RB [Category: Embedded]
>
> and it's layout in the object code is:
>
> +------+------+------+------+------------+---+
> | 31 | TH | RA | RB | 246(0xF6) | / |
> |0 |6 |11 |16 |21 |31 |
> +------+------+------+------+------------+---+
>
> (Analogously: dcbt pp. 770)
>
> However, GAS (as of version 2.23.52.20130912) decides on the syntax to use based on
> processor/architecture dialect (not Power ISA Category), using the Server syntax in
> the case of POWER4 and the Embedded syntax for generic PPC or VLE.
That was a bug fixed here:
https://sourceware.org/ml/binutils/2012-11/msg00352.html
> Consequently (e.g.),
>
> dcbtst 17, 14, 6
>
> in the assembly file gets "misassembled" under -many for a user-space program on Linux:
When you only specify -many (and not one of -mpower4, -mpower5, etc.),
the assembler/disassembler will choose a default -m<CPU> value for
you. That has changed over time, but is generally one of the newer
server cpus. For example, for binutils trunk, the default is now
-mpower8 and for your 2.23.x binutils, it is -mpower7.
That should force the assembler and disassembler to assemble
the instruction using the server operand order you want, but the bug
above (which is in 2.23) basically resets it to an old cpu, so it
chooses to use the embedded/old cpu setting.
The patch from Amodra fixes the issue by manually generating the correct
hex value for the instruction rather then leaving it to the assembler to
generate the hex value from the symbolic assembly instruction name.
This is the fix for Bugzilla 324765.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13562
behavior of the xscvspdp instruction, indicating that if the source argument
is a SNaN, it is first changed to a QNaN before being converted from
single-precision to double-precision. This updated information about the
xscvspdp instruction exposed a bug in the VEX implementation for that
instruction and also a bug in the testing for all instructions having
special behavior for single-precision SNaN arguments.
The VEX code fix for this issue is r2760.
This patch fixes the test cases for the ISA 2.07.
Testing bug: In several ppc[64] test cases, an array of special
double-precision floating point values is set up, and then all elements of
that array are copied via assignment to a single-precision array ('float'
type). Assignment from a double to a float works fine for all cases, except for
SNaN values. In the case of a SNaN, the source is changed to a QNaN and then
converted to single-precision. So the end result was that our array of floats
did not have an actual SNaN value, and, therefore, any instructions that had
special behavior for a single-precision SNaN input argument was never being
properly tested. This patch makes some functional changes in the following
testcases:
none/tests/ppc[32|64]/test_isa_2_06_part2.c
none/tests/ppc[32|64]/test_isa_2_06_part3.c
none/tests/ppc[32|64]/test_isa_2_07_part2.c
These changes impacted the associated *.stdout.exp files, so the patch also
updates those files. Additionally, there were several errors in testcase
source comments that misidentified QNaN and SNaN bit patterns which this patch
corrects.
See bugzilla 324816.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13544
Power ISA 2.07. The first bugzilla in the series was: 322294: Add initial
support for IBM Power ISA 2.07
Phase 2 VEX commit 2756 added support for the following new instructions to
VEX/priv/guest_ppc_toIR.c:
- lq, stq, lqarx, stqcx.
- mfvsrwz, mtvsrwz
- fmrgew, fmrgow
This commit adds the corresponding test cases for these instructions.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13539
under the case PPCG_FLAG_OP_MULLW: does not apply to the mulldo as we need to
detect overflow when performing a Multiply Low Doubleword (not Multiply Low
Word). Hence, we added a new enumeration value PPCG_FLAG_OP_MULLD in
VEX/priv/guest_ppc_defs.h and a corresponding new case under which the
computation for detecting overflow for mulldo/mulldo. is added in
set_XER_OV_64(). The tests have been added to: none/tests/ppc32/jm-insns.c
Vex commit 2754 for the source code fix
This commit adds the test cases.
Bugzilla 324594, submitted by Anmol P. Paralkar
Patch reviewed and tested by Carl Love
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13537
dcbt instruction, which is valid for several forms of data cache block
touch instructions. The VEX commit 2761 fixed the missing support in
VEX/priv/guest_ppc_toIR.c. This commit adds tests for the the non-zero
fields to the test cases for 32 and 64-bit modes.
Bugzilla 324518
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13534
incorrectly set to FLAG_M64 instead of FLAG_M32. Fixed the flag. The
issue was reported in Bugzilla 324546.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13533
The IBM Power ISA 2.07 has been published on power.org, and IBM's new POWER8
processor is under development to implement that ISA. This patch provides
initial runtime and testsuite support for running Valgrind on POWER8 systems
running a soon-to-be released Linux distribution. This Linux distro will
include a POWER8-tuned libc that uses a subset of the new instructions from
ISA 2.07. Since virtually all applications link with libc, it would be
impossible to run an application under Valgrind on this distro without adding
support for these new instructions to Valgrind, so that's the intent of this
patch. Note that applications built on this distro will *not* employ new POWER8
instructions by default. There are roughly 150 new instructions in the Power
ISA 2.07, including hardware transaction management (HTM). Support for these
new instructions (modulo the subset included in this bug) will be added to
Valgrind in a phased approach, similar to what we did for Power ISA 2.06.
Bugzilla 322294, VEX commit 2740
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13494
The frsqrte and vrefp instructions produce an approximate result.
According to the ISA document for the POWER processor, the result will
vary in its precision for different processor implementations. This patch
fixes the masks to be applied to the results to remove the variability
in the results. The expected output files are also updated to reflect the
change in the result given the new masking of the result.
patch from Carl Love <cel@us.ibm.com>
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12720
(Carl Love, carll@us.ibm.com and Maynard Johnson, maynardj@us.ibm.com)
This patch adds support for Power Decimal Floating Point (DFP) . This
is the fifth patch set in the series of five to add the DFP
instruction support to Valgrind. Adds support for the ddedpd,
ddedpdq, denbcd, denbcdq, dtstsf, and dtstsfq instructions.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12603
test group and test exponent instructions dtstdc, dtstdcq, dtstdg,
dtstdgq, dtstex and dtstexq. Bug #298862. (Carl Love,
carll@us.ibm.com and Maynard Johnson, maynardj@us.ibm.com)
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12546
instruction support -- VEX side changes. See #295221.
This patch adds test cases. Also adds some minor Memcheck
instrumentation tweaks necessitated by the IR changes.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12476
rev 12001 has introduced a regression in VG_(env_remove_valgrind_env_stuff):
to avoid modifying a possibly read-only env string, the string is duplicated,
and the copy is modified. However, mash_env_column modifies the string
"in-place". The modified string was not put back in the env (and could not,
because the src string is only partially copied).
This means that the valgrind preload strings were not cleaned up and
when a 32 bit executable execs a 64 bits (or vice versa: 64 bit execs 32 bits),
LD_PRELOAD contains both the 32 bits and 64 bits versions of Valgrind
vgpreload.... => ld.so then gives an error msg, as it can't preload either
the 32 or the 64 bits version.
The patch fixes this by duplicating the whole env string, and passing
to mash_colon_env a pointer to the correct offset in the whole env string.
The duplicated string is replacing the original entry in envp.
This patch adds two regression tests : none/tests/allexec32 and
none/tests/allexec64. On a bi-arch valgrind, these will be 32bits and 64 bits
executables, exec-ing each other. On a single arch, one will be a symlink
to the other (to avoid different .exp files, and still test exec).
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12287
