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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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Add DFP test cases that accidentally missed in r12546.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12547
This commit is contained in:
Julian Seward
parent
6e0e5e15c5
commit
52df50db1b
626
none/tests/ppc32/test_dfp4.c
Normal file
626
none/tests/ppc32/test_dfp4.c
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@ -0,0 +1,626 @@
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/* Copyright (C) 2012 IBM
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Author: Maynard Johnson <maynardj@us.ibm.com>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#if defined(HAS_DFP)
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typedef union stuff {
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_Decimal64 dec_val;
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_Decimal128 dec_val128;
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unsigned long long u64_val;
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struct {
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unsigned long long valu;
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unsigned long long vall;
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} u128;
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} dfp_val_t;
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typedef unsigned char Bool;
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#define True 1
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#define False 0
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#define ALLCR "cr0","cr1","cr2","cr3","cr4","cr5","cr6","cr7"
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#define SET_CR(_arg) \
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__asm__ __volatile__ ("mtcr %0" : : "b"(_arg) : ALLCR );
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#define SET_XER(_arg) \
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__asm__ __volatile__ ("mtxer %0" : : "b"(_arg) : "xer" );
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#define GET_CR(_lval) \
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__asm__ __volatile__ ("mfcr %0" : "=b"(_lval) )
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#define GET_XER(_lval) \
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__asm__ __volatile__ ("mfxer %0" : "=b"(_lval) )
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#define GET_CR_XER(_lval_cr,_lval_xer) \
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do { GET_CR(_lval_cr); GET_XER(_lval_xer); } while (0)
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#define SET_CR_ZERO \
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SET_CR(0)
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#define SET_XER_ZERO \
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SET_XER(0)
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#define SET_CR_XER_ZERO \
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do { SET_CR_ZERO; SET_XER_ZERO; } while (0)
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#define SET_FPSCR_ZERO \
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do { double _d = 0.0; \
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__asm__ __volatile__ ("mtfsf 0xFF, %0" : : "f"(_d) ); \
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} while (0)
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#define GET_FPSCR(_arg) \
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__asm__ __volatile__ ("mffs %0" : "=f"(_arg) )
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#define SET_FPSCR_DRN \
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__asm__ __volatile__ ("mtfsf 1, %0, 0, 1" : : "f"(f14) )
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// The assembly-level instructions being tested
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/* In _test_dtstdc[q], DCM can be one of 6 possible data classes, numbered 0-5.
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* In reality, DCM is a 6-bit mask field. We just test the individual values
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* and assume that masking multiple values would work OK.
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* BF is the condition register bit field which can range from 0-7. But for
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* testing purposes, we only use BF values of '0' and '5'.
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*/
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static void _test_dtstdc(int BF, int DCM, dfp_val_t val1, dfp_val_t x1 __attribute__((unused)))
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{
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_Decimal64 f14 = val1.dec_val;
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if (DCM < 0 || DCM > 5 || !(BF == 0 || BF == 5)) {
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fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DCM);
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return;
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}
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switch (DCM) {
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case 0:
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if (BF)
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__asm__ __volatile__ ("dtstdc 5, %0, 1" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdc 0, %0, 1" : : "f" (f14));
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break;
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case 1:
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if (BF)
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__asm__ __volatile__ ("dtstdc 5, %0, 2" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdc 0, %0, 2" : : "f" (f14));
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break;
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case 2:
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if (BF)
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__asm__ __volatile__ ("dtstdc 5, %0, 4" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdc 0, %0, 4" : : "f" (f14));
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break;
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case 3:
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if (BF)
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__asm__ __volatile__ ("dtstdc 5, %0, 8" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdc 0, %0, 8" : : "f" (f14));
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break;
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case 4:
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if (BF)
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__asm__ __volatile__ ("dtstdc 5, %0, 16" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdc 0, %0, 16" : : "f" (f14));
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break;
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case 5:
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if (BF)
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__asm__ __volatile__ ("dtstdc 5, %0, 32" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdc 0, %0, 32" : : "f" (f14));
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break;
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default:
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break;
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}
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}
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static void _test_dtstdcq(int BF, int DCM, dfp_val_t val1, dfp_val_t x1 __attribute__((unused)))
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{
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_Decimal128 f14 = val1.dec_val128;
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if (DCM < 0 || DCM > 5 || !(BF == 0 || BF == 5)) {
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fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DCM);
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return;
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}
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switch (DCM) {
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case 0:
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if (BF)
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__asm__ __volatile__ ("dtstdcq 5, %0, 1" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdcq 0, %0, 1" : : "f" (f14));
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break;
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case 1:
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if (BF)
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__asm__ __volatile__ ("dtstdcq 5, %0, 2" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdcq 0, %0, 2" : : "f" (f14));
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break;
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case 2:
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if (BF)
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__asm__ __volatile__ ("dtstdcq 5, %0, 4" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdcq 0, %0, 4" : : "f" (f14));
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break;
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case 3:
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if (BF)
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__asm__ __volatile__ ("dtstdcq 5, %0, 8" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdcq 0, %0, 8" : : "f" (f14));
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break;
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case 4:
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if (BF)
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__asm__ __volatile__ ("dtstdcq 5, %0, 16" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdcq 0, %0, 16" : : "f" (f14));
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break;
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case 5:
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if (BF)
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__asm__ __volatile__ ("dtstdcq 5, %0, 32" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdcq 0, %0, 32" : : "f" (f14));
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break;
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default:
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break;
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}
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}
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/* In _test_dtstdg[q], DGM can be one of 6 possible data groups, numbered 0-5.
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* In reality, DGM is a 6-bit mask field. We just test the individual values
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* and assume that masking multiple values would work OK.
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* BF is the condition register bit field which can range from 0-7. But for
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* testing purposes, we only use BF values of '0' and '5'.
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*/
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static void _test_dtstdg(int BF, int DGM, dfp_val_t val1, dfp_val_t x1 __attribute__((unused)))
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{
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_Decimal64 f14 = val1.dec_val;
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if (DGM < 0 || DGM > 5 || !(BF == 0 || BF == 5)) {
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fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DGM);
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return;
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}
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switch (DGM) {
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case 0:
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if (BF)
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__asm__ __volatile__ ("dtstdg 5, %0, 1" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdg 0, %0, 1" : : "f" (f14));
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break;
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case 1:
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if (BF)
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__asm__ __volatile__ ("dtstdg 5, %0, 2" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdg 0, %0, 2" : : "f" (f14));
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break;
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case 2:
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if (BF)
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__asm__ __volatile__ ("dtstdg 5, %0, 4" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdg 0, %0, 4" : : "f" (f14));
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break;
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case 3:
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if (BF)
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__asm__ __volatile__ ("dtstdg 5, %0, 8" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdg 0, %0, 8" : : "f" (f14));
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break;
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case 4:
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if (BF)
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__asm__ __volatile__ ("dtstdg 5, %0, 16" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdg 0, %0, 16" : : "f" (f14));
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break;
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case 5:
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if (BF)
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__asm__ __volatile__ ("dtstdg 5, %0, 32" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdg 0, %0, 32" : : "f" (f14));
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break;
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default:
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break;
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}
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}
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static void _test_dtstdgq(int BF, int DGM, dfp_val_t val1, dfp_val_t x1 __attribute__((unused)))
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{
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_Decimal128 f14 = val1.dec_val128;
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if (DGM < 0 || DGM > 5 || !(BF == 0 || BF == 5)) {
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fprintf(stderr, "Invalid inputs to asm test: a=%d, b=%d\n", BF, DGM);
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return;
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}
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switch (DGM) {
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case 0:
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if (BF)
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__asm__ __volatile__ ("dtstdgq 5, %0, 1" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdgq 0, %0, 1" : : "f" (f14));
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break;
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case 1:
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if (BF)
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__asm__ __volatile__ ("dtstdgq 5, %0, 2" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdgq 0, %0, 2" : : "f" (f14));
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break;
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case 2:
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if (BF)
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__asm__ __volatile__ ("dtstdgq 5, %0, 4" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdgq 0, %0, 4" : : "f" (f14));
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break;
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case 3:
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if (BF)
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__asm__ __volatile__ ("dtstdgq 5, %0, 8" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdgq 0, %0, 8" : : "f" (f14));
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break;
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case 4:
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if (BF)
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__asm__ __volatile__ ("dtstdgq 5, %0, 16" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdgq 0, %0, 16" : : "f" (f14));
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break;
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case 5:
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if (BF)
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__asm__ __volatile__ ("dtstdgq 5, %0, 32" : : "f" (f14));
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else
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__asm__ __volatile__ ("dtstdgq 0, %0, 32" : : "f" (f14));
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break;
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default:
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break;
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}
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}
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/* In _test_dtstex[q], BF is the condition register bit field indicating the
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* CR field in which the result of the test should be placed. BF can range
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* from 0-7, but for testing purposes, we only use BF values of '4' and '7'.
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*/
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static void
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_test_dtstex(int BF, int x __attribute__((unused)), dfp_val_t val1, dfp_val_t val2)
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{
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_Decimal64 f14 = val1.dec_val;
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_Decimal64 f16 = val2.dec_val;
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if (!(BF == 4 || BF == 7)) {
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fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
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return;
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}
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switch (BF) {
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case 4:
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__asm__ __volatile__ ("dtstex 4, %0, %1" : : "f" (f14),"f" (f16));
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break;
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case 7:
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__asm__ __volatile__ ("dtstex 7, %0, %1" : : "f" (f14),"f" (f16));
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break;
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default:
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break;
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}
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}
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static void _test_dtstexq(int BF, int x __attribute__((unused)), dfp_val_t val1, dfp_val_t val2)
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{
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_Decimal128 f14 = val1.dec_val128;
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_Decimal128 f16 = val2.dec_val128;
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if (!(BF == 4 || BF == 7)) {
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fprintf(stderr, "Invalid input to asm test: a=%d\n", BF);
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return;
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}
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switch (BF) {
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case 4:
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__asm__ __volatile__ ("dtstexq 4, %0, %1" : : "f" (f14),"f" (f16));
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break;
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case 7:
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__asm__ __volatile__ ("dtstexq 7, %0, %1" : : "f" (f14),"f" (f16));
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break;
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default:
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break;
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}
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}
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typedef void (*test_func_t)(int a, int b, dfp_val_t val1, dfp_val_t val2);
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typedef void (*test_driver_func_t)(void);
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typedef struct test_table
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{
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test_driver_func_t test_category;
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char * name;
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} test_table_t;
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/*
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* 345.0DD (0x2207c00000000000 0xe50)
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* 1.2300e+5DD (0x2207c00000000000 0x14c000)
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* -16.0DD (0xa207c00000000000 0xe0)
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* 0.00189DD (0x2206c00000000000 0xcf)
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* -4.1235DD (0xa205c00000000000 0x10a395bcf)
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* 9.8399e+20DD (0x2209400000000000 0x253f1f534acdd4)
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* 0DD (0x2208000000000000 0x0)
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* 0DD (0x2208000000000000 0x0)
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* infDD (0x7800000000000000 0x0)
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* nanDD (0x7c00000000000000 0x0
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*/
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static unsigned long long dfp128_vals[] = {
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// Some finite numbers
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0x2207c00000000000ULL, 0x0000000000000e50ULL,
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0x2207c00000000000ULL, 0x000000000014c000ULL,
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0xa207c00000000000ULL, 0x00000000000000e0ULL,
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0x2206c00000000000ULL, 0x00000000000000cfULL,
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0xa205c00000000000ULL, 0x000000010a395bcfULL,
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0x6209400000fd0000ULL, 0x00253f1f534acdd4ULL, // huge number
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0x000400000089b000ULL, 0x0a6000d000000049ULL, // very small number
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// flavors of zero
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0x2208000000000000ULL, 0x0000000000000000ULL,
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0xa208000000000000ULL, 0x0000000000000000ULL, // negative
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0xa248000000000000ULL, 0x0000000000000000ULL,
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// flavors of NAN
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0x7c00000000000000ULL, 0x0000000000000000ULL, // quiet
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0xfc00000000000000ULL, 0xc00100035b007700ULL,
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0x7e00000000000000ULL, 0xfe000000d0e0a0d0ULL, // signaling
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// flavors of Infinity
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0x7800000000000000ULL, 0x0000000000000000ULL,
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0xf800000000000000ULL, 0x0000000000000000ULL, // negative
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0xf900000000000000ULL, 0x0000000000000000ULL
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};
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static unsigned long long dfp64_vals[] = {
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// various finite numbers
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0x2234000000000e50ULL,
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0x223400000014c000ULL,
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0xa2340000000000e0ULL,// negative
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0x22240000000000cfULL,
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0xa21400010a395bcfULL,// negative
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0x6e4d3f1f534acdd4ULL,// huge number
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0x000400000089b000ULL,// very small number
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// flavors of zero
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0x2238000000000000ULL,
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0xa238000000000000ULL,
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0x4248000000000000ULL,
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// flavors of NAN
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0x7e34000000000111ULL,
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0xfe000000d0e0a0d0ULL,//signaling
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0xfc00000000000000ULL,//quiet
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// flavors of Infinity
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0x7800000000000000ULL,
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0xf800000000000000ULL,//negative
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0x7a34000000000000ULL,
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};
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// Both Long and Quad arrays of DFP values should have the same length, so it
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// doesn't matter which array I use for calculating the following #define.
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#define NUM_DFP_VALS (sizeof(dfp64_vals)/8)
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typedef struct dfp_test_args {
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int fra_idx;
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int frb_idx;
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} dfp_test_args_t;
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// Index pairs from dfp64_vals array to be used with dfp_two_arg_tests
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static dfp_test_args_t dfp_2args_x1[] = {
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{0, 1},
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{2, 1},
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{4, 3},
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{6, 0},
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{2, 4},
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{5, 1},
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{5, 2},
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{7, 1},
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{7, 2},
|
||||
{8, 0},
|
||||
{8, 1},
|
||||
{8, 2},
|
||||
{7, 8},
|
||||
{12, 14},
|
||||
{12, 1},
|
||||
{12, 13},
|
||||
{12, 12},
|
||||
{12, 11},
|
||||
{11, 14},
|
||||
{11, 0},
|
||||
{11, 13},
|
||||
{11, 11},
|
||||
{14, 14},
|
||||
{14, 3},
|
||||
{14, 15},
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
LONG_TEST,
|
||||
QUAD_TEST
|
||||
} precision_type_t;
|
||||
|
||||
typedef struct dfp_test
|
||||
{
|
||||
test_func_t test_func;
|
||||
const char * name;
|
||||
dfp_test_args_t * targs;
|
||||
int num_tests;
|
||||
precision_type_t precision;
|
||||
const char * op;
|
||||
} dfp_test_t;
|
||||
|
||||
typedef struct dfp_one_arg_test
|
||||
{
|
||||
test_func_t test_func;
|
||||
const char * name;
|
||||
precision_type_t precision;
|
||||
const char * op;
|
||||
} dfp_one_arg_test_t;
|
||||
|
||||
|
||||
|
||||
static dfp_one_arg_test_t
|
||||
dfp_ClassAndGroupTest_tests[] = {
|
||||
{ &_test_dtstdc, "dtstdc", LONG_TEST, "[tCls]"},
|
||||
{ &_test_dtstdcq, "dtstdcq", QUAD_TEST, "[tCls]"},
|
||||
{ &_test_dtstdg, "dtstdg", LONG_TEST, "[tGrp]"},
|
||||
{ &_test_dtstdgq, "dtstdgq", QUAD_TEST, "[tGrp]"},
|
||||
{ NULL, NULL, 0, NULL}
|
||||
};
|
||||
|
||||
static void test_dfp_ClassAndGroupTest_ops(void)
|
||||
{
|
||||
test_func_t func;
|
||||
dfp_val_t test_val, dummy;
|
||||
|
||||
int k = 0;
|
||||
|
||||
while ((func = dfp_ClassAndGroupTest_tests[k].test_func)) {
|
||||
int i, j;
|
||||
dfp_one_arg_test_t test_def = dfp_ClassAndGroupTest_tests[k];
|
||||
|
||||
for (i = 0; i < NUM_DFP_VALS; i++) {
|
||||
int data_class_OR_group, BF = 0;
|
||||
Bool repeat = True;
|
||||
|
||||
if (test_def.precision == LONG_TEST) {
|
||||
test_val.u64_val = dfp64_vals[i];
|
||||
} else {
|
||||
test_val.u128.valu = dfp128_vals[i * 2];
|
||||
test_val.u64_val = test_val.u128.valu;
|
||||
test_val.u128.vall = dfp128_vals[(i * 2) + 1];
|
||||
}
|
||||
|
||||
again:
|
||||
for (data_class_OR_group = 0; data_class_OR_group < 6; data_class_OR_group++) {
|
||||
unsigned int condreg;
|
||||
unsigned int flags;
|
||||
SET_FPSCR_ZERO;
|
||||
SET_CR_XER_ZERO;
|
||||
(*func)(BF, data_class_OR_group, test_val, dummy);
|
||||
GET_CR(flags);
|
||||
|
||||
condreg = ((flags >> (4 * (7-BF)))) & 0xf;
|
||||
printf("%s (DC/DG=%d) %s%016llx", test_def.name, data_class_OR_group,
|
||||
test_def.op, test_val.u64_val);
|
||||
if (test_def.precision == QUAD_TEST) {
|
||||
printf(" %016llx", test_val.u128.vall);
|
||||
}
|
||||
printf(" => %x (BF=%d)\n", condreg, BF);
|
||||
}
|
||||
if (repeat) {
|
||||
repeat = False;
|
||||
BF = 5;
|
||||
goto again;
|
||||
}
|
||||
}
|
||||
k++;
|
||||
printf( "\n" );
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static dfp_test_t
|
||||
dfp_ExpTest_tests[] = {
|
||||
{ &_test_dtstex, "dtstex", dfp_2args_x1, 25, LONG_TEST, "[tExp]"},
|
||||
{ &_test_dtstexq, "dtstexq", dfp_2args_x1, 25, QUAD_TEST, "[tExp]"},
|
||||
{ NULL, NULL, NULL, 0, 0, NULL}
|
||||
};
|
||||
|
||||
|
||||
static void test_dfp_ExpTest_ops(void)
|
||||
{
|
||||
dfp_val_t test_val1, test_val2;
|
||||
test_func_t func;
|
||||
int k = 0;
|
||||
|
||||
while ((func = dfp_ExpTest_tests[k].test_func)) {
|
||||
/* BF is a 3-bit instruction field that indicates the CR field in which the
|
||||
* result of the test should be placed. We won't iterate through all
|
||||
* 8 possible BF values since storing compare results to a given field is
|
||||
* a well-tested mechanism in VEX. But we will test two BF values, just as
|
||||
* a sniff-test.
|
||||
*/
|
||||
int i, repeat = 1, BF = 4;
|
||||
dfp_test_t test_def = dfp_ExpTest_tests[k];
|
||||
|
||||
again:
|
||||
for (i = 0; i < test_def.num_tests; i++) {
|
||||
unsigned int condreg;
|
||||
unsigned int flags;
|
||||
|
||||
if (test_def.precision == LONG_TEST) {
|
||||
test_val1.u64_val = dfp64_vals[test_def.targs[i].fra_idx];
|
||||
test_val2.u64_val = dfp64_vals[test_def.targs[i].frb_idx];
|
||||
} else {
|
||||
test_val1.u128.valu = dfp128_vals[test_def.targs[i].fra_idx * 2];
|
||||
test_val1.u64_val = test_val1.u128.valu;
|
||||
test_val1.u128.vall = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
|
||||
test_val2.u128.valu = dfp128_vals[test_def.targs[i].frb_idx * 2];
|
||||
test_val2.u64_val = test_val2.u128.valu;
|
||||
test_val2.u128.vall = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
|
||||
}
|
||||
|
||||
SET_FPSCR_ZERO;
|
||||
SET_CR_XER_ZERO;
|
||||
(*func)(BF, 0, test_val1, test_val2);
|
||||
GET_CR(flags);
|
||||
|
||||
condreg = ((flags >> (4 * (7-BF)))) & 0xf;
|
||||
printf("%s %016llx", test_def.name, test_val1.u64_val);
|
||||
if (test_def.precision == LONG_TEST) {
|
||||
printf(" %s %016llx ",
|
||||
test_def.op, test_val2.u64_val);
|
||||
} else {
|
||||
printf(" %016llx %s %016llx %016llx ",
|
||||
test_val1.u128.vall, test_def.op, test_val2.u128.valu, test_val2.u128.vall);
|
||||
}
|
||||
printf(" => %x (BF=%d)\n", condreg, BF);
|
||||
}
|
||||
if (repeat) {
|
||||
repeat = 0;
|
||||
BF = 7;
|
||||
goto again;
|
||||
}
|
||||
k++;
|
||||
printf( "\n" );
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static test_table_t
|
||||
all_tests[] =
|
||||
{
|
||||
{ &test_dfp_ExpTest_ops,
|
||||
"Test DFP exponent test instructions"},
|
||||
{ &test_dfp_ClassAndGroupTest_ops,
|
||||
"Test DFP class and group test instructions"},
|
||||
{ NULL, NULL }
|
||||
};
|
||||
#endif // HAS_DFP
|
||||
|
||||
int main() {
|
||||
#if defined(HAS_DFP)
|
||||
|
||||
test_table_t aTest;
|
||||
test_driver_func_t func;
|
||||
int i = 0;
|
||||
|
||||
while ((func = all_tests[i].test_category)) {
|
||||
aTest = all_tests[i];
|
||||
printf( "%s\n", aTest.name );
|
||||
(*func)();
|
||||
i++;
|
||||
}
|
||||
|
||||
#endif // HAS_DFP
|
||||
return 0;
|
||||
}
|
||||
2
none/tests/ppc32/test_dfp4.stderr.exp
Normal file
2
none/tests/ppc32/test_dfp4.stderr.exp
Normal file
@ -0,0 +1,2 @@
|
||||
|
||||
|
||||
876
none/tests/ppc32/test_dfp4.stdout.exp
Normal file
876
none/tests/ppc32/test_dfp4.stdout.exp
Normal file
@ -0,0 +1,876 @@
|
||||
Test DFP exponent test instructions
|
||||
dtstex 2234000000000e50 [tExp] 223400000014c000 => 2 (BF=4)
|
||||
dtstex a2340000000000e0 [tExp] 223400000014c000 => 2 (BF=4)
|
||||
dtstex a21400010a395bcf [tExp] 22240000000000cf => 8 (BF=4)
|
||||
dtstex 000400000089b000 [tExp] 2234000000000e50 => 8 (BF=4)
|
||||
dtstex a2340000000000e0 [tExp] a21400010a395bcf => 4 (BF=4)
|
||||
dtstex 6e4d3f1f534acdd4 [tExp] 223400000014c000 => 4 (BF=4)
|
||||
dtstex 6e4d3f1f534acdd4 [tExp] a2340000000000e0 => 4 (BF=4)
|
||||
dtstex 2238000000000000 [tExp] 223400000014c000 => 4 (BF=4)
|
||||
dtstex 2238000000000000 [tExp] a2340000000000e0 => 4 (BF=4)
|
||||
dtstex a238000000000000 [tExp] 2234000000000e50 => 4 (BF=4)
|
||||
dtstex a238000000000000 [tExp] 223400000014c000 => 4 (BF=4)
|
||||
dtstex a238000000000000 [tExp] a2340000000000e0 => 4 (BF=4)
|
||||
dtstex 2238000000000000 [tExp] a238000000000000 => 2 (BF=4)
|
||||
dtstex fc00000000000000 [tExp] f800000000000000 => 1 (BF=4)
|
||||
dtstex fc00000000000000 [tExp] 223400000014c000 => 1 (BF=4)
|
||||
dtstex fc00000000000000 [tExp] 7800000000000000 => 1 (BF=4)
|
||||
dtstex fc00000000000000 [tExp] fc00000000000000 => 2 (BF=4)
|
||||
dtstex fc00000000000000 [tExp] fe000000d0e0a0d0 => 2 (BF=4)
|
||||
dtstex fe000000d0e0a0d0 [tExp] f800000000000000 => 1 (BF=4)
|
||||
dtstex fe000000d0e0a0d0 [tExp] 2234000000000e50 => 1 (BF=4)
|
||||
dtstex fe000000d0e0a0d0 [tExp] 7800000000000000 => 1 (BF=4)
|
||||
dtstex fe000000d0e0a0d0 [tExp] fe000000d0e0a0d0 => 2 (BF=4)
|
||||
dtstex f800000000000000 [tExp] f800000000000000 => 2 (BF=4)
|
||||
dtstex f800000000000000 [tExp] 22240000000000cf => 1 (BF=4)
|
||||
dtstex f800000000000000 [tExp] 7a34000000000000 => 2 (BF=4)
|
||||
dtstex 2234000000000e50 [tExp] 223400000014c000 => 2 (BF=7)
|
||||
dtstex a2340000000000e0 [tExp] 223400000014c000 => 2 (BF=7)
|
||||
dtstex a21400010a395bcf [tExp] 22240000000000cf => 8 (BF=7)
|
||||
dtstex 000400000089b000 [tExp] 2234000000000e50 => 8 (BF=7)
|
||||
dtstex a2340000000000e0 [tExp] a21400010a395bcf => 4 (BF=7)
|
||||
dtstex 6e4d3f1f534acdd4 [tExp] 223400000014c000 => 4 (BF=7)
|
||||
dtstex 6e4d3f1f534acdd4 [tExp] a2340000000000e0 => 4 (BF=7)
|
||||
dtstex 2238000000000000 [tExp] 223400000014c000 => 4 (BF=7)
|
||||
dtstex 2238000000000000 [tExp] a2340000000000e0 => 4 (BF=7)
|
||||
dtstex a238000000000000 [tExp] 2234000000000e50 => 4 (BF=7)
|
||||
dtstex a238000000000000 [tExp] 223400000014c000 => 4 (BF=7)
|
||||
dtstex a238000000000000 [tExp] a2340000000000e0 => 4 (BF=7)
|
||||
dtstex 2238000000000000 [tExp] a238000000000000 => 2 (BF=7)
|
||||
dtstex fc00000000000000 [tExp] f800000000000000 => 1 (BF=7)
|
||||
dtstex fc00000000000000 [tExp] 223400000014c000 => 1 (BF=7)
|
||||
dtstex fc00000000000000 [tExp] 7800000000000000 => 1 (BF=7)
|
||||
dtstex fc00000000000000 [tExp] fc00000000000000 => 2 (BF=7)
|
||||
dtstex fc00000000000000 [tExp] fe000000d0e0a0d0 => 2 (BF=7)
|
||||
dtstex fe000000d0e0a0d0 [tExp] f800000000000000 => 1 (BF=7)
|
||||
dtstex fe000000d0e0a0d0 [tExp] 2234000000000e50 => 1 (BF=7)
|
||||
dtstex fe000000d0e0a0d0 [tExp] 7800000000000000 => 1 (BF=7)
|
||||
dtstex fe000000d0e0a0d0 [tExp] fe000000d0e0a0d0 => 2 (BF=7)
|
||||
dtstex f800000000000000 [tExp] f800000000000000 => 2 (BF=7)
|
||||
dtstex f800000000000000 [tExp] 22240000000000cf => 1 (BF=7)
|
||||
dtstex f800000000000000 [tExp] 7a34000000000000 => 2 (BF=7)
|
||||
|
||||
dtstexq 2207c00000000000 0000000000000e50 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=4)
|
||||
dtstexq a207c00000000000 00000000000000e0 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=4)
|
||||
dtstexq a205c00000000000 000000010a395bcf [tExp] 2206c00000000000 00000000000000cf => 8 (BF=4)
|
||||
dtstexq 000400000089b000 0a6000d000000049 [tExp] 2207c00000000000 0000000000000e50 => 8 (BF=4)
|
||||
dtstexq a207c00000000000 00000000000000e0 [tExp] a205c00000000000 000000010a395bcf => 4 (BF=4)
|
||||
dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] 2207c00000000000 000000000014c000 => 8 (BF=4)
|
||||
dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] a207c00000000000 00000000000000e0 => 8 (BF=4)
|
||||
dtstexq 2208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=4)
|
||||
dtstexq 2208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=4)
|
||||
dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 0000000000000e50 => 4 (BF=4)
|
||||
dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=4)
|
||||
dtstexq a208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=4)
|
||||
dtstexq 2208000000000000 0000000000000000 [tExp] a208000000000000 0000000000000000 => 2 (BF=4)
|
||||
dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] f800000000000000 0000000000000000 => 1 (BF=4)
|
||||
dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 2207c00000000000 000000000014c000 => 1 (BF=4)
|
||||
dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7800000000000000 0000000000000000 => 1 (BF=4)
|
||||
dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7e00000000000000 fe000000d0e0a0d0 => 2 (BF=4)
|
||||
dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=4)
|
||||
dtstexq fc00000000000000 c00100035b007700 [tExp] f800000000000000 0000000000000000 => 1 (BF=4)
|
||||
dtstexq fc00000000000000 c00100035b007700 [tExp] 2207c00000000000 0000000000000e50 => 1 (BF=4)
|
||||
dtstexq fc00000000000000 c00100035b007700 [tExp] 7800000000000000 0000000000000000 => 1 (BF=4)
|
||||
dtstexq fc00000000000000 c00100035b007700 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=4)
|
||||
dtstexq f800000000000000 0000000000000000 [tExp] f800000000000000 0000000000000000 => 2 (BF=4)
|
||||
dtstexq f800000000000000 0000000000000000 [tExp] 2206c00000000000 00000000000000cf => 1 (BF=4)
|
||||
dtstexq f800000000000000 0000000000000000 [tExp] f900000000000000 0000000000000000 => 2 (BF=4)
|
||||
dtstexq 2207c00000000000 0000000000000e50 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=7)
|
||||
dtstexq a207c00000000000 00000000000000e0 [tExp] 2207c00000000000 000000000014c000 => 2 (BF=7)
|
||||
dtstexq a205c00000000000 000000010a395bcf [tExp] 2206c00000000000 00000000000000cf => 8 (BF=7)
|
||||
dtstexq 000400000089b000 0a6000d000000049 [tExp] 2207c00000000000 0000000000000e50 => 8 (BF=7)
|
||||
dtstexq a207c00000000000 00000000000000e0 [tExp] a205c00000000000 000000010a395bcf => 4 (BF=7)
|
||||
dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] 2207c00000000000 000000000014c000 => 8 (BF=7)
|
||||
dtstexq 6209400000fd0000 00253f1f534acdd4 [tExp] a207c00000000000 00000000000000e0 => 8 (BF=7)
|
||||
dtstexq 2208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=7)
|
||||
dtstexq 2208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=7)
|
||||
dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 0000000000000e50 => 4 (BF=7)
|
||||
dtstexq a208000000000000 0000000000000000 [tExp] 2207c00000000000 000000000014c000 => 4 (BF=7)
|
||||
dtstexq a208000000000000 0000000000000000 [tExp] a207c00000000000 00000000000000e0 => 4 (BF=7)
|
||||
dtstexq 2208000000000000 0000000000000000 [tExp] a208000000000000 0000000000000000 => 2 (BF=7)
|
||||
dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] f800000000000000 0000000000000000 => 1 (BF=7)
|
||||
dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 2207c00000000000 000000000014c000 => 1 (BF=7)
|
||||
dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7800000000000000 0000000000000000 => 1 (BF=7)
|
||||
dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] 7e00000000000000 fe000000d0e0a0d0 => 2 (BF=7)
|
||||
dtstexq 7e00000000000000 fe000000d0e0a0d0 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=7)
|
||||
dtstexq fc00000000000000 c00100035b007700 [tExp] f800000000000000 0000000000000000 => 1 (BF=7)
|
||||
dtstexq fc00000000000000 c00100035b007700 [tExp] 2207c00000000000 0000000000000e50 => 1 (BF=7)
|
||||
dtstexq fc00000000000000 c00100035b007700 [tExp] 7800000000000000 0000000000000000 => 1 (BF=7)
|
||||
dtstexq fc00000000000000 c00100035b007700 [tExp] fc00000000000000 c00100035b007700 => 2 (BF=7)
|
||||
dtstexq f800000000000000 0000000000000000 [tExp] f800000000000000 0000000000000000 => 2 (BF=7)
|
||||
dtstexq f800000000000000 0000000000000000 [tExp] 2206c00000000000 00000000000000cf => 1 (BF=7)
|
||||
dtstexq f800000000000000 0000000000000000 [tExp] f900000000000000 0000000000000000 => 2 (BF=7)
|
||||
|
||||
Test DFP class and group test instructions
|
||||
dtstdc (DC/DG=0) [tCls]2234000000000e50 => 0 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]2234000000000e50 => 0 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]2234000000000e50 => 0 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]2234000000000e50 => 2 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]2234000000000e50 => 0 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]2234000000000e50 => 0 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]2234000000000e50 => 0 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]2234000000000e50 => 0 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]2234000000000e50 => 0 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]2234000000000e50 => 2 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]2234000000000e50 => 0 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]2234000000000e50 => 0 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]223400000014c000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]223400000014c000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]223400000014c000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]223400000014c000 => 2 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]223400000014c000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]223400000014c000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]223400000014c000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]223400000014c000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]223400000014c000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]223400000014c000 => 2 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]223400000014c000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]223400000014c000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]a2340000000000e0 => 8 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]a2340000000000e0 => 8 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]a2340000000000e0 => 8 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]a2340000000000e0 => a (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]a2340000000000e0 => 8 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]a2340000000000e0 => 8 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]a2340000000000e0 => 8 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]a2340000000000e0 => 8 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]a2340000000000e0 => 8 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]a2340000000000e0 => a (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]a2340000000000e0 => 8 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]a2340000000000e0 => 8 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]22240000000000cf => 0 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]22240000000000cf => 0 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]22240000000000cf => 0 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]22240000000000cf => 2 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]22240000000000cf => 0 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]22240000000000cf => 0 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]22240000000000cf => 0 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]22240000000000cf => 0 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]22240000000000cf => 0 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]22240000000000cf => 2 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]22240000000000cf => 0 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]22240000000000cf => 0 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]a21400010a395bcf => 8 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]a21400010a395bcf => 8 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]a21400010a395bcf => 8 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]a21400010a395bcf => a (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]a21400010a395bcf => 8 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]a21400010a395bcf => 8 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]a21400010a395bcf => 8 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]a21400010a395bcf => 8 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]a21400010a395bcf => 8 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]a21400010a395bcf => a (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]a21400010a395bcf => 8 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]a21400010a395bcf => 8 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]6e4d3f1f534acdd4 => 2 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]6e4d3f1f534acdd4 => 0 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]6e4d3f1f534acdd4 => 2 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]6e4d3f1f534acdd4 => 0 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]000400000089b000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]000400000089b000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]000400000089b000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]000400000089b000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]000400000089b000 => 2 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]000400000089b000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]000400000089b000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]000400000089b000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]000400000089b000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]000400000089b000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]000400000089b000 => 2 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]000400000089b000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]2238000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]2238000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]2238000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]2238000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]2238000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]2238000000000000 => 2 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]2238000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]2238000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]2238000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]2238000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]2238000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]2238000000000000 => 2 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]a238000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]a238000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]a238000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]a238000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]a238000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]a238000000000000 => a (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]a238000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]a238000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]a238000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]a238000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]a238000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]a238000000000000 => a (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]4248000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]4248000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]4248000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]4248000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]4248000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]4248000000000000 => 2 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]4248000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]4248000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]4248000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]4248000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]4248000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]4248000000000000 => 2 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]7e34000000000111 => 2 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]7e34000000000111 => 0 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]7e34000000000111 => 0 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]7e34000000000111 => 0 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]7e34000000000111 => 0 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]7e34000000000111 => 0 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]7e34000000000111 => 2 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]7e34000000000111 => 0 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]7e34000000000111 => 0 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]7e34000000000111 => 0 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]7e34000000000111 => 0 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]7e34000000000111 => 0 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]fe000000d0e0a0d0 => a (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]fe000000d0e0a0d0 => 8 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]fe000000d0e0a0d0 => a (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]fe000000d0e0a0d0 => 8 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]fc00000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]fc00000000000000 => a (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]fc00000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]fc00000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]fc00000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]fc00000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]fc00000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]fc00000000000000 => a (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]fc00000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]fc00000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]fc00000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]fc00000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]7800000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]7800000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]7800000000000000 => 2 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]7800000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]7800000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]7800000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]7800000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]7800000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]7800000000000000 => 2 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]7800000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]7800000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]7800000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]f800000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]f800000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]f800000000000000 => a (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]f800000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]f800000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]f800000000000000 => 8 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]f800000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]f800000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]f800000000000000 => a (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]f800000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]f800000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]f800000000000000 => 8 (BF=5)
|
||||
dtstdc (DC/DG=0) [tCls]7a34000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=1) [tCls]7a34000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=2) [tCls]7a34000000000000 => 2 (BF=0)
|
||||
dtstdc (DC/DG=3) [tCls]7a34000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=4) [tCls]7a34000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=5) [tCls]7a34000000000000 => 0 (BF=0)
|
||||
dtstdc (DC/DG=0) [tCls]7a34000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=1) [tCls]7a34000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=2) [tCls]7a34000000000000 => 2 (BF=5)
|
||||
dtstdc (DC/DG=3) [tCls]7a34000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=4) [tCls]7a34000000000000 => 0 (BF=5)
|
||||
dtstdc (DC/DG=5) [tCls]7a34000000000000 => 0 (BF=5)
|
||||
|
||||
dtstdcq (DC/DG=0) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]2207c00000000000 0000000000000e50 => 2 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]2207c00000000000 0000000000000e50 => 2 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]2207c00000000000 0000000000000e50 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]2207c00000000000 000000000014c000 => 2 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]2207c00000000000 000000000014c000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]2207c00000000000 000000000014c000 => 2 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]2207c00000000000 000000000014c000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]a207c00000000000 00000000000000e0 => a (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]a207c00000000000 00000000000000e0 => a (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]a207c00000000000 00000000000000e0 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]2206c00000000000 00000000000000cf => 2 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]2206c00000000000 00000000000000cf => 0 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]2206c00000000000 00000000000000cf => 2 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]2206c00000000000 00000000000000cf => 0 (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]a205c00000000000 000000010a395bcf => a (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]a205c00000000000 000000010a395bcf => a (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]a205c00000000000 000000010a395bcf => 8 (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]6209400000fd0000 00253f1f534acdd4 => 2 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]6209400000fd0000 00253f1f534acdd4 => 2 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]000400000089b000 0a6000d000000049 => 2 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]000400000089b000 0a6000d000000049 => 2 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]000400000089b000 0a6000d000000049 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]2208000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]2208000000000000 0000000000000000 => 2 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]2208000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]2208000000000000 0000000000000000 => 2 (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]a208000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]a208000000000000 0000000000000000 => a (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]a208000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]a208000000000000 0000000000000000 => a (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]a248000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]a248000000000000 0000000000000000 => a (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]a248000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]a248000000000000 0000000000000000 => a (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]7c00000000000000 0000000000000000 => 2 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]7c00000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]7c00000000000000 0000000000000000 => 2 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]7c00000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]fc00000000000000 c00100035b007700 => a (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]fc00000000000000 c00100035b007700 => a (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]fc00000000000000 c00100035b007700 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]7800000000000000 0000000000000000 => 2 (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]7800000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]7800000000000000 0000000000000000 => 2 (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]7800000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]f800000000000000 0000000000000000 => a (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]f800000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]f800000000000000 0000000000000000 => a (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]f800000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=0) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=1) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=2) [tCls]f900000000000000 0000000000000000 => a (BF=0)
|
||||
dtstdcq (DC/DG=3) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=4) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=5) [tCls]f900000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdcq (DC/DG=0) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=1) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=2) [tCls]f900000000000000 0000000000000000 => a (BF=5)
|
||||
dtstdcq (DC/DG=3) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=4) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdcq (DC/DG=5) [tCls]f900000000000000 0000000000000000 => 8 (BF=5)
|
||||
|
||||
dtstdg (DC/DG=0) [tGrp]2234000000000e50 => 0 (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]2234000000000e50 => 0 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]2234000000000e50 => 2 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]2234000000000e50 => 0 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]2234000000000e50 => 0 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]2234000000000e50 => 0 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]2234000000000e50 => 0 (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]2234000000000e50 => 0 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]2234000000000e50 => 2 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]2234000000000e50 => 0 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]2234000000000e50 => 0 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]2234000000000e50 => 0 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]223400000014c000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]223400000014c000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]223400000014c000 => 2 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]223400000014c000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]223400000014c000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]223400000014c000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]223400000014c000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]223400000014c000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]223400000014c000 => 2 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]223400000014c000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]223400000014c000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]223400000014c000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]a2340000000000e0 => 8 (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]a2340000000000e0 => 8 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]a2340000000000e0 => a (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]a2340000000000e0 => 8 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]a2340000000000e0 => 8 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]a2340000000000e0 => 8 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]a2340000000000e0 => 8 (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]a2340000000000e0 => 8 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]a2340000000000e0 => a (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]a2340000000000e0 => 8 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]a2340000000000e0 => 8 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]a2340000000000e0 => 8 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]22240000000000cf => 0 (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]22240000000000cf => 0 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]22240000000000cf => 2 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]22240000000000cf => 0 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]22240000000000cf => 0 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]22240000000000cf => 0 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]22240000000000cf => 0 (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]22240000000000cf => 0 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]22240000000000cf => 2 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]22240000000000cf => 0 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]22240000000000cf => 0 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]22240000000000cf => 0 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]a21400010a395bcf => 8 (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]a21400010a395bcf => 8 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]a21400010a395bcf => a (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]a21400010a395bcf => 8 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]a21400010a395bcf => 8 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]a21400010a395bcf => 8 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]a21400010a395bcf => 8 (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]a21400010a395bcf => 8 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]a21400010a395bcf => a (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]a21400010a395bcf => 8 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]a21400010a395bcf => 8 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]a21400010a395bcf => 8 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]6e4d3f1f534acdd4 => 2 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]6e4d3f1f534acdd4 => 0 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]6e4d3f1f534acdd4 => 2 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]6e4d3f1f534acdd4 => 0 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]000400000089b000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]000400000089b000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]000400000089b000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]000400000089b000 => 2 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]000400000089b000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]000400000089b000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]000400000089b000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]000400000089b000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]000400000089b000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]000400000089b000 => 2 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]000400000089b000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]000400000089b000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]2238000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]2238000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]2238000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]2238000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]2238000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]2238000000000000 => 2 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]2238000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]2238000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]2238000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]2238000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]2238000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]2238000000000000 => 2 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]a238000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]a238000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]a238000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]a238000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]a238000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]a238000000000000 => a (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]a238000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]a238000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]a238000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]a238000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]a238000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]a238000000000000 => a (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]4248000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]4248000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]4248000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]4248000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]4248000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]4248000000000000 => 2 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]4248000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]4248000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]4248000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]4248000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]4248000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]4248000000000000 => 2 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]7e34000000000111 => 2 (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]7e34000000000111 => 0 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]7e34000000000111 => 0 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]7e34000000000111 => 0 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]7e34000000000111 => 0 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]7e34000000000111 => 0 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]7e34000000000111 => 2 (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]7e34000000000111 => 0 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]7e34000000000111 => 0 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]7e34000000000111 => 0 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]7e34000000000111 => 0 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]7e34000000000111 => 0 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]fe000000d0e0a0d0 => a (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]fe000000d0e0a0d0 => 8 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]fe000000d0e0a0d0 => a (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]fe000000d0e0a0d0 => 8 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]fc00000000000000 => a (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]fc00000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]fc00000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]fc00000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]fc00000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]fc00000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]fc00000000000000 => a (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]fc00000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]fc00000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]fc00000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]fc00000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]fc00000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]7800000000000000 => 2 (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]7800000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]7800000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]7800000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]7800000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]7800000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]7800000000000000 => 2 (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]7800000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]7800000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]7800000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]7800000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]7800000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]f800000000000000 => a (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]f800000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]f800000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]f800000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]f800000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]f800000000000000 => 8 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]f800000000000000 => a (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]f800000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]f800000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]f800000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]f800000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]f800000000000000 => 8 (BF=5)
|
||||
dtstdg (DC/DG=0) [tGrp]7a34000000000000 => 2 (BF=0)
|
||||
dtstdg (DC/DG=1) [tGrp]7a34000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=2) [tGrp]7a34000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=3) [tGrp]7a34000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=4) [tGrp]7a34000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=5) [tGrp]7a34000000000000 => 0 (BF=0)
|
||||
dtstdg (DC/DG=0) [tGrp]7a34000000000000 => 2 (BF=5)
|
||||
dtstdg (DC/DG=1) [tGrp]7a34000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=2) [tGrp]7a34000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=3) [tGrp]7a34000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=4) [tGrp]7a34000000000000 => 0 (BF=5)
|
||||
dtstdg (DC/DG=5) [tGrp]7a34000000000000 => 0 (BF=5)
|
||||
|
||||
dtstdgq (DC/DG=0) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]2207c00000000000 0000000000000e50 => 2 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]2207c00000000000 0000000000000e50 => 2 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]2207c00000000000 0000000000000e50 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]2207c00000000000 000000000014c000 => 2 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]2207c00000000000 000000000014c000 => 2 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]2207c00000000000 000000000014c000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]a207c00000000000 00000000000000e0 => a (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]a207c00000000000 00000000000000e0 => a (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]a207c00000000000 00000000000000e0 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]2206c00000000000 00000000000000cf => 2 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]2206c00000000000 00000000000000cf => 2 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]2206c00000000000 00000000000000cf => 0 (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]a205c00000000000 000000010a395bcf => a (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]a205c00000000000 000000010a395bcf => a (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]a205c00000000000 000000010a395bcf => 8 (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]6209400000fd0000 00253f1f534acdd4 => 2 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]6209400000fd0000 00253f1f534acdd4 => 2 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]6209400000fd0000 00253f1f534acdd4 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]000400000089b000 0a6000d000000049 => 2 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]000400000089b000 0a6000d000000049 => 2 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]000400000089b000 0a6000d000000049 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]2208000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]2208000000000000 0000000000000000 => 2 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]2208000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]2208000000000000 0000000000000000 => 2 (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]a208000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]a208000000000000 0000000000000000 => a (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]a208000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]a208000000000000 0000000000000000 => a (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]a248000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]a248000000000000 0000000000000000 => a (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]a248000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]a248000000000000 0000000000000000 => a (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]7c00000000000000 0000000000000000 => 2 (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]7c00000000000000 0000000000000000 => 2 (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]7c00000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]fc00000000000000 c00100035b007700 => a (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]fc00000000000000 c00100035b007700 => a (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]fc00000000000000 c00100035b007700 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 2 (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]7e00000000000000 fe000000d0e0a0d0 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]7800000000000000 0000000000000000 => 2 (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]7800000000000000 0000000000000000 => 0 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]7800000000000000 0000000000000000 => 2 (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]7800000000000000 0000000000000000 => 0 (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]f800000000000000 0000000000000000 => a (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]f800000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]f800000000000000 0000000000000000 => a (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]f800000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=0) [tGrp]f900000000000000 0000000000000000 => a (BF=0)
|
||||
dtstdgq (DC/DG=1) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=2) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=3) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=4) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=5) [tGrp]f900000000000000 0000000000000000 => 8 (BF=0)
|
||||
dtstdgq (DC/DG=0) [tGrp]f900000000000000 0000000000000000 => a (BF=5)
|
||||
dtstdgq (DC/DG=1) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=2) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=3) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=4) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
|
||||
dtstdgq (DC/DG=5) [tGrp]f900000000000000 0000000000000000 => 8 (BF=5)
|
||||
|
||||
2
none/tests/ppc32/test_dfp4.vgtest
Normal file
2
none/tests/ppc32/test_dfp4.vgtest
Normal file
@ -0,0 +1,2 @@
|
||||
prereq: ../../../tests/check_dfp_cap
|
||||
prog: test_dfp4
|
||||
Loading…
x
Reference in New Issue
Block a user