mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-03 18:13:01 +00:00
This commit is for Bugzilla 334836. The Bugzilla contains patch 3 of 3
to add PPC64 LE support. The other two patches can be found in Bugzillas 334384 and 334834. Note, there are no VEX changes in this patch. PP64 Little Endian test case fixes. This patch adds new LE and BE expect files where needed. In other cases, the test was fixed to run correctly on LE and BE using based on testing to see which platform is being used. Where practical, the test cases have been changed so that the output produced for BE and LE will be identical. The test cases that require a major rewrite to make the output identical for BE and LE simply had an additional expect file added. Signed-off-by: Carl Love <carll@us.ibm.com> git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14240
This commit is contained in:
Carl Love
parent
98908947c7
commit
0689c096e5
@ -64,7 +64,6 @@ static struct {
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{ CPU_TYPE_ARM, "arm", "arm" },
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{ CPU_TYPE_POWERPC, "ppc", "ppc32" },
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{ CPU_TYPE_POWERPC64BE, "ppc64be", "ppc64be" },
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{ CPU_TYPE_POWERPC64LE, "ppc64le", "ppc64le" },
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};
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static int valid_archs_count = sizeof(valid_archs)/sizeof(valid_archs[0]);
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@ -83,8 +83,8 @@ void * VG_NOTIFY_ON_LOAD(ifunc_wrapper) (void)
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VALGRIND_GET_ORIG_FN(fn);
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CALL_FN_W_v(result, fn);
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#if defined(VGP_ppc64_linux)
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/* ppc64 uses function descriptors, so get the actual function entry
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#if defined(VGP_ppc64be_linux)
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/* ppc64be uses function descriptors, so get the actual function entry
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address for the client request, but return the function descriptor
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from this function.
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result points to the function descriptor, which starts with the
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@ -14,7 +14,7 @@
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#undef PLAT_x86_linux
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#undef PLAT_amd64_linux
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#undef PLAT_ppc32_linux
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#undef PLAT_ppc64_linux
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#undef PLAT_ppc64be_linux
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#undef PLAT_arm_linux
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#undef PLAT_s390x_linux
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#undef PLAT_mips32_linux
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@ -79,6 +79,23 @@ __attribute__((noinline)) void atomic_add_8bit ( char* p, int n )
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: /*trash*/ "memory", "cc", "r15"
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);
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} while (success != 1);
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#elif defined(VGA_ppc64le)
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/* Nasty hack. Does correctly atomically do *p += n, but only if p
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is 8-aligned -- guaranteed by caller. */
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unsigned long success;
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do {
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__asm__ __volatile__(
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"ldarx 15,0,%1" "\n\t"
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"add 15,15,%2" "\n\t"
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"stdcx. 15,0,%1" "\n\t"
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"mfcr %0" "\n\t"
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"srwi %0,%0,29" "\n\t"
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"andi. %0,%0,1" "\n"
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: /*out*/"=b"(success)
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: /*in*/ "b"(p), "b"(((unsigned long)n))
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: /*trash*/ "memory", "cc", "r15"
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);
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} while (success != 1);
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#elif defined(VGA_arm)
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unsigned int block[3]
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= { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
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@ -278,6 +295,23 @@ __attribute__((noinline)) void atomic_add_16bit ( short* p, int n )
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: /*trash*/ "memory", "cc", "r15"
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);
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} while (success != 1);
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#elif defined(VGA_ppc64le)
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/* Nasty hack. Does correctly atomically do *p += n, but only if p
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is 8-aligned -- guaranteed by caller. */
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unsigned long success;
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do {
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__asm__ __volatile__(
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"ldarx 15,0,%1" "\n\t"
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"add 15,15,%2" "\n\t"
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"stdcx. 15,0,%1" "\n\t"
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"mfcr %0" "\n\t"
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"srwi %0,%0,29" "\n\t"
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"andi. %0,%0,1" "\n"
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: /*out*/"=b"(success)
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: /*in*/ "b"(p), "b"(((unsigned long)n))
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: /*trash*/ "memory", "cc", "r15"
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);
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} while (success != 1);
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#elif defined(VGA_arm)
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unsigned int block[3]
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= { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
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@ -474,6 +508,23 @@ __attribute__((noinline)) void atomic_add_32bit ( int* p, int n )
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: /*trash*/ "memory", "cc", "r15"
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);
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} while (success != 1);
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#elif defined(VGA_ppc64le)
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/* Nasty hack. Does correctly atomically do *p += n, but only if p
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is 8-aligned -- guaranteed by caller. */
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unsigned long success;
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do {
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__asm__ __volatile__(
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"ldarx 15,0,%1" "\n\t"
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"add 15,15,%2" "\n\t"
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"stdcx. 15,0,%1" "\n\t"
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"mfcr %0" "\n\t"
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"srwi %0,%0,29" "\n\t"
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"andi. %0,%0,1" "\n"
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: /*out*/"=b"(success)
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: /*in*/ "b"(p), "b"(((unsigned long)n))
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: /*trash*/ "memory", "cc", "r15"
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);
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} while (success != 1);
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#elif defined(VGA_arm)
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unsigned int block[3]
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= { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
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@ -574,7 +625,7 @@ __attribute__((noinline)) void atomic_add_64bit ( long long int* p, int n )
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"lock; addq %%rbx,(%%rax)" "\n"
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: : "S"(&block[0])/* S means "rsi only" */ : "memory","cc","rax","rbx"
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);
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#elif defined(VGA_ppc64be)
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#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
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unsigned long success;
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do {
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__asm__ __volatile__(
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@ -2,7 +2,7 @@
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int main ( void )
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{
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#if defined(__powerpc64__)
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#if defined(__powerpc64__) && _CALL_ELF != 2
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/* on ppc64-linux, a function pointer points to a function
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descriptor, not to the function's entry point. Hence to get
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uniform behaviour on all supported targets - a jump to an
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@ -41,19 +41,25 @@ void test_parity_instrs()
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void test_lfiwax()
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{
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unsigned long base;
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float foo_s;
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typedef struct {
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#if defined(VGP_ppc64le_linux)
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unsigned int lo;
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unsigned int hi;
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#else
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unsigned int hi;
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unsigned int lo;
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#endif
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} int_pair_t;
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int_pair_t *ip;
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foo = -1024.0;
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base = (unsigned long) &foo;
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foo_s = -1024.0;
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base = (unsigned long) &foo_s;
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__asm__ volatile ("lfiwax %0, 0, %1":"=f" (FRT1):"r"(base));
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ip = (int_pair_t *) & FRT1;
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printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
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printf("lfiwax (%f) => FRT=(%x, %x)\n", foo_s, ip->hi, ip->lo);
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}
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@ -167,24 +173,27 @@ void test_fcpsgn()
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void test_reservation()
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{
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int RT;
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unsigned long long RT;
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unsigned long base;
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unsigned long offset;
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long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
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long arrL[] __attribute__ ((aligned (8))) = { 0xdeadbeef00112233ULL, 0xbad0beef44556677ULL, 0xbeefdead8899aabbULL, 0xbeef0badccddeeffULL };
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int arrI[] __attribute__ ((aligned (4))) = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
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base = (unsigned long) &arr;
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offset = (unsigned long) &arr[1] - base;
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base = (unsigned long) &arrI;
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offset = ((unsigned long) &arrI[1]) - base;
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__asm__ volatile ("ori 20, %0, 0"::"r" (base));
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__asm__ volatile ("ori 21, %0, 0"::"r" (offset));
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__asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT));
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printf("lwarx => %x\n", RT);
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printf("lwarx => 0x%llx\n", RT);
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#ifdef __powerpc64__
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offset = (unsigned long) &arr[1] - base;
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base = (unsigned long) &arrL;
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offset = ((unsigned long) &arrL[1]) - base;
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__asm__ volatile ("ori 20, %0, 0"::"r" (base));
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__asm__ volatile ("ori 21, %0, 0"::"r" (offset));
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__asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
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printf("ldarx => %x\n", RT);
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printf("ldarx => 0x%llx\n", RT);
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#endif
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}
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@ -1,5 +1,5 @@
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lwarx => 0
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ldarx => bad0beef
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lwarx => 0xbad0beef
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ldarx => 0xbad0beef44556677
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fcpsgn sign=10.101010, base=11.111111 => 11.111111
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fcpsgn sign=10.101010, base=-0.000000 => 0.000000
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fcpsgn sign=10.101010, base=0.000000 => 0.000000
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@ -20,7 +20,7 @@ lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000
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stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
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lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
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stfdpx (2.204800, 2.204800) => F_hi=2.204800, F_lo=2.204800
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lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
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lfiwax (-1024.000000) => FRT=(ffffffff, c4800000)
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prtyd (0) => parity=0
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prtyw (0) => parity=0
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prtyd (1) => parity=1
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@ -9,7 +9,7 @@
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#undef PLAT_x86_linux
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#undef PLAT_amd64_linux
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#undef PLAT_ppc32_linux
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#undef PLAT_ppc64_linux
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#undef PLAT_ppc64be_linux
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#if defined(__i386__)
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# define PLAT_x86_linux 1
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@ -11,13 +11,13 @@ EXTRA_DIST = \
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ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \
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lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
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jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
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jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest \
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jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-BE2 \
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jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
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jm-vmx.vgtest \
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jm-misc.stderr.exp jm-misc.stdout.exp jm-misc.vgtest \
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mftocrf.stderr.exp mftocrf.stdout.exp mftocrf.vgtest \
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mcrfs.stderr.exp mcrfs.stdout.exp mcrfs.vgtest \
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round.stderr.exp round.stdout.exp round.vgtest \
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round.stderr.exp round.stdout.exp round.vgtest round.stdout.exp-RM-fix\
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test_fx.stderr.exp test_fx.stdout.exp test_fx.stdout.exp_Minus_nan \
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test_fx.vgtest \
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test_gx.stderr.exp test_gx.stdout.exp test_gx.stdout.exp_Minus_nan \
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@ -113,29 +113,41 @@ test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_
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test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
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@FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
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test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \
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test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
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@FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
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test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
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test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
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@FLAG_M32@ $(BUILD_FLAGS_DFP)
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test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
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test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
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@FLAG_M32@ $(BUILD_FLAGS_DFP)
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test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
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test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
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@FLAG_M32@ $(BUILD_FLAGS_DFP)
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test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
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test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
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@FLAG_M32@ $(BUILD_FLAGS_DFP)
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test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
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test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
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@FLAG_M32@ $(BUILD_FLAGS_DFP)
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test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
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test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
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@FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
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test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
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test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
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@FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
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test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
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test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
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@FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
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test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
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test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
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@FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
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test_isa_2_06_part3_LDADD = -lm
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test_dfp1_LDADD = -lm
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test_dfp2_LDADD = -lm
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test_dfp3_LDADD = -lm
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test_dfp4_LDADD = -lm
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test_dfp5_LDADD = -lm
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test_isa_2_07_part1_LDADD = -lm
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test_isa_2_07_part2_LDADD = -lm
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test_tm_LDADD = -lm
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test_touch_tm_LDADD = -lm
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1431
none/tests/ppc32/jm-fp.stdout.exp-BE2
Normal file
1431
none/tests/ppc32/jm-fp.stdout.exp-BE2
Normal file
File diff suppressed because it is too large
Load Diff
@ -260,6 +260,7 @@ asm(".section \".text\"\n" \
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"\t.previous\n" \
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)
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#else
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#if defined(VGP_ppc64be_linux)
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#define ASSEMBLY_FUNC(__fname, __insn) \
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asm(".section \".text\"\n" \
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"\t.align 2\n" \
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@ -275,6 +276,16 @@ asm(".section \".text\"\n" \
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"\t"__insn"\n" \
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"\tblr\n" \
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)
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#elif defined(VGP_ppc64le_linux)
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#define ASSEMBLY_FUNC(__fname, __insn) \
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asm(".section \".text\"\n" \
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"\t.align 2\n" \
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"\t.global "__fname"\n" \
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""__fname":\n" \
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"\t"__insn"\n" \
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"\tblr\n" \
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)
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#endif // VGP_ppc64 or VGP_ppc64le
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#endif // #ifndef __powerpc64__
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@ -4849,7 +4860,7 @@ static inline
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test_func_t init_function( test_func_t p_func_F, uint32_t func_buf[] )
|
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{
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uint32_t* p_func = (uint32_t*)p_func_F;
|
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#ifndef __powerpc64__
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#if !defined(__powerpc64__) || _CALL_ELF == 2
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func_buf[0] = p_func[0];
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func_buf[1] = p_func[1];
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return (test_func_t)&func_buf[0];
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@ -5521,20 +5532,21 @@ static void test_int_ld_one_reg_imm16 (const char* name,
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uint32_t* func_buf = get_rwx_area();
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volatile HWord_t res, base;
|
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volatile uint32_t flags, xer;
|
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int i, offs, is_lwa=0;
|
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int i, offs, shift_offset = 0;
|
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|
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#ifdef __powerpc64__
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is_lwa = strstr(name, "lwa") != NULL;
|
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if (strstr(name, "lwa") || strstr(name, "ld") || strstr(name, "ldu"))
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shift_offset = 1;
|
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#endif
|
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|
||||
// +ve d
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base = (HWord_t)&iargs[0];
|
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for (i=0; i<nb_iargs; i++) {
|
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offs = i * sizeof(HWord_t);
|
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offs = (i == 0) ? i : (i * sizeof(HWord_t)) - 1;
|
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|
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/* Patch up the instruction */
|
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func = init_function( func_IN, func_buf );
|
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if (is_lwa)
|
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if (shift_offset)
|
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patch_op_imm(&func_buf[0], offs>>2, 2, 14);
|
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else
|
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patch_op_imm16(&func_buf[0], offs);
|
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@ -5557,8 +5569,8 @@ static void test_int_ld_one_reg_imm16 (const char* name,
|
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|
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// -ve d
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base = (HWord_t)&iargs[nb_iargs-1];
|
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for (i = -nb_iargs+1; i<=0; i++) {
|
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offs = i * sizeof(HWord_t);
|
||||
for (i = 0; i > -nb_iargs; i--) {
|
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offs = (i * sizeof(HWord_t)) + 1;
|
||||
|
||||
/* Patch up the instruction */
|
||||
func = init_function( func, func_buf );
|
||||
@ -5574,9 +5586,9 @@ static void test_int_ld_one_reg_imm16 (const char* name,
|
||||
#ifndef __powerpc64__
|
||||
printf("%s %2d, (%08x) => %08x, %2d (%08x %08x)\n",
|
||||
#else
|
||||
printf("%s %3d, (%016llx) => %016llx, %3lld (%08x %08x)\n",
|
||||
printf("%s %3d, (%016x) => %016llx, %3lld (%08x %08x)\n",
|
||||
#endif
|
||||
name, offs, iargs[nb_iargs-1+i], res, r14-base, flags, xer);
|
||||
name, offs, iargs[nb_iargs-1 + i], res, r14-base, flags, xer);
|
||||
}
|
||||
}
|
||||
|
||||
@ -5767,7 +5779,6 @@ static void test_float_three_args (const char* name, test_func_t func,
|
||||
/* Note: using nb_normal_fargs:
|
||||
- not testing special values for these insns
|
||||
*/
|
||||
|
||||
for (i=0; i<nb_normal_fargs; i+=3) {
|
||||
for (j=0; j<nb_normal_fargs; j+=5) {
|
||||
for (k=0; k<nb_normal_fargs; k+=7) {
|
||||
@ -5965,10 +5976,11 @@ static void test_float_ld_one_reg_imm16 (const char* name,
|
||||
{
|
||||
volatile test_func_t func;
|
||||
uint32_t* func_buf = get_rwx_area();
|
||||
uint32_t base;
|
||||
HWord_t base;
|
||||
volatile uint32_t flags, xer;
|
||||
volatile double src, res;
|
||||
int i, offs;
|
||||
int i;
|
||||
uint16_t offs;
|
||||
|
||||
/* offset within [1-nb_fargs:nb_fargs] */
|
||||
for (i=1-nb_fargs; i<nb_fargs; i++) {
|
||||
@ -6016,7 +6028,7 @@ static void test_float_ld_two_regs (const char* name,
|
||||
volatile uint32_t flags, xer;
|
||||
volatile double src, res;
|
||||
int i, offs;
|
||||
|
||||
|
||||
/* offset within [1-nb_fargs:nb_fargs] */
|
||||
for (i=1-nb_fargs; i<nb_fargs; i++) {
|
||||
offs = i * 8; // offset = i * sizeof(double)
|
||||
@ -6721,8 +6733,9 @@ static void lvs_cb (const char *name, test_func_t func,
|
||||
volatile uint32_t flags, tmpcr;
|
||||
volatile vector unsigned int tmpvscr;
|
||||
volatile vector unsigned int vec_out, vscr;
|
||||
unsigned int *dst;
|
||||
int i;
|
||||
unsigned shift;
|
||||
unsigned char * dst;
|
||||
int i, j;
|
||||
#if defined TEST_VSCR_SAT
|
||||
unsigned int* p_vscr;
|
||||
#endif
|
||||
@ -6731,7 +6744,8 @@ static void lvs_cb (const char *name, test_func_t func,
|
||||
vec_out = (vector unsigned int){ 0,0,0,0 };
|
||||
|
||||
// make sure start address is 16 aligned - use viargs[0]
|
||||
r15 = (HWord_t)&viargs[0];
|
||||
HWord_t * r15_in_ptr = (HWord_t *)&viargs[0];
|
||||
r15 = *r15_in_ptr;
|
||||
r14 = i;
|
||||
|
||||
/* Save flags */
|
||||
@ -6758,11 +6772,18 @@ static void lvs_cb (const char *name, test_func_t func,
|
||||
__asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
|
||||
__asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
|
||||
|
||||
dst = (unsigned int*)&vec_out;
|
||||
dst = (unsigned char*)&vec_out;
|
||||
|
||||
printf("%s %3d, %3d", name, i, 0);
|
||||
printf(" => %08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]);
|
||||
printf("(%08x)\n", flags);
|
||||
shift = ((unsigned int)i + *r15_in_ptr) & 0xf;
|
||||
printf("%s %x, %3d", name, shift, 0);
|
||||
printf(" => 0x");
|
||||
for (j = 0; j < 16; j++) {
|
||||
printf("%02x", dst[j]);
|
||||
if (j == 7)
|
||||
printf(" 0x");
|
||||
}
|
||||
|
||||
printf(" (%08x)\n", flags);
|
||||
}
|
||||
if (verbose) printf("\n");
|
||||
}
|
||||
|
||||
@ -1439,60 +1439,60 @@ PPC logical insns with special forms with flags update:
|
||||
PPC integer load insns
|
||||
with one register + one 16 bits immediate args with flags update:
|
||||
lbz 0, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
lbz 4, (000f423f) => 00000000, 0 (00000000 00000000)
|
||||
lbz 8, (ffffffff) => 000000ff, 0 (00000000 00000000)
|
||||
lbz -8, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
lbz -4, (000f423f) => 00000000, 0 (00000000 00000000)
|
||||
lbz 0, (ffffffff) => 000000ff, 0 (00000000 00000000)
|
||||
lbz 3, (000f423f) => 00000000, 0 (00000000 00000000)
|
||||
lbz 7, (ffffffff) => 0000003f, 0 (00000000 00000000)
|
||||
lbz 1, (ffffffff) => 000000ff, 0 (00000000 00000000)
|
||||
lbz -3, (000f423f) => 0000000f, 0 (00000000 00000000)
|
||||
lbz -7, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
|
||||
lbzu 0, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
lbzu 4, (000f423f) => 00000000, 4 (00000000 00000000)
|
||||
lbzu 8, (ffffffff) => 000000ff, 8 (00000000 00000000)
|
||||
lbzu -8, (00000000) => 00000000, -8 (00000000 00000000)
|
||||
lbzu -4, (000f423f) => 00000000, -4 (00000000 00000000)
|
||||
lbzu 0, (ffffffff) => 000000ff, 0 (00000000 00000000)
|
||||
lbzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
|
||||
lbzu 7, (ffffffff) => 0000003f, 7 (00000000 00000000)
|
||||
lbzu 1, (ffffffff) => 000000ff, 1 (00000000 00000000)
|
||||
lbzu -3, (000f423f) => 0000000f, -3 (00000000 00000000)
|
||||
lbzu -7, (00000000) => 00000000, -7 (00000000 00000000)
|
||||
|
||||
lha 0, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
lha 4, (000f423f) => 0000000f, 0 (00000000 00000000)
|
||||
lha 8, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
||||
lha -8, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
lha -4, (000f423f) => 0000000f, 0 (00000000 00000000)
|
||||
lha 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
||||
lha 3, (000f423f) => 00000000, 0 (00000000 00000000)
|
||||
lha 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
|
||||
lha 1, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
||||
lha -3, (000f423f) => 00000f42, 0 (00000000 00000000)
|
||||
lha -7, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
|
||||
lhau 0, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
lhau 4, (000f423f) => 0000000f, 4 (00000000 00000000)
|
||||
lhau 8, (ffffffff) => ffffffff, 8 (00000000 00000000)
|
||||
lhau -8, (00000000) => 00000000, -8 (00000000 00000000)
|
||||
lhau -4, (000f423f) => 0000000f, -4 (00000000 00000000)
|
||||
lhau 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
||||
lhau 3, (000f423f) => 00000000, 3 (00000000 00000000)
|
||||
lhau 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
|
||||
lhau 1, (ffffffff) => ffffffff, 1 (00000000 00000000)
|
||||
lhau -3, (000f423f) => 00000f42, -3 (00000000 00000000)
|
||||
lhau -7, (00000000) => 00000000, -7 (00000000 00000000)
|
||||
|
||||
lhz 0, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
lhz 4, (000f423f) => 0000000f, 0 (00000000 00000000)
|
||||
lhz 8, (ffffffff) => 0000ffff, 0 (00000000 00000000)
|
||||
lhz -8, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
lhz -4, (000f423f) => 0000000f, 0 (00000000 00000000)
|
||||
lhz 0, (ffffffff) => 0000ffff, 0 (00000000 00000000)
|
||||
lhz 3, (000f423f) => 00000000, 0 (00000000 00000000)
|
||||
lhz 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
|
||||
lhz 1, (ffffffff) => 0000ffff, 0 (00000000 00000000)
|
||||
lhz -3, (000f423f) => 00000f42, 0 (00000000 00000000)
|
||||
lhz -7, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
|
||||
lhzu 0, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
lhzu 4, (000f423f) => 0000000f, 4 (00000000 00000000)
|
||||
lhzu 8, (ffffffff) => 0000ffff, 8 (00000000 00000000)
|
||||
lhzu -8, (00000000) => 00000000, -8 (00000000 00000000)
|
||||
lhzu -4, (000f423f) => 0000000f, -4 (00000000 00000000)
|
||||
lhzu 0, (ffffffff) => 0000ffff, 0 (00000000 00000000)
|
||||
lhzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
|
||||
lhzu 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
|
||||
lhzu 1, (ffffffff) => 0000ffff, 1 (00000000 00000000)
|
||||
lhzu -3, (000f423f) => 00000f42, -3 (00000000 00000000)
|
||||
lhzu -7, (00000000) => 00000000, -7 (00000000 00000000)
|
||||
|
||||
lwz 0, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
lwz 4, (000f423f) => 000f423f, 0 (00000000 00000000)
|
||||
lwz 8, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
||||
lwz -8, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
lwz -4, (000f423f) => 000f423f, 0 (00000000 00000000)
|
||||
lwz 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
||||
lwz 3, (000f423f) => 00000f42, 0 (00000000 00000000)
|
||||
lwz 7, (ffffffff) => 3fffffff, 0 (00000000 00000000)
|
||||
lwz 1, (ffffffff) => ffffff00, 0 (00000000 00000000)
|
||||
lwz -3, (000f423f) => 0f423fff, 0 (00000000 00000000)
|
||||
lwz -7, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
|
||||
lwzu 0, (00000000) => 00000000, 0 (00000000 00000000)
|
||||
lwzu 4, (000f423f) => 000f423f, 4 (00000000 00000000)
|
||||
lwzu 8, (ffffffff) => ffffffff, 8 (00000000 00000000)
|
||||
lwzu -8, (00000000) => 00000000, -8 (00000000 00000000)
|
||||
lwzu -4, (000f423f) => 000f423f, -4 (00000000 00000000)
|
||||
lwzu 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
|
||||
lwzu 3, (000f423f) => 00000f42, 3 (00000000 00000000)
|
||||
lwzu 7, (ffffffff) => 3fffffff, 7 (00000000 00000000)
|
||||
lwzu 1, (ffffffff) => ffffff00, 1 (00000000 00000000)
|
||||
lwzu -3, (000f423f) => 0f423fff, -3 (00000000 00000000)
|
||||
lwzu -7, (00000000) => 00000000, -7 (00000000 00000000)
|
||||
|
||||
PPC integer load insns with two register args:
|
||||
lbzx 0 (00000000) => 00000000, 0 (00000000 00000000)
|
||||
|
||||
@ -1407,43 +1407,43 @@ Altivec integer special insns:
|
||||
vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
|
||||
vsldoi: => fefff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000)
|
||||
|
||||
lvsl -1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
|
||||
lvsl 0, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
|
||||
lvsl 1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
|
||||
lvsl 2, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
|
||||
lvsl 3, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
|
||||
lvsl 4, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
|
||||
lvsl 5, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
|
||||
lvsl 6, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
|
||||
lvsl 7, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
|
||||
lvsl 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
|
||||
lvsl 9, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
|
||||
lvsl 10, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
|
||||
lvsl 11, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
|
||||
lvsl 12, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
|
||||
lvsl 13, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
|
||||
lvsl 14, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
|
||||
lvsl 15, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
|
||||
lvsl 16, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
|
||||
lvsl 3, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
|
||||
lvsl 4, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
|
||||
lvsl 5, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000)
|
||||
lvsl 6, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000)
|
||||
lvsl 7, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
|
||||
lvsl 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
|
||||
lvsl 9, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
|
||||
lvsl a, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000)
|
||||
lvsl b, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000)
|
||||
lvsl c, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
|
||||
lvsl d, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
|
||||
lvsl e, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000)
|
||||
lvsl f, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000)
|
||||
lvsl 0, 0 => 0x0001020304050607 0x08090a0b0c0d0e0f (00000000)
|
||||
lvsl 1, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000)
|
||||
lvsl 2, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000)
|
||||
lvsl 3, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
|
||||
lvsl 4, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
|
||||
|
||||
lvsr -1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
|
||||
lvsr 0, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
|
||||
lvsr 1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
|
||||
lvsr 2, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
|
||||
lvsr 3, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
|
||||
lvsr 4, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
|
||||
lvsr 5, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
|
||||
lvsr 6, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
|
||||
lvsr 7, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
|
||||
lvsr 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
|
||||
lvsr 9, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
|
||||
lvsr 10, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
|
||||
lvsr 11, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
|
||||
lvsr 12, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
|
||||
lvsr 13, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
|
||||
lvsr 14, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
|
||||
lvsr 15, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
|
||||
lvsr 16, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
|
||||
lvsr 3, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
|
||||
lvsr 4, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
|
||||
lvsr 5, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000)
|
||||
lvsr 6, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000)
|
||||
lvsr 7, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
|
||||
lvsr 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
|
||||
lvsr 9, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
|
||||
lvsr a, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000)
|
||||
lvsr b, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000)
|
||||
lvsr c, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
|
||||
lvsr d, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
|
||||
lvsr e, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000)
|
||||
lvsr f, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000)
|
||||
lvsr 0, 0 => 0x1011121314151617 0x18191a1b1c1d1e1f (00000000)
|
||||
lvsr 1, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000)
|
||||
lvsr 2, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000)
|
||||
lvsr 3, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
|
||||
lvsr 4, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
|
||||
|
||||
Altivec load insns with two register args:
|
||||
lvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000000 00000000 00000000 (00000000)
|
||||
@ -3451,18 +3451,18 @@ Altivec float special insns:
|
||||
vcfux: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
|
||||
vcfux: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
|
||||
vcfux: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
|
||||
vcfux: ffffffff ( nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
|
||||
vcfux: ffffffff ( nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
|
||||
vcfux: ffffffff ( nan), 18 => 46800000 ( 1.638400e+04) (00000000)
|
||||
vcfux: ffffffff ( nan), 27 => 42000000 ( 3.200000e+01) (00000000)
|
||||
vcfux: ffffffff ( -nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
|
||||
vcfux: ffffffff ( -nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
|
||||
vcfux: ffffffff ( -nan), 18 => 46800000 ( 1.638400e+04) (00000000)
|
||||
vcfux: ffffffff ( -nan), 27 => 42000000 ( 3.200000e+01) (00000000)
|
||||
vcfux: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
|
||||
vcfux: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
|
||||
vcfux: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
|
||||
vcfux: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
|
||||
vcfux: ffbfffff ( nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
|
||||
vcfux: ffbfffff ( nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
|
||||
vcfux: ffbfffff ( nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
|
||||
vcfux: ffbfffff ( nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
|
||||
vcfux: ffbfffff ( -nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
|
||||
vcfux: ffbfffff ( -nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
|
||||
vcfux: ffbfffff ( -nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
|
||||
vcfux: ffbfffff ( -nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
|
||||
|
||||
vcfsx: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
|
||||
vcfsx: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
|
||||
@ -3500,27 +3500,27 @@ Altivec float special insns:
|
||||
vcfsx: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
|
||||
vcfsx: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
|
||||
vcfsx: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
|
||||
vcfsx: ffffffff ( nan), 0 => bf800000 (-1.000000e+00) (00000000)
|
||||
vcfsx: ffffffff ( nan), 9 => bb000000 (-1.953125e-03) (00000000)
|
||||
vcfsx: ffffffff ( nan), 18 => b6800000 (-3.814697e-06) (00000000)
|
||||
vcfsx: ffffffff ( nan), 27 => b2000000 (-7.450581e-09) (00000000)
|
||||
vcfsx: ffffffff ( -nan), 0 => bf800000 (-1.000000e+00) (00000000)
|
||||
vcfsx: ffffffff ( -nan), 9 => bb000000 (-1.953125e-03) (00000000)
|
||||
vcfsx: ffffffff ( -nan), 18 => b6800000 (-3.814697e-06) (00000000)
|
||||
vcfsx: ffffffff ( -nan), 27 => b2000000 (-7.450581e-09) (00000000)
|
||||
vcfsx: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
|
||||
vcfsx: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
|
||||
vcfsx: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
|
||||
vcfsx: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
|
||||
vcfsx: ffbfffff ( nan), 0 => ca800002 (-4.194305e+06) (00000000)
|
||||
vcfsx: ffbfffff ( nan), 9 => c6000002 (-8.192002e+03) (00000000)
|
||||
vcfsx: ffbfffff ( nan), 18 => c1800002 (-1.600000e+01) (00000000)
|
||||
vcfsx: ffbfffff ( nan), 27 => bd000002 (-3.125001e-02) (00000000)
|
||||
vcfsx: ffbfffff ( -nan), 0 => ca800002 (-4.194305e+06) (00000000)
|
||||
vcfsx: ffbfffff ( -nan), 9 => c6000002 (-8.192002e+03) (00000000)
|
||||
vcfsx: ffbfffff ( -nan), 18 => c1800002 (-1.600000e+01) (00000000)
|
||||
vcfsx: ffbfffff ( -nan), 27 => bd000002 (-3.125001e-02) (00000000)
|
||||
|
||||
vctuxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
@ -3537,10 +3537,10 @@ Altivec float special insns:
|
||||
vctuxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 0 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 9 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 18 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 27 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 0 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 9 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 18 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 27 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: ff800000 ( -inf), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ff800000 ( -inf), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ff800000 ( -inf), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
@ -3549,18 +3549,18 @@ Altivec float special insns:
|
||||
vctuxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
|
||||
vctsxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
@ -3598,17 +3598,17 @@ Altivec float special insns:
|
||||
vctsxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
|
||||
All done. Tested 165 different instructions
|
||||
|
||||
@ -443,9 +443,9 @@ vsubuqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==
|
||||
vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0
|
||||
vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
|
||||
|
||||
vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000020a
|
||||
vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000020a0000000000000000
|
||||
vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
|
||||
vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000e3ea
|
||||
vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000e3ea0000000000000000
|
||||
vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
|
||||
|
||||
vaddecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000
|
||||
|
||||
@ -324,38 +324,38 @@ zero:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
|
||||
+inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
|
||||
+inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
|
||||
+inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1p-3 ) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.000002p-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.000004p-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.000006p-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.000008p-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.00000ap-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.00000cp-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.00000ep-3) = 0x1.000004p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.00001p-3 ) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.000012p-3) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.000014p-3) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.000016p-3) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.000018p-3) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.00001ap-3) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.00001cp-3) = 0x1.000002p+0
|
||||
+inf:PASSED:fsubs(1.125001 , 0x1.00001ep-3) = 0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1p-3 ) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.000002p-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.000004p-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.000006p-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.000008p-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.00000ap-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.00000cp-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.00000ep-3) = -0x1.000004p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.00001p-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.000012p-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.000014p-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.000016p-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.000018p-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.00001ap-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.00001cp-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(-1.125001 , -0x1.00001ep-3) = -0x1.000002p+0
|
||||
-inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
|
||||
-inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0
|
||||
-inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0
|
||||
@ -409,78 +409,78 @@ zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
|
||||
zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
|
||||
zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
|
||||
zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
|
||||
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0
|
||||
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
|
||||
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
|
||||
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
|
||||
zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
|
||||
zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
|
||||
zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
|
||||
zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
|
||||
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
|
||||
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
|
||||
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
|
||||
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
|
||||
zero:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0
|
||||
zero:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
|
||||
zero:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
|
||||
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
|
||||
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
|
||||
zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
|
||||
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
|
||||
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
|
||||
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
|
||||
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
|
||||
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
|
||||
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0
|
||||
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
|
||||
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
|
||||
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
|
||||
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
|
||||
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
|
||||
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
|
||||
zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
|
||||
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
|
||||
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
|
||||
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
|
||||
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
|
||||
zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0
|
||||
zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
|
||||
zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
|
||||
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
|
||||
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
|
||||
zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
|
||||
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
|
||||
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
|
||||
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
|
||||
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
|
||||
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
|
||||
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0
|
||||
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
|
||||
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
|
||||
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
|
||||
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
|
||||
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
|
||||
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
|
||||
+inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
|
||||
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
|
||||
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
|
||||
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
|
||||
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
|
||||
+inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0
|
||||
+inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
|
||||
+inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
|
||||
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
|
||||
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
|
||||
+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
|
||||
+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
|
||||
+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
|
||||
+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
|
||||
+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
|
||||
+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
|
||||
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200004p+0
|
||||
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200006p+0
|
||||
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200008p+0
|
||||
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0
|
||||
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
|
||||
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
|
||||
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0
|
||||
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
|
||||
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
|
||||
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
|
||||
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
|
||||
+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
|
||||
+inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200016p+0
|
||||
+inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200018p+0
|
||||
+inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ap+0
|
||||
+inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0
|
||||
+inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
|
||||
+inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
|
||||
+inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0
|
||||
-inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
|
||||
-inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
|
||||
-inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
|
||||
-inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
|
||||
-inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
|
||||
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200004p+0
|
||||
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200006p+0
|
||||
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200008p+0
|
||||
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0
|
||||
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
|
||||
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
|
||||
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0
|
||||
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
|
||||
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
|
||||
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
|
||||
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
|
||||
-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
|
||||
-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200016p+0
|
||||
-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200018p+0
|
||||
-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ap+0
|
||||
-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0
|
||||
-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
|
||||
-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
|
||||
-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0
|
||||
@ -489,17 +489,17 @@ zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
|
||||
-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
|
||||
-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
|
||||
-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
|
||||
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0
|
||||
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
|
||||
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
|
||||
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
|
||||
-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
|
||||
-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
|
||||
-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
|
||||
-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
|
||||
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
|
||||
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
|
||||
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
|
||||
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
|
||||
-inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0
|
||||
-inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
|
||||
-inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
|
||||
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
|
||||
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
|
||||
-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
|
||||
near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
||||
near:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
|
||||
near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
||||
@ -566,35 +566,35 @@ zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
||||
zero:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0
|
||||
+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
||||
+inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
|
||||
+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
||||
+inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
|
||||
+inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
|
||||
+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
||||
+inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
|
||||
+inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0
|
||||
+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
||||
+inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
|
||||
+inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0
|
||||
+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
||||
+inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
||||
+inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
|
||||
+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
||||
+inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
||||
+inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
|
||||
+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
||||
+inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
||||
+inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0
|
||||
+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
|
||||
+inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
|
||||
+inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0
|
||||
+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
|
||||
+inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f72p+0
|
||||
+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
||||
+inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
||||
+inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec6p+0
|
||||
+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
||||
+inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
||||
+inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0
|
||||
+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
||||
+inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
||||
+inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0
|
||||
+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
|
||||
+inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
|
||||
+inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92494p+0
|
||||
+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
|
||||
+inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
|
||||
+inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f8p+0
|
||||
+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
|
||||
+inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
|
||||
+inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0
|
||||
+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
|
||||
+inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
|
||||
+inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0
|
||||
-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
|
||||
-inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f72p+0
|
||||
@ -665,78 +665,78 @@ zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+
|
||||
zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
||||
zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
||||
zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
||||
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
||||
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
||||
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
||||
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
||||
zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
||||
zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
||||
zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
||||
zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
||||
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
||||
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
||||
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
||||
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
||||
zero:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
||||
zero:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
||||
zero:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
||||
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
||||
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
||||
zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
||||
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
||||
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
||||
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
||||
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
||||
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
||||
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
||||
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
||||
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
||||
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
||||
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
||||
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
||||
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
||||
zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
||||
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
||||
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
||||
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
||||
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
||||
zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
||||
zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
||||
zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
||||
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
||||
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
||||
zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
||||
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
||||
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
||||
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
||||
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
||||
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
||||
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
||||
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
||||
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
||||
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
||||
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
||||
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
||||
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
||||
+inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
||||
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
||||
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
||||
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
||||
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
||||
+inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
||||
+inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
||||
+inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
||||
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
||||
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
||||
+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
||||
+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
||||
+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
||||
+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
||||
+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
||||
+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
||||
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
||||
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
||||
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
||||
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
||||
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
||||
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
||||
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
||||
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
||||
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
||||
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
||||
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
||||
+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
||||
+inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
||||
+inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
||||
+inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
||||
+inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
||||
+inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
||||
+inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
||||
+inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
|
||||
-inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
||||
-inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
||||
-inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
||||
-inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
||||
-inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
||||
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
||||
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
||||
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
||||
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
||||
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
||||
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
||||
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
||||
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
||||
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
||||
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
||||
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
||||
-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
||||
-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
||||
-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
||||
-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
||||
-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
||||
-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
||||
-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
||||
-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
|
||||
@ -745,17 +745,17 @@ zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
||||
-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
||||
-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
||||
-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
||||
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
||||
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
||||
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
||||
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
||||
-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
||||
-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
||||
-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
||||
-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
||||
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
||||
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
||||
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
||||
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
||||
-inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
||||
-inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
||||
-inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
||||
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
||||
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
||||
-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
||||
near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
||||
near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
||||
near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
||||
@ -793,78 +793,78 @@ zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
||||
zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
||||
zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
||||
zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
||||
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
||||
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
||||
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
||||
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
||||
zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
||||
zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
||||
zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
||||
zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
||||
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
||||
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
||||
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
||||
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
||||
zero:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
||||
zero:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
||||
zero:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
||||
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
||||
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
||||
zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
||||
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
||||
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
||||
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
||||
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
||||
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
||||
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
||||
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
||||
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
||||
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
||||
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
||||
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
||||
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
||||
zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
||||
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
||||
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
||||
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
||||
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
||||
zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
||||
zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
||||
zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
||||
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
||||
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
||||
zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
||||
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
||||
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
||||
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
||||
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
||||
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
||||
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
||||
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
||||
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
||||
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
||||
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
||||
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
||||
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
||||
+inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
||||
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
||||
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
||||
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
||||
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
||||
+inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
||||
+inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
||||
+inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
||||
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
||||
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
||||
+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
||||
+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
||||
+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
||||
+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
||||
+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
||||
+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
||||
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
||||
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
||||
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
||||
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
||||
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
||||
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
||||
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
||||
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
||||
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
||||
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
||||
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
||||
+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
||||
+inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
||||
+inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
||||
+inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
||||
+inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
||||
+inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
||||
+inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
||||
+inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
|
||||
-inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
||||
-inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
||||
-inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
||||
-inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
||||
-inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
||||
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
||||
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
||||
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
||||
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
||||
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
||||
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
||||
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
||||
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
||||
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
||||
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
||||
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
||||
-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
||||
-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
||||
-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
||||
-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
||||
-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
||||
-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
||||
-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
||||
-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
|
||||
@ -873,17 +873,17 @@ zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
||||
-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
||||
-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
||||
-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
||||
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
||||
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
||||
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
||||
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
||||
-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
||||
-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
||||
-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
||||
-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
||||
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
||||
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
||||
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
||||
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
||||
-inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
||||
-inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
||||
-inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
||||
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
||||
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
||||
-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
||||
near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
||||
near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
||||
near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
||||
@ -921,78 +921,78 @@ zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+
|
||||
zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
||||
zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
||||
zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
||||
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
||||
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
||||
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
||||
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
||||
zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
||||
zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
||||
zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
||||
zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
||||
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
||||
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
||||
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
||||
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
||||
zero:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
||||
zero:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
||||
zero:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
||||
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
||||
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
||||
zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
||||
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
|
||||
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
||||
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
||||
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
||||
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
||||
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
||||
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
||||
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
||||
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
||||
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
||||
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
||||
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
||||
zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
||||
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
||||
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
||||
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
||||
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
||||
zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
||||
zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
||||
zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
||||
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
||||
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
||||
zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
||||
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
|
||||
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
||||
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
||||
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
||||
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
||||
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
||||
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
||||
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
||||
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
||||
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
|
||||
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
||||
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
||||
+inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
||||
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
||||
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
||||
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
||||
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
||||
+inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
||||
+inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
||||
+inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
||||
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
|
||||
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
||||
+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
||||
+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
|
||||
+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
||||
+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
||||
+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
||||
+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
||||
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
||||
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
||||
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
|
||||
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
||||
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
||||
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
||||
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
||||
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
||||
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
||||
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
||||
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
||||
+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
||||
+inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
||||
+inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
||||
+inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
|
||||
+inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
||||
+inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
||||
+inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
||||
+inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
|
||||
-inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
|
||||
-inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
||||
-inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
||||
-inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
||||
-inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
||||
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
|
||||
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
|
||||
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
|
||||
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
|
||||
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
|
||||
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
|
||||
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
|
||||
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
|
||||
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
||||
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
||||
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
||||
-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
||||
-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
|
||||
-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
|
||||
-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
|
||||
-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
|
||||
-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
|
||||
-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
|
||||
-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
|
||||
@ -1001,17 +1001,17 @@ zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+
|
||||
-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
|
||||
-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
|
||||
-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
|
||||
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
||||
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
||||
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
||||
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
||||
-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
|
||||
-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
|
||||
-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
|
||||
-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
|
||||
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
|
||||
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
|
||||
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
|
||||
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
|
||||
-inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
||||
-inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
||||
-inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
||||
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
|
||||
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
|
||||
-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
|
||||
near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
||||
near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
||||
near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
||||
@ -1049,78 +1049,78 @@ zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
||||
zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
||||
zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
||||
zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
||||
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
||||
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
||||
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
||||
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
||||
zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
||||
zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
||||
zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
||||
zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
||||
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
||||
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
||||
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
||||
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
||||
zero:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
||||
zero:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
||||
zero:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
||||
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
||||
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
||||
zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
||||
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
|
||||
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
||||
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
||||
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
||||
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
||||
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
||||
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
||||
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
||||
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
||||
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
||||
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
||||
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
||||
zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
||||
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
||||
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
||||
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
||||
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
||||
zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
||||
zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
||||
zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
||||
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
||||
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
||||
zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
||||
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
|
||||
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
||||
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
||||
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
||||
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
||||
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
||||
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
||||
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
||||
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
||||
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
|
||||
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
||||
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
||||
+inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
||||
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
||||
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
||||
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
||||
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
||||
+inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
||||
+inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
||||
+inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
||||
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
|
||||
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
||||
+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
||||
+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
|
||||
+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
||||
+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
||||
+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
||||
+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
||||
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
||||
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
||||
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
|
||||
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
||||
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
||||
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
||||
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
||||
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
||||
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
||||
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
||||
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
||||
+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
||||
+inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
||||
+inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
||||
+inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
|
||||
+inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
||||
+inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
||||
+inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
||||
+inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
|
||||
-inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
|
||||
-inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
||||
-inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
||||
-inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
||||
-inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
||||
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
|
||||
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
|
||||
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
|
||||
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
|
||||
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
|
||||
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
|
||||
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
|
||||
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
|
||||
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
||||
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
||||
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
||||
-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
||||
-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
|
||||
-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
|
||||
-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
|
||||
-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
|
||||
-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
|
||||
-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
|
||||
-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
|
||||
@ -1129,17 +1129,17 @@ zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p
|
||||
-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
|
||||
-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
|
||||
-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
|
||||
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
||||
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
||||
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
||||
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
||||
-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
|
||||
-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
|
||||
-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
|
||||
-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
|
||||
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
|
||||
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
|
||||
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
|
||||
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
|
||||
-inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
||||
-inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
||||
-inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
||||
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
|
||||
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
|
||||
-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
|
||||
-------------------------- test rounding of double operators with guard bits --------------------------
|
||||
near:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
|
||||
near:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
|
||||
|
||||
2335
none/tests/ppc32/round.stdout.exp-RM-fix
Normal file
2335
none/tests/ppc32/round.stdout.exp-RM-fix
Normal file
File diff suppressed because it is too large
Load Diff
@ -31,8 +31,13 @@ typedef union stuff {
|
||||
_Decimal128 dec_val128;
|
||||
unsigned long long u64_val;
|
||||
struct {
|
||||
#if defined(VGP_ppc64le_linux)
|
||||
unsigned long long vall;
|
||||
unsigned long long valu;
|
||||
#else
|
||||
unsigned long long valu;
|
||||
unsigned long long vall;
|
||||
#endif
|
||||
} u128;
|
||||
} dfp_val_t;
|
||||
|
||||
@ -495,7 +500,6 @@ static void test_dfp_ClassAndGroupTest_ops(void)
|
||||
test_val.u64_val = dfp64_vals[i];
|
||||
} else {
|
||||
test_val.u128.valu = dfp128_vals[i * 2];
|
||||
test_val.u64_val = test_val.u128.valu;
|
||||
test_val.u128.vall = dfp128_vals[(i * 2) + 1];
|
||||
}
|
||||
|
||||
@ -509,11 +513,15 @@ again:
|
||||
GET_CR(flags);
|
||||
|
||||
condreg = ((flags >> (4 * (7-BF)))) & 0xf;
|
||||
printf("%s (DC/DG=%d) %s%016llx", test_def.name, data_class_OR_group,
|
||||
test_def.op, test_val.u64_val);
|
||||
printf("%s (DC/DG=%d) %s", test_def.name, data_class_OR_group,
|
||||
test_def.op);
|
||||
if (test_def.precision == QUAD_TEST) {
|
||||
printf(" %016llx", test_val.u128.vall);
|
||||
printf("%016llx %016llx", test_val.u128.valu, test_val.u128.vall);
|
||||
} else {
|
||||
printf("%016llx", test_val.u64_val);
|
||||
}
|
||||
|
||||
//%016llx
|
||||
printf(" => %x (BF=%d)\n", condreg, BF);
|
||||
}
|
||||
if (repeat) {
|
||||
@ -562,10 +570,8 @@ again:
|
||||
test_val2.u64_val = dfp64_vals[test_def.targs[i].frb_idx];
|
||||
} else {
|
||||
test_val1.u128.valu = dfp128_vals[test_def.targs[i].fra_idx * 2];
|
||||
test_val1.u64_val = test_val1.u128.valu;
|
||||
test_val1.u128.vall = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
|
||||
test_val2.u128.valu = dfp128_vals[test_def.targs[i].frb_idx * 2];
|
||||
test_val2.u64_val = test_val2.u128.valu;
|
||||
test_val2.u128.vall = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
|
||||
}
|
||||
|
||||
@ -575,13 +581,13 @@ again:
|
||||
GET_CR(flags);
|
||||
|
||||
condreg = ((flags >> (4 * (7-BF)))) & 0xf;
|
||||
printf("%s %016llx", test_def.name, test_val1.u64_val);
|
||||
printf("%s ", test_def.name);
|
||||
if (test_def.precision == LONG_TEST) {
|
||||
printf(" %s %016llx ",
|
||||
test_def.op, test_val2.u64_val);
|
||||
printf("%016llx %s %016llx ",
|
||||
test_val1.u64_val, test_def.op, test_val2.u64_val);
|
||||
} else {
|
||||
printf(" %016llx %s %016llx %016llx ",
|
||||
test_val1.u128.vall, test_def.op, test_val2.u128.valu, test_val2.u128.vall);
|
||||
printf("%016llx %016llx %s %016llx %016llx ",
|
||||
test_val1.u128.valu, test_val1.u128.vall, test_def.op, test_val2.u128.valu, test_val2.u128.vall);
|
||||
}
|
||||
printf(" => %x (BF=%d)\n", condreg, BF);
|
||||
}
|
||||
|
||||
@ -31,8 +31,13 @@ typedef union stuff {
|
||||
_Decimal128 dec_val128;
|
||||
unsigned long long u64_val;
|
||||
struct {
|
||||
#if defined(VGP_ppc64le_linux)
|
||||
unsigned long long vall;
|
||||
unsigned long long valu;
|
||||
#else
|
||||
unsigned long long valu;
|
||||
unsigned long long vall;
|
||||
#endif
|
||||
} u128;
|
||||
} dfp_val_t;
|
||||
|
||||
@ -418,22 +423,20 @@ static void test_dfp_ddedpd_ops(void)
|
||||
test_val.u64_val = dfp64_vals[i];
|
||||
} else {
|
||||
test_val.u128.valu = dfp128_vals[i * 2];
|
||||
test_val.u64_val = test_val.u128.valu;
|
||||
test_val.u128.vall = dfp128_vals[(i * 2) + 1];
|
||||
}
|
||||
|
||||
for (SP = 0; SP < 4; SP++) {
|
||||
dfp_val_t result;
|
||||
result = (*func)(SP, test_val);
|
||||
printf("%s (SP=%d) %s%016llx", test_def.name, SP,
|
||||
test_def.op, test_val.u64_val);
|
||||
if (test_def.precision == QUAD_TEST) {
|
||||
printf(" %016llx", test_val.u128.vall);
|
||||
printf("%s (SP=%d) %s", test_def.name, SP, test_def.op);
|
||||
if (test_def.precision == LONG_TEST) {
|
||||
printf("%016llx ==> %016llx\n", test_val.u64_val, result.u64_val);
|
||||
} else {
|
||||
printf("%016llx %016llx ==> %016llx %016llx\n",
|
||||
test_val.u128.valu, test_val.u128.vall,
|
||||
result.u128.valu, result.u128.vall);
|
||||
}
|
||||
if (test_def.precision == LONG_TEST)
|
||||
printf(" ==> %016llx\n", result.u64_val);
|
||||
else
|
||||
printf(" ==> %016llx %016llx\n", result.u128.valu, result.u128.vall);
|
||||
}
|
||||
}
|
||||
k++;
|
||||
@ -484,20 +487,18 @@ static void test_dfp_denbcd_ops(void)
|
||||
test_val.u64_val = bcd64_vals[i];
|
||||
} else {
|
||||
test_val.u128.valu = bcd128_vals[i * 2];
|
||||
test_val.u64_val = test_val.u128.valu;
|
||||
test_val.u128.vall = bcd128_vals[(i * 2) + 1];
|
||||
}
|
||||
|
||||
result = (*func)(S, test_val);
|
||||
printf("%s (S=%d) %s%016llx", test_def.name, S,
|
||||
test_def.op, test_val.u64_val);
|
||||
if (test_def.precision == QUAD_TEST) {
|
||||
printf(" %016llx", test_val.u128.vall);
|
||||
printf("%s (S=%d) %s", test_def.name, S, test_def.op);
|
||||
if (test_def.precision == LONG_TEST) {
|
||||
printf("%016llx ==> %016llx\n", test_val.u64_val, result.u64_val);
|
||||
} else {
|
||||
printf("%016llx %016llx ==> %016llx %016llx\n",
|
||||
test_val.u128.valu, test_val.u128.vall,
|
||||
result.u128.valu, result.u128.vall);
|
||||
}
|
||||
if (test_def.precision == LONG_TEST)
|
||||
printf(" ==> %016llx\n", result.u64_val);
|
||||
else
|
||||
printf(" ==> %016llx %016llx\n", result.u128.valu, result.u128.vall);
|
||||
}
|
||||
}
|
||||
k++;
|
||||
@ -532,7 +533,6 @@ static void test_dfp_test_significance_ops(void)
|
||||
test_valB.u64_val = dfp64_vals[i];
|
||||
} else {
|
||||
test_valB.u128.valu = dfp128_vals[i * 2];
|
||||
test_valB.u64_val = test_valB.u128.valu;
|
||||
test_valB.u128.vall = dfp128_vals[(i * 2) + 1];
|
||||
}
|
||||
|
||||
@ -549,10 +549,11 @@ static void test_dfp_test_significance_ops(void)
|
||||
GET_CR(flags);
|
||||
|
||||
condreg = ((flags >> (4 * (7-BF)))) & 0xf;
|
||||
printf("%s (ref_sig=%d) %s%016llx", test_def.name, reference_sig,
|
||||
test_def.op, test_valB.u64_val);
|
||||
if (test_def.precision == QUAD_TEST) {
|
||||
printf(" %016llx", test_valB.u128.vall);
|
||||
printf("%s (ref_sig=%d) %s", test_def.name, reference_sig, test_def.op);
|
||||
if (test_def.precision == LONG_TEST) {
|
||||
printf("%016llx", test_valB.u64_val);
|
||||
} else {
|
||||
printf("%016llx %016llx", test_valB.u128.valu, test_valB.u128.vall);
|
||||
}
|
||||
printf(" => %x (BF=%d)\n", condreg, BF);
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -130,13 +130,27 @@ ftdiv: 0000000000000000 <=> 0000000000000000 ? e (CRx)
|
||||
ftdiv: 0000000000000000 <=> 8000000000000000 ? e (CRx)
|
||||
|
||||
Test VSX move instructions
|
||||
xsabsdp: 01234567 89abcdef xsabsdp 8899aabb 91929394x => 0899aabb 91929394
|
||||
xsabsdp: X[B]: 0123456789abcdef => 0123456789abcdef
|
||||
xsabsdp: X[B]: 8899aabb19293942 => 0899aabb19293942
|
||||
xsabsdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
|
||||
|
||||
xscpsgndp: 8899aabb 91929394 xscpsgndp 01234567 89abcdefx => 81234567 89abcdef
|
||||
xscpsgndp: X[A]: 0123456789abcdef X[B]: 0123456789abcdef => 0123456789abcdef
|
||||
xscpsgndp: X[A]: 8899aabb19293942 X[B]: 0123456789abcdef => 8123456789abcdef
|
||||
xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 0123456789abcdef => 8123456789abcdef
|
||||
xscpsgndp: X[A]: 0123456789abcdef X[B]: 8899aabb19293942 => 0899aabb19293942
|
||||
xscpsgndp: X[A]: 8899aabb19293942 X[B]: 8899aabb19293942 => 8899aabb19293942
|
||||
xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 8899aabb19293942 => 8899aabb19293942
|
||||
xscpsgndp: X[A]: 0123456789abcdef X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
|
||||
xscpsgndp: X[A]: 8899aabb19293942 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
|
||||
xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
|
||||
|
||||
xsnabsdp: b1b2b3b4 c1c2c3c4 xsnabsdp 44556677 8899aabbx => c4556677 8899aabb
|
||||
xsnabsdp: X[B]: 0123456789abcdef => 8123456789abcdef
|
||||
xsnabsdp: X[B]: 8899aabb19293942 => 8899aabb19293942
|
||||
xsnabsdp: X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
|
||||
|
||||
xsnegdp: 01234567 89abcdef xsnegdp b1b2b3b4 c1c2c3c4x => 31b2b3b4 c1c2c3c4
|
||||
xsnegdp: X[B]: 0123456789abcdef => 8123456789abcdef
|
||||
xsnegdp: X[B]: 8899aabb19293942 => 0899aabb19293942
|
||||
xsnegdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
|
||||
|
||||
Test VSX permute instructions
|
||||
xxmrghw:
|
||||
@ -1020,4 +1034,3 @@ Test VSX scalar integer conversion instructions
|
||||
#14: xscvuxddp c0d0650f5a07b353 => 43e81a0ca1eb40f6
|
||||
|
||||
|
||||
Testcase PASSED
|
||||
|
||||
@ -39,6 +39,13 @@ typedef uint64_t HWord_t;
|
||||
typedef unsigned char Bool;
|
||||
#define True 1
|
||||
#define False 0
|
||||
|
||||
#ifdef VGP_ppc64le_linux
|
||||
#define isLE 1
|
||||
#else
|
||||
#define isLE 0
|
||||
#endif
|
||||
|
||||
register HWord_t r14 __asm__ ("r14");
|
||||
register HWord_t r15 __asm__ ("r15");
|
||||
register HWord_t r16 __asm__ ("r16");
|
||||
@ -798,8 +805,20 @@ static void test_xxspltw(void)
|
||||
{
|
||||
int uim;
|
||||
unsigned long long * dst = NULL;
|
||||
unsigned long long xb[] = { 0xfedc432124681235ULL, 0xf1e2d3c4e0057708ULL};
|
||||
memcpy(&vec_inB, xb, 16);
|
||||
unsigned int xb[] = { 0xfedc4321, 0x24681235, 0xf1e2d3c4, 0xe0057708};
|
||||
int i;
|
||||
void * vecB_ptr = &vec_inB;
|
||||
if (isLE) {
|
||||
for (i = 3; i >=0; i--) {
|
||||
memcpy(vecB_ptr, &xb[i], 4);
|
||||
vecB_ptr+=4;
|
||||
}
|
||||
} else {
|
||||
for (i = 0; i < 4; i++) {
|
||||
memcpy(vecB_ptr, &xb[i], 4);
|
||||
vecB_ptr+=4;
|
||||
}
|
||||
}
|
||||
|
||||
for (uim = 0; uim < 4; uim++) {
|
||||
switch (uim) {
|
||||
@ -817,7 +836,8 @@ static void test_xxspltw(void)
|
||||
break;
|
||||
}
|
||||
dst = (unsigned long long *) &vec_out;
|
||||
printf("xxspltw 0x%016llx%016llx %d=> 0x%016llx", xb[0], xb[1], uim, *dst);
|
||||
printf("xxspltw 0x%08x%08x%08x%08x %d=> 0x%016llx", xb[0], xb[1],
|
||||
xb[2], xb[3], uim, *dst);
|
||||
dst++;
|
||||
printf("%016llx\n", *dst);
|
||||
}
|
||||
@ -1226,22 +1246,33 @@ static void test_vx_simple_scalar_fp_ops(void)
|
||||
* (e.g. xssqrtdp).
|
||||
*/
|
||||
if (test_group.num_tests == nb_special_fargs && !test_group.targs) {
|
||||
void * inB;
|
||||
void * inB, * vec_void_ptr = (void *)&vec_inB;
|
||||
int i;
|
||||
if (isLE)
|
||||
vec_void_ptr += 8;
|
||||
for (i = 0; i < nb_special_fargs; i++) {
|
||||
inB = (void *)&spec_fargs[i];
|
||||
frbp = (unsigned long long *)&spec_fargs[i];
|
||||
memcpy(&vec_inB, inB, 8);
|
||||
memcpy(vec_void_ptr, inB, 8);
|
||||
(*func)();
|
||||
dst = (unsigned long long *) &vec_out;
|
||||
if (isLE)
|
||||
dst++;
|
||||
printf("#%d: %s %016llx => %016llx\n", i, test_group.name, *frbp,
|
||||
convToWord ? (*dst & 0x00000000ffffffffULL) : *dst);
|
||||
}
|
||||
} else {
|
||||
void * inA, * inB;
|
||||
void * inA, * inB, * vecA_void_ptr, * vecB_void_ptr;
|
||||
unsigned int condreg, flags;
|
||||
int isTdiv = (strstr(test_group.name, "xstdivdp") != NULL) ? 1 : 0;
|
||||
int i;
|
||||
if (isLE) {
|
||||
vecA_void_ptr = (void *)&vec_inA + 8;
|
||||
vecB_void_ptr = (void *)&vec_inB + 8;
|
||||
} else {
|
||||
vecA_void_ptr = (void *)&vec_inA;
|
||||
vecB_void_ptr = (void *)&vec_inB;
|
||||
}
|
||||
for (i = 0; i < test_group.num_tests; i++) {
|
||||
fp_test_args_t aTest = test_group.targs[i];
|
||||
inA = (void *)&spec_fargs[aTest.fra_idx];
|
||||
@ -1249,8 +1280,8 @@ static void test_vx_simple_scalar_fp_ops(void)
|
||||
frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
|
||||
frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
|
||||
// Only need to copy one doubleword into each vector's element 0
|
||||
memcpy(&vec_inA, inA, 8);
|
||||
memcpy(&vec_inB, inB, 8);
|
||||
memcpy(vecA_void_ptr, inA, 8);
|
||||
memcpy(vecB_void_ptr, inB, 8);
|
||||
SET_FPSCR_ZERO;
|
||||
SET_CR_XER_ZERO;
|
||||
(*func)();
|
||||
@ -1260,6 +1291,8 @@ static void test_vx_simple_scalar_fp_ops(void)
|
||||
printf("#%d: %s %016llx,%016llx => cr %x\n", i, test_group.name, *frap, *frbp, condreg);
|
||||
} else {
|
||||
dst = (unsigned long long *) &vec_out;
|
||||
if (isLE)
|
||||
dst++;
|
||||
printf("#%d: %s %016llx,%016llx => %016llx\n", i, test_group.name,
|
||||
*frap, *frbp, *dst);
|
||||
}
|
||||
@ -1346,21 +1379,26 @@ again:
|
||||
* src3 <= VSX[XB]
|
||||
*/
|
||||
if (scalar) {
|
||||
#ifdef VGP_ppc64le_linux
|
||||
#define VECTOR_ADDR(_v) ((void *)&_v) + 8
|
||||
#else
|
||||
#define VECTOR_ADDR(_v) ((void *)&_v)
|
||||
#endif
|
||||
// For scalar op, only need to copy one doubleword into each vector's element 0
|
||||
inA = (void *)&spec_fargs[aTest.fra_idx];
|
||||
inB = (void *)&spec_fargs[aTest.frb_idx];
|
||||
frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
|
||||
memcpy(&vec_inA, inA, 8);
|
||||
memcpy(VECTOR_ADDR(vec_inA), inA, 8);
|
||||
if (repeat) {
|
||||
memcpy(&vec_out, inB, 8); // src2
|
||||
memcpy(&vec_inB, &spec_fargs[fp_idx[0]], 8); //src3
|
||||
memcpy(VECTOR_ADDR(vec_out), inB, 8); // src2
|
||||
memcpy(VECTOR_ADDR(vec_inB), &spec_fargs[fp_idx[0]], 8); //src3
|
||||
frbp = (unsigned long long *)&spec_fargs[fp_idx[0]];
|
||||
} else {
|
||||
frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
|
||||
memcpy(&vec_inB, inB, 8); // src2
|
||||
memcpy(&vec_out, &spec_fargs[fp_idx[0]], 8); //src3
|
||||
memcpy(VECTOR_ADDR(vec_inB), inB, 8); // src2
|
||||
memcpy(VECTOR_ADDR(vec_out), &spec_fargs[fp_idx[0]], 8); //src3
|
||||
}
|
||||
memcpy(vsr_XT, &vec_out, 8);
|
||||
memcpy(vsr_XT, VECTOR_ADDR(vec_out), 8);
|
||||
} else {
|
||||
int j, loops = do_dp ? 2 : 4;
|
||||
size_t len = do_dp ? 8 : 4;
|
||||
@ -1382,6 +1420,8 @@ again:
|
||||
|
||||
(*func)();
|
||||
dst = (unsigned long long *) &vec_out;
|
||||
if (isLE)
|
||||
dst++;
|
||||
if (test_type < VX_VECTOR_FP_MULT_AND_OP2)
|
||||
printf( "#%d: %s %s(%016llx,%016llx,%016llx) = %016llx\n", i,
|
||||
test_name, test_group.op, vsr_XT[0], *frap, *frbp, *dst );
|
||||
|
||||
@ -36,6 +36,12 @@ typedef uint32_t HWord_t;
|
||||
typedef uint64_t HWord_t;
|
||||
#endif /* __powerpc64__ */
|
||||
|
||||
#ifdef VGP_ppc64le_linux
|
||||
#define isLE 1
|
||||
#else
|
||||
#define isLE 0
|
||||
#endif
|
||||
|
||||
typedef unsigned char Bool;
|
||||
#define True 1
|
||||
#define False 0
|
||||
@ -1116,7 +1122,7 @@ static void test_vsx_one_fp_arg(void)
|
||||
|
||||
for (i = 0; i < test_group.num_tests; i+=stride) {
|
||||
unsigned int * pv;
|
||||
void * inB;
|
||||
void * inB, * vecB_void_ptr = (void *)&vec_inB;
|
||||
|
||||
pv = (unsigned int *)&vec_out;
|
||||
// clear vec_out
|
||||
@ -1129,11 +1135,15 @@ static void test_vsx_one_fp_arg(void)
|
||||
for (j = 0; j < loops; j++) {
|
||||
inB = (void *)&spec_fargs[i + j];
|
||||
// copy double precision FP into vector element i
|
||||
memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
|
||||
if (isLE && is_scalar)
|
||||
vecB_void_ptr += 8;
|
||||
memcpy(vecB_void_ptr + (j * 8), inB, 8);
|
||||
}
|
||||
// execute test insn
|
||||
(*func)();
|
||||
dst_dp = (unsigned long long *) &vec_out;
|
||||
if (isLE && is_scalar)
|
||||
dst_dp++;
|
||||
printf("#%d: %s ", i/stride, test_group.name);
|
||||
for (j = 0; j < loops; j++) {
|
||||
if (j)
|
||||
@ -1141,7 +1151,7 @@ static void test_vsx_one_fp_arg(void)
|
||||
frB_dp = (unsigned long long *)&spec_fargs[i + j];
|
||||
printf("%s(%016llx)", test_group.op, *frB_dp);
|
||||
if (estimate) {
|
||||
Bool res = check_estimate(DOUBLE_TEST, is_sqrt, i + j, j);
|
||||
Bool res = check_estimate(DOUBLE_TEST, is_sqrt, i + j, (isLE && is_scalar) ? 1: j);
|
||||
printf(" ==> %s)", res ? "PASS" : "FAIL");
|
||||
/* For debugging . . .
|
||||
printf(" ==> %s (res=%016llx)", res ? "PASS" : "FAIL", dst_dp[j]);
|
||||
@ -1162,29 +1172,36 @@ static void test_vsx_one_fp_arg(void)
|
||||
}
|
||||
printf("\n");
|
||||
} else {
|
||||
int j, skip_slot;
|
||||
int j;
|
||||
unsigned int * frB_sp, * dst_sp = NULL;
|
||||
unsigned long long * dst_dp = NULL;
|
||||
if (sparse_sp) {
|
||||
skip_slot = 1;
|
||||
if (sparse_sp)
|
||||
loops = 2;
|
||||
} else {
|
||||
skip_slot = 0;
|
||||
}
|
||||
for (j = 0; j < loops; j++) {
|
||||
inB = (void *)&spec_sp_fargs[i + j];
|
||||
// copy single precision FP into vector element i
|
||||
if (skip_slot && j > 0)
|
||||
memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4);
|
||||
else
|
||||
memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
|
||||
if (sparse_sp) {
|
||||
if (isLE)
|
||||
memcpy(vecB_void_ptr + ((2 * j * 4) + 4), inB, 4);
|
||||
else
|
||||
memcpy(vecB_void_ptr + ((2 * j * 4) ), inB, 4);
|
||||
} else {
|
||||
if (isLE && is_scalar)
|
||||
vecB_void_ptr += 12;
|
||||
memcpy(vecB_void_ptr + (j * 4), inB, 4);
|
||||
}
|
||||
}
|
||||
// execute test insn
|
||||
(*func)();
|
||||
if (test_group.type == VX_CONV_TO_DOUBLE)
|
||||
if (test_group.type == VX_CONV_TO_DOUBLE) {
|
||||
dst_dp = (unsigned long long *) &vec_out;
|
||||
else
|
||||
if (isLE && is_scalar)
|
||||
dst_dp++;
|
||||
} else {
|
||||
dst_sp = (unsigned int *) &vec_out;
|
||||
if (isLE && is_scalar)
|
||||
dst_sp += 3;
|
||||
}
|
||||
// print result
|
||||
printf("#%d: %s ", i/stride, test_group.name);
|
||||
for (j = 0; j < loops; j++) {
|
||||
@ -1193,7 +1210,7 @@ static void test_vsx_one_fp_arg(void)
|
||||
frB_sp = (unsigned int *)&spec_sp_fargs[i + j];
|
||||
printf("%s(%08x)", test_group.op, *frB_sp);
|
||||
if (estimate) {
|
||||
Bool res = check_estimate(SINGLE_TEST, is_sqrt, i + j, j);
|
||||
Bool res = check_estimate(SINGLE_TEST, is_sqrt, i + j, (isLE && is_scalar) ? 3 : j);
|
||||
printf(" ==> %s)", res ? "PASS" : "FAIL");
|
||||
} else {
|
||||
if (test_group.type == VX_CONV_TO_DOUBLE)
|
||||
@ -1275,23 +1292,24 @@ static void test_int_to_fp_convert(void)
|
||||
}
|
||||
printf("\n");
|
||||
} else {
|
||||
int j, skip_slot;
|
||||
int j;
|
||||
unsigned int * dst_sp = NULL;
|
||||
unsigned int * targs = test_group.targs;
|
||||
unsigned long long * dst_dp = NULL;
|
||||
if (sparse_sp) {
|
||||
skip_slot = 1;
|
||||
void * vecB_void_ptr = (void *)&vec_inB;
|
||||
if (sparse_sp)
|
||||
loops = 2;
|
||||
} else {
|
||||
skip_slot = 0;
|
||||
}
|
||||
for (j = 0; j < loops; j++) {
|
||||
inB = (void *)&targs[i + j];
|
||||
// copy single word into vector element i
|
||||
if (skip_slot && j > 0)
|
||||
memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4);
|
||||
else
|
||||
memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
|
||||
if (sparse_sp) {
|
||||
if (isLE)
|
||||
memcpy(vecB_void_ptr + ((2 * j * 4) + 4), inB, 4);
|
||||
else
|
||||
memcpy(vecB_void_ptr + ((2 * j * 4) ), inB, 4);
|
||||
} else {
|
||||
memcpy(vecB_void_ptr + (j * 4), inB, 4);
|
||||
}
|
||||
}
|
||||
// execute test insn
|
||||
(*func)();
|
||||
@ -1441,7 +1459,7 @@ static void test_vx_tdivORtsqrt(void)
|
||||
|
||||
for (i = 0; i < test_group.num_tests; i+=stride) {
|
||||
unsigned int * pv;
|
||||
void * inB;
|
||||
void * inB, * vecB_void_ptr = (void *)&vec_inB;
|
||||
|
||||
pv = (unsigned int *)&vec_out;
|
||||
// clear vec_out
|
||||
@ -1457,7 +1475,9 @@ static void test_vx_tdivORtsqrt(void)
|
||||
for (j = 0; j < loops; j++) {
|
||||
inB = (void *)&spec_fargs[i + j];
|
||||
// copy double precision FP into vector element i
|
||||
memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
|
||||
if (isLE && is_scalar)
|
||||
vecB_void_ptr += 8;
|
||||
memcpy(vecB_void_ptr + (j * 8), inB, 8);
|
||||
}
|
||||
}
|
||||
// execute test insn
|
||||
|
||||
@ -651,26 +651,26 @@ Test VSX floating point instructions
|
||||
|
||||
|
||||
Test VSX vector and scalar single argument instructions
|
||||
#0: xscvdpspn conv(3ec00000) = 3ec00000
|
||||
#1: xscvdpspn conv(42780000) = 42780000
|
||||
#2: xscvdpspn conv(00000000) = 00000000
|
||||
#3: xscvdpspn conv(7f800000) = 7f800000
|
||||
#4: xscvdpspn conv(00000000) = 00000000
|
||||
#5: xscvdpspn conv(00000000) = 00000000
|
||||
#6: xscvdpspn conv(80000000) = 80000000
|
||||
#7: xscvdpspn conv(7f800000) = 7f800000
|
||||
#8: xscvdpspn conv(ff800000) = ff800000
|
||||
#9: xscvdpspn conv(7fbfffff) = 7fbfffff
|
||||
#10: xscvdpspn conv(ffbfffff) = ffbfffff
|
||||
#11: xscvdpspn conv(7fc00000) = 7fc00000
|
||||
#12: xscvdpspn conv(ffc00000) = ffc00000
|
||||
#13: xscvdpspn conv(80000000) = 80000000
|
||||
#14: xscvdpspn conv(c683287b) = c683287b
|
||||
#15: xscvdpspn conv(49192c2d) = 49192c2d
|
||||
#16: xscvdpspn conv(49c1288d) = 49c1288d
|
||||
#17: xscvdpspn conv(418977ad) = 418977ad
|
||||
#18: xscvdpspn conv(428a5faf) = 428a5faf
|
||||
#19: xscvdpspn conv(44bb5fcc) = 44bb5fcc
|
||||
#0: xscvdpspn conv(3fd8000000000000) = 3ec00000
|
||||
#1: xscvdpspn conv(404f000000000000) = 42780000
|
||||
#2: xscvdpspn conv(0018000000b77501) = 00000000
|
||||
#3: xscvdpspn conv(7fe800000000051b) = 7f800000
|
||||
#4: xscvdpspn conv(0123214569900000) = 00000000
|
||||
#5: xscvdpspn conv(0000000000000000) = 00000000
|
||||
#6: xscvdpspn conv(8000000000000000) = 80000000
|
||||
#7: xscvdpspn conv(7ff0000000000000) = 7f800000
|
||||
#8: xscvdpspn conv(fff0000000000000) = ff800000
|
||||
#9: xscvdpspn conv(7ff7ffffffffffff) = 7fbfffff
|
||||
#10: xscvdpspn conv(fff7ffffffffffff) = ffbfffff
|
||||
#11: xscvdpspn conv(7ff8000000000000) = 7fc00000
|
||||
#12: xscvdpspn conv(fff8000000000000) = ffc00000
|
||||
#13: xscvdpspn conv(8008340000078000) = 80000000
|
||||
#14: xscvdpspn conv(c0d0650f5a07b353) = c683287b
|
||||
#15: xscvdpspn conv(41232585a9900000) = 49192c2d
|
||||
#16: xscvdpspn conv(41382511a2000000) = 49c1288d
|
||||
#17: xscvdpspn conv(40312ef5a9300000) = 418977ad
|
||||
#18: xscvdpspn conv(40514bf5d2300000) = 428a5faf
|
||||
#19: xscvdpspn conv(40976bf982440000) = 44bb5fcc
|
||||
|
||||
#0: xscvspdpn conv(3ec00000) = 3fd8000000000000
|
||||
#1: xscvspdpn conv(42780000) = 404f000000000000
|
||||
@ -783,23 +783,15 @@ Test VSX logic instructions
|
||||
#2: xxlnand (80000001 89abcdef 00112233 74556677, 80000001 89abcdef 00112233 74556677) ==> 7ffffffe 76543210 ffeeddcc 8baa9988
|
||||
|
||||
Test VSX scalar integer conversion instructions
|
||||
#0: xscvsxdsp 80000001 => c3e0000000000000
|
||||
#1: xscvsxdsp 89abcdef => c3dd950c80000000
|
||||
#2: xscvsxdsp 00112233 => 4331223380000000
|
||||
#3: xscvsxdsp 74556677 => 43dd1559a0000000
|
||||
#4: xscvsxdsp 00001abb => 42babb89a0000000
|
||||
#5: xscvsxdsp 00000001 => 41f89abce0000000
|
||||
#6: xscvsxdsp 31929394 => 43c8c949c0000000
|
||||
#7: xscvsxdsp a1a2a3a4 => c3d7975720000000
|
||||
#0: xscvsxdsp 0102030405060708 => 4370203040000000
|
||||
#1: xscvsxdsp 090a0b0c0e0d0e0f => 43a2141620000000
|
||||
#2: xscvsxdsp f1f2f3f4f5f6f7f8 => c3ac1a1820000000
|
||||
#3: xscvsxdsp f9fafbfcfefdfeff => c398141000000000
|
||||
|
||||
#0: xscvuxdsp 80000001 => 43e0000000000000
|
||||
#1: xscvuxdsp 89abcdef => 43e13579c0000000
|
||||
#2: xscvuxdsp 00112233 => 4331223380000000
|
||||
#3: xscvuxdsp 74556677 => 43dd1559a0000000
|
||||
#4: xscvuxdsp 00001abb => 42babb89a0000000
|
||||
#5: xscvuxdsp 00000001 => 41f89abce0000000
|
||||
#6: xscvuxdsp 31929394 => 43c8c949c0000000
|
||||
#7: xscvuxdsp a1a2a3a4 => 43e4345480000000
|
||||
#0: xscvuxdsp 0102030405060708 => 4370203040000000
|
||||
#1: xscvuxdsp 090a0b0c0e0d0e0f => 43a2141620000000
|
||||
#2: xscvuxdsp f1f2f3f4f5f6f7f8 => 43ee3e5e80000000
|
||||
#3: xscvuxdsp f9fafbfcfefdfeff => 43ef3f5f80000000
|
||||
|
||||
|
||||
Test VSX load/store dp to sp instructions
|
||||
@ -812,14 +804,13 @@ stxsspx: 41232585a0000000 ==> 49192c2d
|
||||
stxsspx: 40514bf5e0000000 ==> 428a5faf
|
||||
|
||||
|
||||
stxsiwx: 80000001 ==> 80000001
|
||||
stxsiwx: 89abcdef ==> 89abcdef
|
||||
stxsiwx: 00112233 ==> 00112233
|
||||
stxsiwx: 74556677 ==> 74556677
|
||||
stxsiwx: 00001abb ==> 00001abb
|
||||
stxsiwx: 00000001 ==> 00000001
|
||||
stxsiwx: 31929394 ==> 31929394
|
||||
stxsiwx: a1a2a3a4 ==> a1a2a3a4
|
||||
stxsiwx: 3ec00000 ==> 3ec00000
|
||||
stxsiwx: 7f800000 ==> 7f800000
|
||||
stxsiwx: 80000000 ==> 80000000
|
||||
stxsiwx: 7fbfffff ==> 7fbfffff
|
||||
stxsiwx: ffc00000 ==> ffc00000
|
||||
stxsiwx: 49192c2d ==> 49192c2d
|
||||
stxsiwx: 428a5faf ==> 428a5faf
|
||||
|
||||
|
||||
lxsiwax: 80000001 ==> ffffffff80000001
|
||||
@ -832,14 +823,13 @@ lxsiwax: 31929394 ==> 0000000031929394
|
||||
lxsiwax: a1a2a3a4 ==> ffffffffa1a2a3a4
|
||||
|
||||
|
||||
lxsiwzx: 89abcdef ==> 00000000abcdef00
|
||||
lxsiwzx: 00112233 ==> 0000000011223374
|
||||
lxsiwzx: 74556677 ==> 0000000055667700
|
||||
lxsiwzx: 00001abb ==> 00000000001abb00
|
||||
lxsiwzx: 00000001 ==> 0000000000000131
|
||||
lxsiwzx: 31929394 ==> 00000000929394a1
|
||||
lxsiwzx: a1a2a3a4 ==> 00000000a2a3a410
|
||||
lxsiwzx: 10000b08 ==> 00000000000b0810
|
||||
lxsiwzx: 89abcdef ==> 0000000089abcdef
|
||||
lxsiwzx: 00112233 ==> 0000000000112233
|
||||
lxsiwzx: 74556677 ==> 0000000074556677
|
||||
lxsiwzx: 00001abb ==> 0000000000001abb
|
||||
lxsiwzx: 00000001 ==> 0000000000000001
|
||||
lxsiwzx: 31929394 ==> 0000000031929394
|
||||
lxsiwzx: a1a2a3a4 ==> 00000000a1a2a3a4
|
||||
|
||||
|
||||
lxsspx: 3ec00000 ==> 3fd8000000000000
|
||||
|
||||
@ -4,20 +4,20 @@ include $(top_srcdir)/Makefile.tool-tests.am
|
||||
dist_noinst_SCRIPTS = filter_stderr
|
||||
|
||||
EXTRA_DIST = \
|
||||
jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
|
||||
jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest \
|
||||
jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
|
||||
jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest jm-int.stdout.exp-LE \
|
||||
jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-LE jm-fp.stdout.exp-LE2 jm-fp.stdout.exp-BE2 \
|
||||
jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan jm-vmx.stdout.exp-LE \
|
||||
jm-vmx.vgtest \
|
||||
jm-misc.stderr.exp jm-misc.stdout.exp jm-misc.vgtest \
|
||||
lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
|
||||
std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp \
|
||||
round.stderr.exp round.stdout.exp round.vgtest \
|
||||
std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp std_reg_imm.stdout.exp-LE \
|
||||
round.stderr.exp round.stdout.exp round.vgtest round.stdout.exp-RM-fix \
|
||||
twi_tdi.stderr.exp twi_tdi.stdout.exp twi_tdi.vgtest \
|
||||
tw_td.stderr.exp tw_td.stdout.exp tw_td.vgtest \
|
||||
opcodes.h \
|
||||
power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \
|
||||
power6_mf_gpr.stderr.exp power6_mf_gpr.stdout.exp power6_mf_gpr.vgtest \
|
||||
test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
|
||||
test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest test_isa_2_06_part1.stdout.exp-LE \
|
||||
test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
|
||||
test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
|
||||
test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
|
||||
@ -85,33 +85,45 @@ test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_
|
||||
test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
|
||||
@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
|
||||
|
||||
test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \
|
||||
test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
|
||||
@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
|
||||
|
||||
jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \
|
||||
@FLAG_M64@ $(ALTIVEC_FLAG)
|
||||
|
||||
test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
||||
test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
||||
@FLAG_M64@ $(BUILD_FLAGS_DFP)
|
||||
|
||||
test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
||||
test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
||||
@FLAG_M64@ $(BUILD_FLAGS_DFP)
|
||||
test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
||||
test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
||||
@FLAG_M64@ $(BUILD_FLAGS_DFP)
|
||||
|
||||
test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
||||
test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
||||
@FLAG_M64@ $(BUILD_FLAGS_DFP)
|
||||
|
||||
test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
|
||||
test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
|
||||
@FLAG_M64@ $(BUILD_FLAGS_DFP)
|
||||
|
||||
test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
|
||||
test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
|
||||
@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
|
||||
|
||||
test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
|
||||
test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
|
||||
@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
|
||||
|
||||
test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
|
||||
test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
|
||||
@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
|
||||
test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
|
||||
test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
|
||||
@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
|
||||
|
||||
test_isa_2_06_part3_LDADD = -lm
|
||||
test_dfp1_LDADD = -lm
|
||||
test_dfp2_LDADD = -lm
|
||||
test_dfp3_LDADD = -lm
|
||||
test_dfp4_LDADD = -lm
|
||||
test_dfp5_LDADD = -lm
|
||||
test_isa_2_07_part1_LDADD = -lm
|
||||
test_isa_2_07_part2_LDADD = -lm
|
||||
test_tm_LDADD = -lm
|
||||
test_touch_tm_LDADD = -lm
|
||||
|
||||
|
||||
@ -692,11 +692,11 @@ PPC floating point compare insns (two args):
|
||||
PPC floating point arith insns with one arg:
|
||||
fres 0010000000000001 => 7ff0000000000000
|
||||
fres 00100094e0000359 => 7ff0000000000000
|
||||
fres 3fe0000000000001 => 4000000000000000
|
||||
fres 3fe0000000000001 => 3ffff00000000000
|
||||
fres 3fe00094e0000359 => 3ffff00000000000
|
||||
fres 8010000000000001 => fff0000000000000
|
||||
fres 80100094e0000359 => fff0000000000000
|
||||
fres bfe0000000000001 => c000000000000000
|
||||
fres bfe0000000000001 => bffff00000000000
|
||||
fres bfe00094e0000359 => bffff00000000000
|
||||
fres 0000000000000000 => 7ff0000000000000
|
||||
fres 8000000000000000 => fff0000000000000
|
||||
@ -915,11 +915,11 @@ PPC floating point arith insns
|
||||
with one arg with flags update:
|
||||
fres. 0010000000000001 => 7ff0000000000000
|
||||
fres. 00100094e0000359 => 7ff0000000000000
|
||||
fres. 3fe0000000000001 => 4000000000000000
|
||||
fres. 3fe0000000000001 => 3ffff00000000000
|
||||
fres. 3fe00094e0000359 => 3ffff00000000000
|
||||
fres. 8010000000000001 => fff0000000000000
|
||||
fres. 80100094e0000359 => fff0000000000000
|
||||
fres. bfe0000000000001 => c000000000000000
|
||||
fres. bfe0000000000001 => bffff00000000000
|
||||
fres. bfe00094e0000359 => bffff00000000000
|
||||
fres. 0000000000000000 => 7ff0000000000000
|
||||
fres. 8000000000000000 => fff0000000000000
|
||||
@ -1122,21 +1122,21 @@ PPC floating point status register manipulation insns
|
||||
with flags update:
|
||||
PPC float load insns
|
||||
with one register + one 16 bits immediate args with flags update:
|
||||
lfs 0010000000000001, -120 => 37e0000000000000, 0
|
||||
lfs 00100094e0000359, -112 => 37e0009400000000, 0
|
||||
lfs 3fe0000000000001, -104 => 3ffc000000000000, 0
|
||||
lfs 3fe00094e0000359, -96 => 3ffc001280000000, 0
|
||||
lfs 8010000000000001, -88 => b7e0000000000000, 0
|
||||
lfs 80100094e0000359, -80 => b7e0009400000000, 0
|
||||
lfs bfe0000000000001, -72 => bffc000000000000, 0
|
||||
lfs bfe00094e0000359, -64 => bffc001280000000, 0
|
||||
lfs 0000000000000000, -56 => 0000000000000000, 0
|
||||
lfs 8000000000000000, -48 => 8000000000000000, 0
|
||||
lfs 7ff0000000000000, -40 => 7ffe000000000000, 0
|
||||
lfs fff0000000000000, -32 => fffe000000000000, 0
|
||||
lfs 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 0
|
||||
lfs fff7ffffffffffff, -16 => fffeffffe0000000, 0
|
||||
lfs 7ff8000000000000, -8 => 7fff000000000000, 0
|
||||
lfs 0010000000000001, 65416 => 37e0000000000000, 0
|
||||
lfs 00100094e0000359, 65424 => 37e0009400000000, 0
|
||||
lfs 3fe0000000000001, 65432 => 3ffc000000000000, 0
|
||||
lfs 3fe00094e0000359, 65440 => 3ffc001280000000, 0
|
||||
lfs 8010000000000001, 65448 => b7e0000000000000, 0
|
||||
lfs 80100094e0000359, 65456 => b7e0009400000000, 0
|
||||
lfs bfe0000000000001, 65464 => bffc000000000000, 0
|
||||
lfs bfe00094e0000359, 65472 => bffc001280000000, 0
|
||||
lfs 0000000000000000, 65480 => 0000000000000000, 0
|
||||
lfs 8000000000000000, 65488 => 8000000000000000, 0
|
||||
lfs 7ff0000000000000, 65496 => 7ffe000000000000, 0
|
||||
lfs fff0000000000000, 65504 => fffe000000000000, 0
|
||||
lfs 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, 0
|
||||
lfs fff7ffffffffffff, 65520 => fffeffffe0000000, 0
|
||||
lfs 7ff8000000000000, 65528 => 7fff000000000000, 0
|
||||
lfs 0010000000000001, 0 => 37e0000000000000, 0
|
||||
lfs 00100094e0000359, 8 => 37e0009400000000, 0
|
||||
lfs 3fe0000000000001, 16 => 3ffc000000000000, 0
|
||||
@ -1154,21 +1154,21 @@ PPC float load insns
|
||||
lfs 7ff8000000000000, 112 => 7fff000000000000, 0
|
||||
lfs fff8000000000000, 120 => ffff000000000000, 0
|
||||
|
||||
lfsu 0010000000000001, -120 => 37e0000000000000, -120
|
||||
lfsu 00100094e0000359, -112 => 37e0009400000000, -112
|
||||
lfsu 3fe0000000000001, -104 => 3ffc000000000000, -104
|
||||
lfsu 3fe00094e0000359, -96 => 3ffc001280000000, -96
|
||||
lfsu 8010000000000001, -88 => b7e0000000000000, -88
|
||||
lfsu 80100094e0000359, -80 => b7e0009400000000, -80
|
||||
lfsu bfe0000000000001, -72 => bffc000000000000, -72
|
||||
lfsu bfe00094e0000359, -64 => bffc001280000000, -64
|
||||
lfsu 0000000000000000, -56 => 0000000000000000, -56
|
||||
lfsu 8000000000000000, -48 => 8000000000000000, -48
|
||||
lfsu 7ff0000000000000, -40 => 7ffe000000000000, -40
|
||||
lfsu fff0000000000000, -32 => fffe000000000000, -32
|
||||
lfsu 7ff7ffffffffffff, -24 => 7ffeffffe0000000, -24
|
||||
lfsu fff7ffffffffffff, -16 => fffeffffe0000000, -16
|
||||
lfsu 7ff8000000000000, -8 => 7fff000000000000, -8
|
||||
lfsu 0010000000000001, 65416 => 37e0000000000000, -120
|
||||
lfsu 00100094e0000359, 65424 => 37e0009400000000, -112
|
||||
lfsu 3fe0000000000001, 65432 => 3ffc000000000000, -104
|
||||
lfsu 3fe00094e0000359, 65440 => 3ffc001280000000, -96
|
||||
lfsu 8010000000000001, 65448 => b7e0000000000000, -88
|
||||
lfsu 80100094e0000359, 65456 => b7e0009400000000, -80
|
||||
lfsu bfe0000000000001, 65464 => bffc000000000000, -72
|
||||
lfsu bfe00094e0000359, 65472 => bffc001280000000, -64
|
||||
lfsu 0000000000000000, 65480 => 0000000000000000, -56
|
||||
lfsu 8000000000000000, 65488 => 8000000000000000, -48
|
||||
lfsu 7ff0000000000000, 65496 => 7ffe000000000000, -40
|
||||
lfsu fff0000000000000, 65504 => fffe000000000000, -32
|
||||
lfsu 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, -24
|
||||
lfsu fff7ffffffffffff, 65520 => fffeffffe0000000, -16
|
||||
lfsu 7ff8000000000000, 65528 => 7fff000000000000, -8
|
||||
lfsu 0010000000000001, 0 => 37e0000000000000, 0
|
||||
lfsu 00100094e0000359, 8 => 37e0009400000000, 8
|
||||
lfsu 3fe0000000000001, 16 => 3ffc000000000000, 16
|
||||
@ -1186,21 +1186,21 @@ PPC float load insns
|
||||
lfsu 7ff8000000000000, 112 => 7fff000000000000, 112
|
||||
lfsu fff8000000000000, 120 => ffff000000000000, 120
|
||||
|
||||
lfd 0010000000000001, -120 => 0010000000000001, 0
|
||||
lfd 00100094e0000359, -112 => 00100094e0000359, 0
|
||||
lfd 3fe0000000000001, -104 => 3fe0000000000001, 0
|
||||
lfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0
|
||||
lfd 8010000000000001, -88 => 8010000000000001, 0
|
||||
lfd 80100094e0000359, -80 => 80100094e0000359, 0
|
||||
lfd bfe0000000000001, -72 => bfe0000000000001, 0
|
||||
lfd bfe00094e0000359, -64 => bfe00094e0000359, 0
|
||||
lfd 0000000000000000, -56 => 0000000000000000, 0
|
||||
lfd 8000000000000000, -48 => 8000000000000000, 0
|
||||
lfd 7ff0000000000000, -40 => 7ff0000000000000, 0
|
||||
lfd fff0000000000000, -32 => fff0000000000000, 0
|
||||
lfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
|
||||
lfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0
|
||||
lfd 7ff8000000000000, -8 => 7ff8000000000000, 0
|
||||
lfd 0010000000000001, 65416 => 0010000000000001, 0
|
||||
lfd 00100094e0000359, 65424 => 00100094e0000359, 0
|
||||
lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0
|
||||
lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0
|
||||
lfd 8010000000000001, 65448 => 8010000000000001, 0
|
||||
lfd 80100094e0000359, 65456 => 80100094e0000359, 0
|
||||
lfd bfe0000000000001, 65464 => bfe0000000000001, 0
|
||||
lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0
|
||||
lfd 0000000000000000, 65480 => 0000000000000000, 0
|
||||
lfd 8000000000000000, 65488 => 8000000000000000, 0
|
||||
lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0
|
||||
lfd fff0000000000000, 65504 => fff0000000000000, 0
|
||||
lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0
|
||||
lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0
|
||||
lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0
|
||||
lfd 0010000000000001, 0 => 0010000000000001, 0
|
||||
lfd 00100094e0000359, 8 => 00100094e0000359, 0
|
||||
lfd 3fe0000000000001, 16 => 3fe0000000000001, 0
|
||||
@ -1218,21 +1218,21 @@ PPC float load insns
|
||||
lfd 7ff8000000000000, 112 => 7ff8000000000000, 0
|
||||
lfd fff8000000000000, 120 => fff8000000000000, 0
|
||||
|
||||
lfdu 0010000000000001, -120 => 0010000000000001, -120
|
||||
lfdu 00100094e0000359, -112 => 00100094e0000359, -112
|
||||
lfdu 3fe0000000000001, -104 => 3fe0000000000001, -104
|
||||
lfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96
|
||||
lfdu 8010000000000001, -88 => 8010000000000001, -88
|
||||
lfdu 80100094e0000359, -80 => 80100094e0000359, -80
|
||||
lfdu bfe0000000000001, -72 => bfe0000000000001, -72
|
||||
lfdu bfe00094e0000359, -64 => bfe00094e0000359, -64
|
||||
lfdu 0000000000000000, -56 => 0000000000000000, -56
|
||||
lfdu 8000000000000000, -48 => 8000000000000000, -48
|
||||
lfdu 7ff0000000000000, -40 => 7ff0000000000000, -40
|
||||
lfdu fff0000000000000, -32 => fff0000000000000, -32
|
||||
lfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
|
||||
lfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16
|
||||
lfdu 7ff8000000000000, -8 => 7ff8000000000000, -8
|
||||
lfdu 0010000000000001, 65416 => 0010000000000001, -120
|
||||
lfdu 00100094e0000359, 65424 => 00100094e0000359, -112
|
||||
lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104
|
||||
lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96
|
||||
lfdu 8010000000000001, 65448 => 8010000000000001, -88
|
||||
lfdu 80100094e0000359, 65456 => 80100094e0000359, -80
|
||||
lfdu bfe0000000000001, 65464 => bfe0000000000001, -72
|
||||
lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64
|
||||
lfdu 0000000000000000, 65480 => 0000000000000000, -56
|
||||
lfdu 8000000000000000, 65488 => 8000000000000000, -48
|
||||
lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40
|
||||
lfdu fff0000000000000, 65504 => fff0000000000000, -32
|
||||
lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24
|
||||
lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16
|
||||
lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8
|
||||
lfdu 0010000000000001, 0 => 0010000000000001, 0
|
||||
lfdu 00100094e0000359, 8 => 00100094e0000359, 8
|
||||
lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
|
||||
|
||||
1533
none/tests/ppc64/jm-fp.stdout.exp-BE2
Normal file
1533
none/tests/ppc64/jm-fp.stdout.exp-BE2
Normal file
File diff suppressed because it is too large
Load Diff
1533
none/tests/ppc64/jm-fp.stdout.exp-LE
Normal file
1533
none/tests/ppc64/jm-fp.stdout.exp-LE
Normal file
File diff suppressed because it is too large
Load Diff
1533
none/tests/ppc64/jm-fp.stdout.exp-LE2
Normal file
1533
none/tests/ppc64/jm-fp.stdout.exp-LE2
Normal file
File diff suppressed because it is too large
Load Diff
@ -4549,81 +4549,81 @@ PPC logical insns with special forms with flags update:
|
||||
PPC integer load insns
|
||||
with one register + one 16 bits immediate args with flags update:
|
||||
lbz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lbz 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lbz 16, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
|
||||
lbz -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lbz -8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lbz 0, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
|
||||
lbz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lbz 15, (ffffffffffffffff) => 00000000000000ef, 0 (00000000 00000000)
|
||||
lbz 1, (00000000ffffffff) => 00000000000000ff, 0 (00000000 00000000)
|
||||
lbz -7, (00000000be991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lbz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
|
||||
lbzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lbzu 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
|
||||
lbzu 16, (ffffffffffffffff) => 00000000000000ff, 16 (00000000 00000000)
|
||||
lbzu -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
||||
lbzu -8, (0000001cbe991def) => 0000000000000000, -8 (00000000 00000000)
|
||||
lbzu 0, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
|
||||
lbzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
|
||||
lbzu 15, (ffffffffffffffff) => 00000000000000ef, 15 (00000000 00000000)
|
||||
lbzu 1, (00000000ffffffff) => 00000000000000ff, 1 (00000000 00000000)
|
||||
lbzu -7, (00000000be991def) => 0000000000000000, -7 (00000000 00000000)
|
||||
lbzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
|
||||
|
||||
lha 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lha 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lha 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
||||
lha -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lha -8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lha 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
||||
lha 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lha 15, (ffffffffffffffff) => ffffffffffffefff, 0 (00000000 00000000)
|
||||
lha 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
||||
lha -7, (00000000be991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lha -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
|
||||
lhau 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lhau 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
|
||||
lhau 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
|
||||
lhau -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
||||
lhau -8, (0000001cbe991def) => 0000000000000000, -8 (00000000 00000000)
|
||||
lhau 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
||||
lhau 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
|
||||
lhau 15, (ffffffffffffffff) => ffffffffffffefff, 15 (00000000 00000000)
|
||||
lhau 1, (00000000ffffffff) => ffffffffffffffff, 1 (00000000 00000000)
|
||||
lhau -7, (00000000be991def) => 0000000000000000, -7 (00000000 00000000)
|
||||
lhau -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
|
||||
|
||||
lhz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lhz 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lhz 16, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
|
||||
lhz -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lhz -8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lhz 0, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
|
||||
lhz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lhz 15, (ffffffffffffffff) => 000000000000efff, 0 (00000000 00000000)
|
||||
lhz 1, (00000000ffffffff) => 000000000000ffff, 0 (00000000 00000000)
|
||||
lhz -7, (00000000be991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lhz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
|
||||
lhzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lhzu 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
|
||||
lhzu 16, (ffffffffffffffff) => 000000000000ffff, 16 (00000000 00000000)
|
||||
lhzu -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
||||
lhzu -8, (0000001cbe991def) => 0000000000000000, -8 (00000000 00000000)
|
||||
lhzu 0, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
|
||||
lhzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
|
||||
lhzu 15, (ffffffffffffffff) => 000000000000efff, 15 (00000000 00000000)
|
||||
lhzu 1, (00000000ffffffff) => 000000000000ffff, 1 (00000000 00000000)
|
||||
lhzu -7, (00000000be991def) => 0000000000000000, -7 (00000000 00000000)
|
||||
lhzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
|
||||
|
||||
lwz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lwz 8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
|
||||
lwz 16, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
|
||||
lwz -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lwz -8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
|
||||
lwz 0, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
|
||||
lwz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lwz 15, (ffffffffffffffff) => 00000000efffffff, 0 (00000000 00000000)
|
||||
lwz 1, (00000000ffffffff) => 00000000ffffffff, 0 (00000000 00000000)
|
||||
lwz -7, (00000000be991def) => 0000000000001cbe, 0 (00000000 00000000)
|
||||
lwz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
|
||||
lwzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lwzu 8, (0000001cbe991def) => 000000000000001c, 8 (00000000 00000000)
|
||||
lwzu 16, (ffffffffffffffff) => 00000000ffffffff, 16 (00000000 00000000)
|
||||
lwzu -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
||||
lwzu -8, (0000001cbe991def) => 000000000000001c, -8 (00000000 00000000)
|
||||
lwzu 0, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
|
||||
lwzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
|
||||
lwzu 15, (ffffffffffffffff) => 00000000efffffff, 15 (00000000 00000000)
|
||||
lwzu 1, (00000000ffffffff) => 00000000ffffffff, 1 (00000000 00000000)
|
||||
lwzu -7, (00000000be991def) => 0000000000001cbe, -7 (00000000 00000000)
|
||||
lwzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
|
||||
|
||||
ld 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
ld 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
|
||||
ld 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
||||
ld -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
ld -8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
|
||||
ld 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
||||
ld 7, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
|
||||
ld 15, (ffffffffffffffff) => be991defffffffff, 0 (00000000 00000000)
|
||||
ld 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
||||
ld -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
|
||||
ld -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
||||
|
||||
ldu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
ldu 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
|
||||
ldu 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
||||
ldu -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
ldu -8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
|
||||
ldu 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
||||
ldu 7, (0000001cbe991def) => 000000000000001c, 4 (00000000 00000000)
|
||||
ldu 15, (ffffffffffffffff) => be991defffffffff, 12 (00000000 00000000)
|
||||
ldu 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
||||
ldu -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
|
||||
ldu -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
||||
|
||||
lwa 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lwa 8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
|
||||
lwa 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
||||
lwa -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
lwa -8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
|
||||
lwa 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
||||
lwa 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
|
||||
lwa 15, (ffffffffffffffff) => ffffffffbe991def, 0 (00000000 00000000)
|
||||
lwa 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
|
||||
lwa -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
|
||||
lwa -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
|
||||
|
||||
PPC integer load insns with two register args:
|
||||
lbzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
|
||||
|
||||
4773
none/tests/ppc64/jm-int.stdout.exp-LE
Normal file
4773
none/tests/ppc64/jm-int.stdout.exp-LE
Normal file
File diff suppressed because it is too large
Load Diff
@ -1407,43 +1407,43 @@ Altivec integer special insns:
|
||||
vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
|
||||
vsldoi: => fefff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000)
|
||||
|
||||
lvsl -1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
|
||||
lvsl 0, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
|
||||
lvsl 1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
|
||||
lvsl 2, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
|
||||
lvsl 3, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
|
||||
lvsl 4, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
|
||||
lvsl 5, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
|
||||
lvsl 6, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
|
||||
lvsl 7, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
|
||||
lvsl 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
|
||||
lvsl 9, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
|
||||
lvsl 10, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
|
||||
lvsl 11, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
|
||||
lvsl 12, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
|
||||
lvsl 13, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
|
||||
lvsl 14, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
|
||||
lvsl 15, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
|
||||
lvsl 16, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
|
||||
lvsl 7, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
|
||||
lvsl 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
|
||||
lvsl 9, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
|
||||
lvsl a, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000)
|
||||
lvsl b, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000)
|
||||
lvsl c, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
|
||||
lvsl d, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
|
||||
lvsl e, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000)
|
||||
lvsl f, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000)
|
||||
lvsl 0, 0 => 0x0001020304050607 0x08090a0b0c0d0e0f (00000000)
|
||||
lvsl 1, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000)
|
||||
lvsl 2, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000)
|
||||
lvsl 3, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
|
||||
lvsl 4, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
|
||||
lvsl 5, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000)
|
||||
lvsl 6, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000)
|
||||
lvsl 7, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
|
||||
lvsl 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
|
||||
|
||||
lvsr -1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
|
||||
lvsr 0, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
|
||||
lvsr 1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
|
||||
lvsr 2, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
|
||||
lvsr 3, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
|
||||
lvsr 4, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
|
||||
lvsr 5, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
|
||||
lvsr 6, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
|
||||
lvsr 7, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
|
||||
lvsr 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
|
||||
lvsr 9, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
|
||||
lvsr 10, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
|
||||
lvsr 11, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
|
||||
lvsr 12, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
|
||||
lvsr 13, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
|
||||
lvsr 14, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
|
||||
lvsr 15, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
|
||||
lvsr 16, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
|
||||
lvsr 7, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
|
||||
lvsr 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
|
||||
lvsr 9, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
|
||||
lvsr a, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000)
|
||||
lvsr b, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000)
|
||||
lvsr c, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
|
||||
lvsr d, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
|
||||
lvsr e, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000)
|
||||
lvsr f, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000)
|
||||
lvsr 0, 0 => 0x1011121314151617 0x18191a1b1c1d1e1f (00000000)
|
||||
lvsr 1, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000)
|
||||
lvsr 2, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000)
|
||||
lvsr 3, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
|
||||
lvsr 4, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
|
||||
lvsr 5, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000)
|
||||
lvsr 6, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000)
|
||||
lvsr 7, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
|
||||
lvsr 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
|
||||
|
||||
Altivec load insns with two register args:
|
||||
lvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000000 00000000 00000000 (00000000)
|
||||
@ -3451,18 +3451,18 @@ Altivec float special insns:
|
||||
vcfux: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
|
||||
vcfux: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
|
||||
vcfux: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
|
||||
vcfux: ffffffff ( nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
|
||||
vcfux: ffffffff ( nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
|
||||
vcfux: ffffffff ( nan), 18 => 46800000 ( 1.638400e+04) (00000000)
|
||||
vcfux: ffffffff ( nan), 27 => 42000000 ( 3.200000e+01) (00000000)
|
||||
vcfux: ffffffff ( -nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
|
||||
vcfux: ffffffff ( -nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
|
||||
vcfux: ffffffff ( -nan), 18 => 46800000 ( 1.638400e+04) (00000000)
|
||||
vcfux: ffffffff ( -nan), 27 => 42000000 ( 3.200000e+01) (00000000)
|
||||
vcfux: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
|
||||
vcfux: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
|
||||
vcfux: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
|
||||
vcfux: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
|
||||
vcfux: ffbfffff ( nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
|
||||
vcfux: ffbfffff ( nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
|
||||
vcfux: ffbfffff ( nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
|
||||
vcfux: ffbfffff ( nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
|
||||
vcfux: ffbfffff ( -nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
|
||||
vcfux: ffbfffff ( -nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
|
||||
vcfux: ffbfffff ( -nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
|
||||
vcfux: ffbfffff ( -nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
|
||||
|
||||
vcfsx: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
|
||||
vcfsx: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
|
||||
@ -3500,27 +3500,27 @@ Altivec float special insns:
|
||||
vcfsx: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
|
||||
vcfsx: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
|
||||
vcfsx: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
|
||||
vcfsx: ffffffff ( nan), 0 => bf800000 (-1.000000e+00) (00000000)
|
||||
vcfsx: ffffffff ( nan), 9 => bb000000 (-1.953125e-03) (00000000)
|
||||
vcfsx: ffffffff ( nan), 18 => b6800000 (-3.814697e-06) (00000000)
|
||||
vcfsx: ffffffff ( nan), 27 => b2000000 (-7.450581e-09) (00000000)
|
||||
vcfsx: ffffffff ( -nan), 0 => bf800000 (-1.000000e+00) (00000000)
|
||||
vcfsx: ffffffff ( -nan), 9 => bb000000 (-1.953125e-03) (00000000)
|
||||
vcfsx: ffffffff ( -nan), 18 => b6800000 (-3.814697e-06) (00000000)
|
||||
vcfsx: ffffffff ( -nan), 27 => b2000000 (-7.450581e-09) (00000000)
|
||||
vcfsx: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
|
||||
vcfsx: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
|
||||
vcfsx: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
|
||||
vcfsx: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
|
||||
vcfsx: ffbfffff ( nan), 0 => ca800002 (-4.194305e+06) (00000000)
|
||||
vcfsx: ffbfffff ( nan), 9 => c6000002 (-8.192002e+03) (00000000)
|
||||
vcfsx: ffbfffff ( nan), 18 => c1800002 (-1.600000e+01) (00000000)
|
||||
vcfsx: ffbfffff ( nan), 27 => bd000002 (-3.125001e-02) (00000000)
|
||||
vcfsx: ffbfffff ( -nan), 0 => ca800002 (-4.194305e+06) (00000000)
|
||||
vcfsx: ffbfffff ( -nan), 9 => c6000002 (-8.192002e+03) (00000000)
|
||||
vcfsx: ffbfffff ( -nan), 18 => c1800002 (-1.600000e+01) (00000000)
|
||||
vcfsx: ffbfffff ( -nan), 27 => bd000002 (-3.125001e-02) (00000000)
|
||||
|
||||
vctuxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
@ -3537,10 +3537,10 @@ Altivec float special insns:
|
||||
vctuxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 0 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 9 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 18 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 27 => ffffffff ( nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 0 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 9 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 18 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: 7f800000 ( inf), 27 => ffffffff ( -nan) (00000000)
|
||||
vctuxs: ff800000 ( -inf), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ff800000 ( -inf), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ff800000 ( -inf), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
@ -3549,18 +3549,18 @@ Altivec float special insns:
|
||||
vctuxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctuxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
|
||||
vctsxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
@ -3598,17 +3598,17 @@ Altivec float special insns:
|
||||
vctsxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
|
||||
vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
|
||||
|
||||
All done. Tested 165 different instructions
|
||||
|
||||
3614
none/tests/ppc64/jm-vmx.stdout.exp-LE
Normal file
3614
none/tests/ppc64/jm-vmx.stdout.exp-LE
Normal file
File diff suppressed because it is too large
Load Diff
@ -443,9 +443,9 @@ vsubuqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==
|
||||
vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0
|
||||
vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
|
||||
|
||||
vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000020a
|
||||
vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000020a0000000000000000
|
||||
vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
|
||||
vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000e3ea
|
||||
vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000e3ea0000000000000000
|
||||
vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
|
||||
|
||||
vaddecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000
|
||||
|
||||
@ -1 +1,2 @@
|
||||
prereq: ../../../tests/is_ppc64_BE
|
||||
prog: lsw
|
||||
|
||||
@ -49,19 +49,32 @@ typedef unsigned int fpscr_t;
|
||||
typedef union {
|
||||
float flt;
|
||||
struct {
|
||||
#if defined(VGP_ppc64le_linux)
|
||||
unsigned int frac:23;
|
||||
unsigned int exp:8;
|
||||
unsigned int sign:1;
|
||||
#else
|
||||
unsigned int sign:1;
|
||||
unsigned int exp:8;
|
||||
unsigned int frac:23;
|
||||
#endif
|
||||
} layout;
|
||||
} flt_overlay;
|
||||
|
||||
typedef union {
|
||||
double dbl;
|
||||
struct {
|
||||
#if defined(VGP_ppc64le_linux)
|
||||
unsigned int frac_lo:32;
|
||||
unsigned int frac_hi:20;
|
||||
unsigned int exp:11;
|
||||
unsigned int sign:1;
|
||||
#else
|
||||
unsigned int sign:1;
|
||||
unsigned int exp:11;
|
||||
unsigned int frac_hi:20;
|
||||
unsigned int frac_lo:32;
|
||||
#endif
|
||||
} layout;
|
||||
struct {
|
||||
unsigned int hi;
|
||||
@ -227,7 +240,7 @@ init()
|
||||
F.layout.frac = 1;
|
||||
denorm_small = F.flt; /* == 2^(-149) */
|
||||
if (debug) {
|
||||
print_double("float small", F.flt);
|
||||
print_single("float small", &F.flt);
|
||||
}
|
||||
|
||||
D.layout.sign = 0;
|
||||
|
||||
2384
none/tests/ppc64/round.stdout.exp-RM-fix
Normal file
2384
none/tests/ppc64/round.stdout.exp-RM-fix
Normal file
File diff suppressed because it is too large
Load Diff
1
none/tests/ppc64/std_reg_imm.stdout.exp-LE
Normal file
1
none/tests/ppc64/std_reg_imm.stdout.exp-LE
Normal file
@ -0,0 +1 @@
|
||||
....8877665544332211............
|
||||
@ -66,9 +66,9 @@ xxlandc: 00112233 44556677 8899aabb 91929394 xxlandc a1a2a3a4 b1b2b3b4 c1c2c3c4
|
||||
xxlandc: 44556677 8899aabb 91929394 a1a2a3a4 xxlandc b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 44454443 0819283b 00000000 8180a280
|
||||
|
||||
Test ldbrx instruction
|
||||
ldbrx: 01 23 45 67 89 ab cd (reverse) => ef cd ab 89 67 45 23 01
|
||||
ldbrx: 89 ab cd ef 00 11 22 (reverse) => 33 22 11 00 ef cd ab 89
|
||||
ldbrx: 00 11 22 33 44 55 66 (reverse) => 77 66 55 44 33 22 11 00
|
||||
ldbrx: 01 23 45 67 89 ab cd ef (reverse) => ef cd ab 89 67 45 23 01
|
||||
ldbrx: 89 ab cd ef 00 11 22 33 (reverse) => 33 22 11 00 ef cd ab 89
|
||||
ldbrx: 00 11 22 33 44 55 66 77 (reverse) => 77 66 55 44 33 22 11 00
|
||||
|
||||
Test popcntd instruction
|
||||
popcntd: 0x9182736405504536 => 24
|
||||
@ -138,13 +138,27 @@ ftdiv: 0000000000000000 <=> 0000000000000000 ? e (CRx)
|
||||
ftdiv: 0000000000000000 <=> 8000000000000000 ? e (CRx)
|
||||
|
||||
Test VSX move instructions
|
||||
xsabsdp: 01234567 89abcdef xsabsdp 8899aabb 91929394x => 0899aabb 91929394
|
||||
xsabsdp: X[B]: 0123456789abcdef => 0123456789abcdef
|
||||
xsabsdp: X[B]: 8899aabb19293942 => 0899aabb19293942
|
||||
xsabsdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
|
||||
|
||||
xscpsgndp: 8899aabb 91929394 xscpsgndp 01234567 89abcdefx => 81234567 89abcdef
|
||||
xscpsgndp: X[A]: 0123456789abcdef X[B]: 0123456789abcdef => 0123456789abcdef
|
||||
xscpsgndp: X[A]: 8899aabb19293942 X[B]: 0123456789abcdef => 8123456789abcdef
|
||||
xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 0123456789abcdef => 8123456789abcdef
|
||||
xscpsgndp: X[A]: 0123456789abcdef X[B]: 8899aabb19293942 => 0899aabb19293942
|
||||
xscpsgndp: X[A]: 8899aabb19293942 X[B]: 8899aabb19293942 => 8899aabb19293942
|
||||
xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 8899aabb19293942 => 8899aabb19293942
|
||||
xscpsgndp: X[A]: 0123456789abcdef X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
|
||||
xscpsgndp: X[A]: 8899aabb19293942 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
|
||||
xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
|
||||
|
||||
xsnabsdp: b1b2b3b4 c1c2c3c4 xsnabsdp 44556677 8899aabbx => c4556677 8899aabb
|
||||
xsnabsdp: X[B]: 0123456789abcdef => 8123456789abcdef
|
||||
xsnabsdp: X[B]: 8899aabb19293942 => 8899aabb19293942
|
||||
xsnabsdp: X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
|
||||
|
||||
xsnegdp: 01234567 89abcdef xsnegdp b1b2b3b4 c1c2c3c4x => 31b2b3b4 c1c2c3c4
|
||||
xsnegdp: X[B]: 0123456789abcdef => 8123456789abcdef
|
||||
xsnegdp: X[B]: 8899aabb19293942 => 0899aabb19293942
|
||||
xsnegdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
|
||||
|
||||
Test VSX permute instructions
|
||||
xxmrghw:
|
||||
@ -1028,4 +1042,3 @@ Test VSX scalar integer conversion instructions
|
||||
#14: xscvuxddp c0d0650f5a07b353 => 43e81a0ca1eb40f6
|
||||
|
||||
|
||||
Testcase PASSED
|
||||
|
||||
1044
none/tests/ppc64/test_isa_2_06_part1.stdout.exp-LE
Normal file
1044
none/tests/ppc64/test_isa_2_06_part1.stdout.exp-LE
Normal file
File diff suppressed because it is too large
Load Diff
@ -135,6 +135,12 @@ typedef uint64_t HWord_t;
|
||||
#define ZERO 0ULL
|
||||
#endif /* __powerpc64__ */
|
||||
|
||||
#ifdef VGP_ppc64le_linux
|
||||
#define isLE 1
|
||||
#else
|
||||
#define isLE 0
|
||||
#endif
|
||||
|
||||
typedef uint64_t Word_t;
|
||||
|
||||
enum {
|
||||
@ -1116,7 +1122,10 @@ static void mfvs(const char* name, test_func_t func,
|
||||
|
||||
for (i=0; i < NB_VDARGS; i++) {
|
||||
r14 = ZERO;
|
||||
vec_inA = (vector unsigned long long){ vdargs[i], 0ULL };
|
||||
if (isLE)
|
||||
vec_inA = (vector unsigned long long){ 0ULL, vdargs[i] };
|
||||
else
|
||||
vec_inA = (vector unsigned long long){ vdargs[i], 0ULL };
|
||||
|
||||
(*func)();
|
||||
result = r14;
|
||||
@ -1139,6 +1148,8 @@ static void mtvs(const char* name, test_func_t func,
|
||||
|
||||
(*func)();
|
||||
dst = (unsigned long long *) &vec_out;
|
||||
if (isLE)
|
||||
dst++;
|
||||
printf("%s: %016llx => %016llx\n", name, vdargs[i], *dst);
|
||||
}
|
||||
}
|
||||
@ -1154,13 +1165,16 @@ static void mtvs2s(const char* name, test_func_t func,
|
||||
for (i=0; i < NB_VDARGS; i++) {
|
||||
// Only the lower half of the vdarg doubleword arg will be used as input by mtvsrwa
|
||||
unsigned int * src = (unsigned int *)&vdargs[i];
|
||||
src++;
|
||||
if (!isLE)
|
||||
src++;
|
||||
r14 = vdargs[i];
|
||||
vec_out = (vector unsigned long long){ 0ULL, 0ULL };
|
||||
|
||||
(*func)();
|
||||
// Only doubleword 0 is used in output
|
||||
dst = (unsigned long long *) &vec_out;
|
||||
if (isLE)
|
||||
dst++;
|
||||
printf("%s: %08x => %016llx\n", name, *src, *dst);
|
||||
}
|
||||
}
|
||||
@ -1222,16 +1236,27 @@ static void test_av_dint_two_args (const char* name, test_func_t func,
|
||||
unsigned int * dst_int;
|
||||
int i,j;
|
||||
int family = test_flags & PPC_FAMILY;
|
||||
int is_vpkudum;
|
||||
int is_vpkudum, is_vpmsumd;
|
||||
if (strcmp(name, "vpkudum") == 0)
|
||||
is_vpkudum = 1;
|
||||
else
|
||||
is_vpkudum = 0;
|
||||
|
||||
if (strcmp(name, "vpmsumd") == 0)
|
||||
is_vpmsumd = 1;
|
||||
else
|
||||
is_vpmsumd = 0;
|
||||
|
||||
for (i = 0; i < NB_VDARGS; i+=2) {
|
||||
vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
|
||||
if (isLE && family == PPC_ALTIVECQ)
|
||||
vec_inA = (vector unsigned long long){ vdargs[i+1], vdargs[i] };
|
||||
else
|
||||
vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
|
||||
for (j = 0; j < NB_VDARGS; j+=2) {
|
||||
vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
|
||||
if (isLE && family == PPC_ALTIVECQ)
|
||||
vec_inB = (vector unsigned long long){ vdargs[j+1], vdargs[j] };
|
||||
else
|
||||
vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
|
||||
vec_out = (vector unsigned long long){ 0,0 };
|
||||
|
||||
(*func)();
|
||||
@ -1244,12 +1269,32 @@ static void test_av_dint_two_args (const char* name, test_func_t func,
|
||||
printf("Inputs: %08llx %08llx %08llx %08llx\n", vdargs[i] & 0x00000000ffffffffULL,
|
||||
vdargs[i+1] & 0x00000000ffffffffULL, vdargs[j] & 0x00000000ffffffffULL,
|
||||
vdargs[j+1] & 0x00000000ffffffffULL);
|
||||
printf(" Output: %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
|
||||
dst_int[2], dst_int[3]);
|
||||
if (isLE)
|
||||
printf(" Output: %08x %08x %08x %08x\n", dst_int[2], dst_int[3],
|
||||
dst_int[0], dst_int[1]);
|
||||
else
|
||||
printf(" Output: %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
|
||||
dst_int[2], dst_int[3]);
|
||||
} else if (is_vpmsumd) {
|
||||
printf("%016llx @@ %016llx ", vdargs[i], vdargs[j]);
|
||||
if (isLE)
|
||||
printf(" ==> %016llx\n", dst[1]);
|
||||
else
|
||||
printf(" ==> %016llx\n", dst[0]);
|
||||
printf("\t%016llx @@ %016llx ", vdargs[i+1], vdargs[j+1]);
|
||||
if (isLE)
|
||||
printf(" ==> %016llx\n", dst[0]);
|
||||
else
|
||||
printf(" ==> %016llx\n", dst[1]);
|
||||
} else if (family == PPC_ALTIVECQ) {
|
||||
printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n",
|
||||
vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1],
|
||||
dst[0], dst[1]);
|
||||
if (isLE)
|
||||
printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n",
|
||||
vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1],
|
||||
dst[1], dst[0]);
|
||||
else
|
||||
printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n",
|
||||
vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1],
|
||||
dst[0], dst[1]);
|
||||
} else {
|
||||
printf("%016llx @@ %016llx ", vdargs[i], vdargs[j]);
|
||||
printf(" ==> %016llx\n", dst[0]);
|
||||
@ -1311,9 +1356,15 @@ static void test_av_bcd (const char* name, test_func_t func,
|
||||
int i, j;
|
||||
|
||||
for (i = 0; i < NUM_VBCD_VALS; i+=2) {
|
||||
vec_inA = (vector unsigned long long){ vbcd_args[i], vbcd_args[i +1 ] };
|
||||
if (isLE)
|
||||
vec_inA = (vector unsigned long long){ vbcd_args[i+1], vbcd_args[i] };
|
||||
else
|
||||
vec_inA = (vector unsigned long long){ vbcd_args[i], vbcd_args[i+1] };
|
||||
for (j = 0; j < NUM_VBCD_VALS; j+=2) {
|
||||
vec_inB = (vector unsigned long long){ vbcd_args[j], vbcd_args[j +1 ] };
|
||||
if (isLE)
|
||||
vec_inB = (vector unsigned long long){ vbcd_args[j+1], vbcd_args[j] };
|
||||
else
|
||||
vec_inB = (vector unsigned long long){ vbcd_args[j], vbcd_args[j+1] };
|
||||
vec_out = (vector unsigned long long){ 0, 0 };
|
||||
|
||||
for (PS_bit = 0; PS_bit < 2; PS_bit++) {
|
||||
@ -1323,7 +1374,10 @@ static void test_av_bcd (const char* name, test_func_t func,
|
||||
printf("%016llx || %016llx @@ %016llx || %016llx",
|
||||
vbcd_args[i], vbcd_args[i + 1],
|
||||
vbcd_args[j], vbcd_args[j + 1]);
|
||||
printf(" ==> %016llx || %016llx\n", dst[0], dst[1]);
|
||||
if (isLE)
|
||||
printf(" ==> %016llx || %016llx\n", dst[1], dst[0]);
|
||||
else
|
||||
printf(" ==> %016llx || %016llx\n", dst[0], dst[1]);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1349,8 +1403,12 @@ static void test_av_dint_to_int_two_args (const char* name, test_func_t func,
|
||||
printf("%016llx, %016llx @@ %016llx, %016llx ",
|
||||
vdargs_x[i], vdargs_x[i+1],
|
||||
vdargs_x[j], vdargs_x[j+1]);
|
||||
printf(" ==> %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
|
||||
dst_int[2], dst_int[3]);
|
||||
if (isLE)
|
||||
printf(" ==> %08x %08x %08x %08x\n", dst_int[2], dst_int[3],
|
||||
dst_int[0], dst_int[1]);
|
||||
else
|
||||
printf(" ==> %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
|
||||
dst_int[2], dst_int[3]);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1365,16 +1423,26 @@ static void test_av_wint_two_args_dres (const char* name, test_func_t func,
|
||||
int i,j;
|
||||
|
||||
for (i = 0; i < NB_VWARGS; i+=4) {
|
||||
vec_inA_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
|
||||
if (isLE)
|
||||
vec_inA_wd = (vector unsigned int){ vwargs[i+3], vwargs[i+2], vwargs[i+1], vwargs[i] };
|
||||
else
|
||||
vec_inA_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
|
||||
for (j = 0; j < NB_VWARGS; j+=4) {
|
||||
vec_inB_wd = (vector unsigned int){ vwargs[j], vwargs[j+1], vwargs[j+2], vwargs[j+3] };
|
||||
if (isLE)
|
||||
vec_inB_wd = (vector unsigned int){ vwargs[j+3], vwargs[j+2], vwargs[j+1], vwargs[j] };
|
||||
else
|
||||
vec_inB_wd = (vector unsigned int){ vwargs[j], vwargs[j+1], vwargs[j+2], vwargs[j+3] };
|
||||
vec_out = (vector unsigned long long){ 0, 0 };
|
||||
|
||||
(*func)();
|
||||
dst = (unsigned long long *)&vec_out;
|
||||
printf("%s: ", name);
|
||||
printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
|
||||
vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
|
||||
if (isLE)
|
||||
printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
|
||||
vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[1], dst[0]);
|
||||
else
|
||||
printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
|
||||
vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -1387,14 +1455,21 @@ static void test_av_wint_one_arg_dres (const char* name, test_func_t func,
|
||||
unsigned long long * dst;
|
||||
int i;
|
||||
for (i = 0; i < NB_VWARGS; i+=4) {
|
||||
vec_inB_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
|
||||
if (isLE)
|
||||
vec_inB_wd = (vector unsigned int){ vwargs[i+3], vwargs[i+2], vwargs[i+1], vwargs[i] };
|
||||
else
|
||||
vec_inB_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
|
||||
vec_out = (vector unsigned long long){ 0, 0 };
|
||||
|
||||
(*func)();
|
||||
dst = (unsigned long long *)&vec_out;
|
||||
printf("%s: ", name);
|
||||
printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
|
||||
vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
|
||||
if (isLE)
|
||||
printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
|
||||
vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[1], dst[0]);
|
||||
else
|
||||
printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
|
||||
vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
|
||||
}
|
||||
}
|
||||
|
||||
@ -1556,28 +1631,52 @@ static void test_av_dint_three_args (const char* name, test_func_t func,
|
||||
0xf000000000000000ULL, 0xf000000000000001ULL
|
||||
};
|
||||
for (i = 0; i < NB_VDARGS; i+=2) {
|
||||
vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
|
||||
if (isLE)
|
||||
vec_inA = (vector unsigned long long){ vdargs[i+1], vdargs[i] };
|
||||
else
|
||||
vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
|
||||
for (j = 0; j < NB_VDARGS; j+=2) {
|
||||
vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
|
||||
if (isLE)
|
||||
vec_inB = (vector unsigned long long){ vdargs[j+1], vdargs[j] };
|
||||
else
|
||||
vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
|
||||
for (k = 0; k < 4; k+=2) {
|
||||
if (family == PPC_ALTIVECQ)
|
||||
vec_inC = (vector unsigned long long){ cin_vals[k], cin_vals[k+1] };
|
||||
else
|
||||
vec_inC = (vector unsigned long long){ vdargs[k], vdargs[k+1] };
|
||||
if (family == PPC_ALTIVECQ) {
|
||||
if (isLE)
|
||||
vec_inC = (vector unsigned long long){ cin_vals[k+1], cin_vals[k] };
|
||||
else
|
||||
vec_inC = (vector unsigned long long){ cin_vals[k], cin_vals[k+1] };
|
||||
} else {
|
||||
if (isLE)
|
||||
vec_inC = (vector unsigned long long){ vdargs[k+1], vdargs[k] };
|
||||
else
|
||||
vec_inC = (vector unsigned long long){ vdargs[k], vdargs[k+1] };
|
||||
}
|
||||
vec_out = (vector unsigned long long){ 0,0 };
|
||||
|
||||
(*func)();
|
||||
dst = (unsigned long long*)&vec_out;
|
||||
printf("%s: ", name);
|
||||
if (family == PPC_ALTIVECQ) {
|
||||
printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n",
|
||||
vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1],
|
||||
dst[0], dst[1]);
|
||||
if (isLE)
|
||||
printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n",
|
||||
vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1],
|
||||
dst[1], dst[0]);
|
||||
else
|
||||
printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n",
|
||||
vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1],
|
||||
dst[0], dst[1]);
|
||||
} else {
|
||||
printf("%016llx @@ %016llx @@ %016llx ", vdargs[i], vdargs[j], vdargs[k]);
|
||||
printf(" ==> %016llx\n", dst[0]);
|
||||
if (isLE)
|
||||
printf(" ==> %016llx\n", dst[1]);
|
||||
else
|
||||
printf(" ==> %016llx\n", dst[0]);
|
||||
printf("\t%016llx @@ %016llx @@ %016llx ", vdargs[i+1], vdargs[j+1], vdargs[k+1]);
|
||||
printf(" ==> %016llx\n", dst[1]);
|
||||
if (isLE)
|
||||
printf(" ==> %016llx\n", dst[0]);
|
||||
else
|
||||
printf(" ==> %016llx\n", dst[1]);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -40,6 +40,12 @@ typedef uint32_t HWord_t;
|
||||
typedef uint64_t HWord_t;
|
||||
#endif /* __powerpc64__ */
|
||||
|
||||
#ifdef VGP_ppc64le_linux
|
||||
#define isLE 1
|
||||
#else
|
||||
#define isLE 0
|
||||
#endif
|
||||
|
||||
register HWord_t r14 __asm__ ("r14");
|
||||
register HWord_t r15 __asm__ ("r15");
|
||||
register HWord_t r16 __asm__ ("r16");
|
||||
@ -341,6 +347,16 @@ static unsigned int viargs[] __attribute__ ((aligned (16))) = { 0x80000001,
|
||||
#define NUM_VIARGS_INTS (sizeof viargs/sizeof viargs[0])
|
||||
#define NUM_VIARGS_VECS (NUM_VIARGS_INTS/4)
|
||||
|
||||
|
||||
static unsigned long long vdargs[] __attribute__ ((aligned (16))) = {
|
||||
0x0102030405060708ULL,
|
||||
0x090A0B0C0E0D0E0FULL,
|
||||
0xF1F2F3F4F5F6F7F8ULL,
|
||||
0xF9FAFBFCFEFDFEFFULL
|
||||
};
|
||||
#define NUM_VDARGS_INTS (sizeof vdargs/sizeof vdargs[0])
|
||||
#define NUM_VDARGS_VECS (NUM_VDARGS_INTS/2)
|
||||
|
||||
typedef void (*test_func_t)(void);
|
||||
|
||||
struct test_table
|
||||
@ -727,7 +743,7 @@ static vx_fp_test_basic_t vx_fp_tests[] = {
|
||||
|
||||
static vx_fp_test2_t
|
||||
vsx_one_fp_arg_tests[] = {
|
||||
{ &test_xscvdpspn, "xscvdpspn", NULL, 20, SINGLE_TEST_SINGLE_RES, VX_SCALAR_SP_TO_VECTOR_SP, "conv"},
|
||||
{ &test_xscvdpspn, "xscvdpspn", NULL, 20, DOUBLE_TEST_SINGLE_RES, VX_SCALAR_SP_TO_VECTOR_SP, "conv"},
|
||||
{ &test_xscvspdpn, "xscvspdpn", NULL, 20, SINGLE_TEST, VX_DEFAULT, "conv"},
|
||||
{ &test_xsresp, "xsresp", NULL, 20, DOUBLE_TEST, VX_ESTIMATE, "1/x"},
|
||||
{ &test_xsrsp, "xsrsp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "round"},
|
||||
@ -749,7 +765,7 @@ ldst_tests[] = {
|
||||
{ &test_stxsspx, "stxsspx", DOUBLE_TEST_SINGLE_RES, vstg, 0, VSX_STORE },
|
||||
{ &test_stxsiwx, "stxsiwx", SINGLE_TEST_SINGLE_RES, vstg, 4, VSX_STORE },
|
||||
{ &test_lxsiwax, "lxsiwax", SINGLE_TEST, viargs, 0, VSX_LOAD },
|
||||
{ &test_lxsiwzx, "lxsiwzx", SINGLE_TEST, viargs, 1, VSX_LOAD },
|
||||
{ &test_lxsiwzx, "lxsiwzx", SINGLE_TEST, viargs, 4, VSX_LOAD },
|
||||
{ &test_lxsspx, "lxsspx", SINGLE_TEST, NULL, 0, VSX_LOAD },
|
||||
{ NULL, NULL, 0, NULL, 0, 0 } };
|
||||
|
||||
@ -881,8 +897,19 @@ static void test_vx_fp_ops(void)
|
||||
test_func_t func;
|
||||
int k;
|
||||
char * test_name = (char *)malloc(20);
|
||||
k = 0;
|
||||
void * vecA_void_ptr, * vecB_void_ptr, * vecOut_void_ptr;
|
||||
|
||||
if (isLE) {
|
||||
vecA_void_ptr = (void *)&vec_inA + 8;
|
||||
vecB_void_ptr = (void *)&vec_inB + 8;
|
||||
vecOut_void_ptr = (void *)&vec_out + 8;
|
||||
} else {
|
||||
vecA_void_ptr = (void *)&vec_inA;
|
||||
vecB_void_ptr = (void *)&vec_inB;
|
||||
vecOut_void_ptr = (void *)&vec_out;
|
||||
}
|
||||
|
||||
k = 0;
|
||||
build_special_fargs_table();
|
||||
while ((func = vx_fp_tests[k].test_func)) {
|
||||
int i, repeat = 0;
|
||||
@ -932,8 +959,8 @@ again:
|
||||
pv = (unsigned int *)&vec_out;
|
||||
|
||||
// Only need to copy one doubleword into each vector's element 0
|
||||
memcpy(&vec_inA, inA, 8);
|
||||
memcpy(&vec_inB, inB, 8);
|
||||
memcpy(vecA_void_ptr, inA, 8);
|
||||
memcpy(vecB_void_ptr, inB, 8);
|
||||
|
||||
// clear vec_out
|
||||
for (idx = 0; idx < 4; idx++, pv++)
|
||||
@ -963,18 +990,20 @@ again:
|
||||
* src2 <= VSX[XT]
|
||||
* src3 <= VSX[XB]
|
||||
*/
|
||||
memcpy(&vec_out, inB, 8); // src2
|
||||
memcpy(&vec_inB, &spec_fargs[extra_arg_idx], 8); //src3
|
||||
memcpy(vecOut_void_ptr, inB, 8); // src2
|
||||
memcpy(vecB_void_ptr, &spec_fargs[extra_arg_idx], 8); //src3
|
||||
frbp = (unsigned long long *)&spec_fargs[extra_arg_idx];
|
||||
} else {
|
||||
// Don't need to init src2, as it's done before the switch()
|
||||
memcpy(&vec_out, &spec_fargs[extra_arg_idx], 8); //src3
|
||||
memcpy(vecOut_void_ptr, &spec_fargs[extra_arg_idx], 8); //src3
|
||||
}
|
||||
memcpy(&vsr_XT, &vec_out, 8);
|
||||
memcpy(&vsr_XT, vecOut_void_ptr, 8);
|
||||
}
|
||||
|
||||
(*func)();
|
||||
dst = (unsigned long long *) &vec_out;
|
||||
if (isLE)
|
||||
dst++;
|
||||
|
||||
if (test_type == VX_FP_OTHER)
|
||||
printf("#%d: %s %016llx %016llx = %016llx\n", i, test_name,
|
||||
@ -1033,6 +1062,8 @@ static void test_vsx_one_fp_arg(void)
|
||||
{
|
||||
test_func_t func;
|
||||
int k;
|
||||
void * vecB_void_ptr;
|
||||
|
||||
k = 0;
|
||||
build_special_fargs_table();
|
||||
|
||||
@ -1047,26 +1078,13 @@ static void test_vsx_one_fp_arg(void)
|
||||
/* size of result */
|
||||
Bool dp_res = IS_DP_RESULT(test_group.precision);
|
||||
Bool is_sqrt = (strstr(test_group.name, "sqrt")) ? True : False;
|
||||
Bool is_scalar = (strstr(test_group.name, "xs")) ? True : False;
|
||||
Bool sparse_sp = False;
|
||||
int stride = dp ? 2 : 4;
|
||||
int loops = is_scalar ? 1 : stride;
|
||||
stride = is_scalar ? 1: stride;
|
||||
|
||||
/* For conversions of single to double, the 128-bit input register is sparsely populated:
|
||||
* |___ SP___|_Unused_|___SP___|__Unused__| // for vector op
|
||||
* or
|
||||
* |___ SP___|_Unused_|_Unused_|__Unused__| // for scalar op
|
||||
*
|
||||
* For the vector op case, we need to adjust stride from '4' to '2', since
|
||||
* we'll only be loading two values per loop into the input register.
|
||||
*/
|
||||
if (!dp && !is_scalar && test_group.test_type == VX_CONV_TO_DOUBLE) {
|
||||
sparse_sp = True;
|
||||
stride = 2;
|
||||
vecB_void_ptr = (void *)&vec_inB;
|
||||
if (isLE) {
|
||||
vecB_void_ptr += dp? 8 : 12;
|
||||
}
|
||||
|
||||
for (i = 0; i < test_group.num_tests; i+=stride) {
|
||||
for (i = 0; i < test_group.num_tests; i++) {
|
||||
unsigned int * pv;
|
||||
void * inB;
|
||||
|
||||
@ -1076,44 +1094,12 @@ static void test_vsx_one_fp_arg(void)
|
||||
*pv = 0;
|
||||
|
||||
if (dp) {
|
||||
int j;
|
||||
int vec_out_idx;
|
||||
unsigned long long * frB_dp;
|
||||
for (j = 0; j < loops; j++) {
|
||||
inB = (void *)&spec_fargs[i + j];
|
||||
// copy double precision FP into vector element i
|
||||
memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
|
||||
}
|
||||
// execute test insn
|
||||
(*func)();
|
||||
if (dp_res)
|
||||
dst_dp = (unsigned long long *) &vec_out;
|
||||
if (isLE)
|
||||
vec_out_idx = dp_res ? 1 : 3;
|
||||
else
|
||||
dst_sp = (unsigned int *) &vec_out;
|
||||
|
||||
printf("#%d: %s ", i/stride, test_group.name);
|
||||
for (j = 0; j < loops; j++) {
|
||||
if (j)
|
||||
printf("; ");
|
||||
frB_dp = (unsigned long long *)&spec_fargs[i + j];
|
||||
printf("%s(%016llx)", test_group.op, *frB_dp);
|
||||
if (test_group.test_type == VX_ESTIMATE)
|
||||
{
|
||||
Bool res;
|
||||
res = check_reciprocal_estimate(is_sqrt, i + j, j);
|
||||
printf(" ==> %s)", res ? "PASS" : "FAIL");
|
||||
} else if (dp_res) {
|
||||
printf(" = %016llx", dst_dp[j]);
|
||||
} else {
|
||||
printf(" = %08x", dst_sp[j]);
|
||||
}
|
||||
}
|
||||
printf("\n");
|
||||
} else { // single precision test type
|
||||
int j;
|
||||
// Clear input vector
|
||||
pv = (unsigned int *)&vec_inB;
|
||||
for (idx = 0; idx < 4; idx++, pv++)
|
||||
*pv = 0;
|
||||
vec_out_idx = 0;
|
||||
|
||||
if (test_group.test_type == VX_SCALAR_SP_TO_VECTOR_SP) {
|
||||
/* Take a single-precision value stored in double word element 0
|
||||
@ -1121,25 +1107,48 @@ static void test_vsx_one_fp_arg(void)
|
||||
* precision and store in word element 0 of dst.
|
||||
*/
|
||||
double input = spec_sp_fargs[i];
|
||||
memcpy(((void *)&vec_inB), (void *)&input, 8);
|
||||
memcpy(vecB_void_ptr, (void *)&input, 8);
|
||||
} else {
|
||||
int skip_slot;
|
||||
if (sparse_sp) {
|
||||
skip_slot = 1;
|
||||
loops = 2;
|
||||
} else {
|
||||
skip_slot = 0;
|
||||
}
|
||||
for (j = 0; j < loops; j++) {
|
||||
inB = (void *)&spec_sp_fargs[i + j];
|
||||
// copy single precision FP into vector element i
|
||||
|
||||
if (skip_slot && j > 0)
|
||||
memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4);
|
||||
else
|
||||
memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
|
||||
}
|
||||
inB = (void *)&spec_fargs[i];
|
||||
// copy double precision FP into input vector element 0
|
||||
memcpy(vecB_void_ptr, inB, 8);
|
||||
}
|
||||
|
||||
// execute test insn
|
||||
(*func)();
|
||||
if (dp_res)
|
||||
dst_dp = (unsigned long long *) &vec_out;
|
||||
else
|
||||
dst_sp = (unsigned int *) &vec_out;
|
||||
|
||||
printf("#%d: %s ", i, test_group.name);
|
||||
frB_dp = (unsigned long long *)&spec_fargs[i];
|
||||
printf("%s(%016llx)", test_group.op, *frB_dp);
|
||||
if (test_group.test_type == VX_ESTIMATE)
|
||||
{
|
||||
Bool res;
|
||||
res = check_reciprocal_estimate(is_sqrt, i, vec_out_idx);
|
||||
printf(" ==> %s)", res ? "PASS" : "FAIL");
|
||||
} else if (dp_res) {
|
||||
printf(" = %016llx", dst_dp[vec_out_idx]);
|
||||
} else {
|
||||
printf(" = %08x", dst_sp[vec_out_idx]);
|
||||
}
|
||||
|
||||
printf("\n");
|
||||
} else { // single precision test type
|
||||
int vec_out_idx;
|
||||
if (isLE)
|
||||
vec_out_idx = dp_res ? 1 : 3;
|
||||
else
|
||||
vec_out_idx = 0;
|
||||
// Clear input vector
|
||||
pv = (unsigned int *)&vec_inB;
|
||||
for (idx = 0; idx < 4; idx++, pv++)
|
||||
*pv = 0;
|
||||
inB = (void *)&spec_sp_fargs[i];
|
||||
// copy single precision FP into input vector element i
|
||||
memcpy(vecB_void_ptr, inB, 4);
|
||||
// execute test insn
|
||||
(*func)();
|
||||
if (dp_res)
|
||||
@ -1147,16 +1156,13 @@ static void test_vsx_one_fp_arg(void)
|
||||
else
|
||||
dst_sp = (unsigned int *) &vec_out;
|
||||
// print result
|
||||
printf("#%d: %s ", i/stride, test_group.name);
|
||||
for (j = 0; j < loops; j++) {
|
||||
if (j)
|
||||
printf("; ");
|
||||
printf("%s(%08x)", test_group.op, *((unsigned int *)&spec_sp_fargs[i + j]));
|
||||
printf("#%d: %s ", i, test_group.name);
|
||||
printf("%s(%08x)", test_group.op, *((unsigned int *)&spec_sp_fargs[i]));
|
||||
if (dp_res)
|
||||
printf(" = %016llx", dst_dp[j]);
|
||||
printf(" = %016llx", dst_dp[vec_out_idx]);
|
||||
else
|
||||
printf(" = %08x", dst_sp[j]);
|
||||
}
|
||||
printf(" = %08x", dst_sp[vec_out_idx]);
|
||||
|
||||
printf("\n");
|
||||
}
|
||||
}
|
||||
@ -1170,6 +1176,15 @@ static void test_vsx_two_fp_arg(void)
|
||||
{
|
||||
test_func_t func;
|
||||
int k = 0;
|
||||
void * vecA_void_ptr, * vecB_void_ptr;
|
||||
|
||||
if (isLE) {
|
||||
vecA_void_ptr = (void *)&vec_inA + 8;
|
||||
vecB_void_ptr = (void *)&vec_inB + 8;
|
||||
} else {
|
||||
vecA_void_ptr = (void *)&vec_inA;
|
||||
vecB_void_ptr = (void *)&vec_inB;
|
||||
}
|
||||
|
||||
build_special_fargs_table();
|
||||
while ((func = vx_simple_scalar_fp_tests[k].test_func)) {
|
||||
@ -1191,10 +1206,12 @@ static void test_vsx_two_fp_arg(void)
|
||||
frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
|
||||
frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
|
||||
// Only need to copy one doubleword into each vector's element 0
|
||||
memcpy(&vec_inA, inA, 8);
|
||||
memcpy(&vec_inB, inB, 8);
|
||||
memcpy(vecA_void_ptr, inA, 8);
|
||||
memcpy(vecB_void_ptr, inB, 8);
|
||||
(*func)();
|
||||
dst = (unsigned long long *) &vec_out;
|
||||
if (isLE)
|
||||
dst++;
|
||||
printf("#%d: %s %016llx,%016llx => %016llx\n", i, test_group.name,
|
||||
*frap, *frbp, *dst);
|
||||
}
|
||||
@ -1214,84 +1231,91 @@ static void _do_store_test (ldst_test_t storeTest)
|
||||
unsigned int *dst32;
|
||||
unsigned int i, idx;
|
||||
unsigned int * pv = (unsigned int *) storeTest.base_addr;
|
||||
void * vecA_void_ptr;
|
||||
|
||||
if (isLE) {
|
||||
if (storeTest.precision == SINGLE_TEST_SINGLE_RES)
|
||||
vecA_void_ptr = (void *)&vec_inA + 8;
|
||||
} else {
|
||||
if (storeTest.precision == SINGLE_TEST_SINGLE_RES)
|
||||
vecA_void_ptr = (void *)&vec_inA + 4;
|
||||
else
|
||||
vecA_void_ptr = (void *)&vec_inA;
|
||||
}
|
||||
|
||||
func = storeTest.test_func;
|
||||
r14 = (HWord_t) storeTest.base_addr;
|
||||
r15 = (HWord_t) storeTest.offset;
|
||||
|
||||
if (storeTest.precision == DOUBLE_TEST_SINGLE_RES) {
|
||||
/* source is single precision stored in double precision format */
|
||||
/* test some of the pre-defined single precision values */
|
||||
for (i = 0; i < nb_special_fargs; i+=3) {
|
||||
// clear out storage destination
|
||||
for (idx = 0; idx < 4; idx++)
|
||||
*(pv + idx) = 0;
|
||||
/* test some of the pre-defined single precision values */
|
||||
for (i = 0; i < nb_special_fargs; i+=3) {
|
||||
// clear out storage destination
|
||||
for (idx = 0; idx < 4; idx++)
|
||||
*(pv + idx) = 0;
|
||||
|
||||
printf( "%s:", storeTest.name );
|
||||
printf( "%s:", storeTest.name );
|
||||
if (storeTest.precision == SINGLE_TEST_SINGLE_RES)
|
||||
{
|
||||
unsigned int * arg_ptr = (unsigned int *)&spec_sp_fargs[i];
|
||||
memcpy(vecA_void_ptr, arg_ptr, sizeof(unsigned int));
|
||||
printf(" %08x ==> ", *arg_ptr);
|
||||
} else {
|
||||
unsigned long long * dp;
|
||||
double input = spec_sp_fargs[i];
|
||||
dp = (unsigned long long *)&input;
|
||||
memcpy(&vec_inA, dp, sizeof(unsigned long long));
|
||||
memcpy(vecA_void_ptr, dp, sizeof(unsigned long long));
|
||||
printf(" %016llx ==> ", *dp);
|
||||
|
||||
// execute test insn
|
||||
(*func)();
|
||||
dst32 = (unsigned int*)(storeTest.base_addr + storeTest.offset);
|
||||
printf( "%08x\n", *dst32);
|
||||
}
|
||||
} else {
|
||||
// source is an integer word
|
||||
for (i = 0; i < NUM_VIARGS_INTS; i++) {
|
||||
// clear out storage destination
|
||||
for (idx = 0; idx < 4; idx++)
|
||||
*(pv + idx) = 0;
|
||||
printf( "%s:", storeTest.name );
|
||||
unsigned int * pi = (unsigned int *)&vec_inA;
|
||||
memcpy(pi + 1, &viargs[i], sizeof(unsigned int));
|
||||
printf(" %08x ==> ", *(pi + 1));
|
||||
|
||||
// execute test insn
|
||||
(*func)();
|
||||
dst32 = (unsigned int*)(storeTest.base_addr + storeTest.offset);
|
||||
printf( "%08x\n", *dst32);
|
||||
}
|
||||
// execute test insn
|
||||
(*func)();
|
||||
dst32 = (unsigned int*)(storeTest.base_addr);
|
||||
dst32 += (storeTest.offset/sizeof(int));
|
||||
printf( "%08x\n", *dst32);
|
||||
}
|
||||
|
||||
printf("\n");
|
||||
}
|
||||
|
||||
static void _do_load_test(ldst_test_t storeTest)
|
||||
static void _do_load_test(ldst_test_t loadTest)
|
||||
{
|
||||
test_func_t func;
|
||||
unsigned int i;
|
||||
unsigned long long * dst_dp;
|
||||
|
||||
func = storeTest.test_func;
|
||||
r15 = (HWord_t) storeTest.offset;
|
||||
func = loadTest.test_func;
|
||||
r15 = (HWord_t) loadTest.offset;
|
||||
|
||||
if (storeTest.base_addr == NULL) {
|
||||
if (loadTest.base_addr == NULL) {
|
||||
/* Test lxsspx: source is single precision value, so let's */
|
||||
/* test some of the pre-defined single precision values. */
|
||||
for (i = 0; i + storeTest.offset < nb_special_fargs; i+=3) {
|
||||
unsigned int * sp = (unsigned int *)&spec_sp_fargs[i + storeTest.offset];
|
||||
printf( "%s:", storeTest.name );
|
||||
int num_loops = (loadTest.offset == 0) ? nb_special_fargs : (nb_special_fargs - (loadTest.offset/sizeof(int)));
|
||||
for (i = 0; i < num_loops; i+=3) {
|
||||
unsigned int * sp = (unsigned int *)&spec_sp_fargs[i + (loadTest.offset/sizeof(int))];
|
||||
printf( "%s:", loadTest.name );
|
||||
printf(" %08x ==> ", *sp);
|
||||
r14 = (HWord_t)&spec_sp_fargs[i];
|
||||
|
||||
// execute test insn
|
||||
(*func)();
|
||||
dst_dp = (unsigned long long *) &vec_out;
|
||||
if (isLE)
|
||||
dst_dp++;
|
||||
printf("%016llx\n", *dst_dp);
|
||||
}
|
||||
} else {
|
||||
// source is an integer word
|
||||
for (i = 0; i < NUM_VIARGS_INTS; i++) {
|
||||
printf( "%s:", storeTest.name );
|
||||
r14 = (HWord_t)&viargs[i + storeTest.offset];
|
||||
printf(" %08x ==> ", viargs[i + storeTest.offset]);
|
||||
int num_loops = (loadTest.offset == 0) ? NUM_VIARGS_INTS : (NUM_VIARGS_INTS - (loadTest.offset/sizeof(int)));
|
||||
for (i = 0; i < num_loops; i++) {
|
||||
printf( "%s:", loadTest.name );
|
||||
r14 = (HWord_t)&viargs[i];
|
||||
printf(" %08x ==> ", viargs[i + (loadTest.offset/sizeof(int))]);
|
||||
|
||||
// execute test insn
|
||||
(*func)();
|
||||
dst_dp = (unsigned long long *) &vec_out;
|
||||
if (isLE)
|
||||
dst_dp++;
|
||||
printf("%016llx\n", *dst_dp);
|
||||
}
|
||||
}
|
||||
@ -1318,24 +1342,32 @@ static void test_xs_conv_ops(void)
|
||||
|
||||
test_func_t func;
|
||||
int k = 0;
|
||||
void * vecB_void_ptr;
|
||||
|
||||
if (isLE)
|
||||
vecB_void_ptr = (void *)&vec_inB + 8;
|
||||
else
|
||||
vecB_void_ptr = (void *)&vec_inB;
|
||||
|
||||
build_special_fargs_table();
|
||||
while ((func = xs_conv_tests[k].test_func)) {
|
||||
int i;
|
||||
unsigned long long * dst;
|
||||
xs_conv_test_t test_group = xs_conv_tests[k];
|
||||
for (i = 0; i < NUM_VIARGS_INTS; i++) {
|
||||
unsigned int * inB, * pv;
|
||||
for (i = 0; i < NUM_VDARGS_INTS; i++) {
|
||||
unsigned long long * inB, * pv;
|
||||
int idx;
|
||||
inB = (unsigned int *)&viargs[i];
|
||||
memcpy(&vec_inB, inB, 4);
|
||||
pv = (unsigned int *)&vec_out;
|
||||
inB = (unsigned long long *)&vdargs[i];
|
||||
memcpy(vecB_void_ptr, inB, 8);
|
||||
pv = (unsigned long long *)&vec_out;
|
||||
// clear vec_out
|
||||
for (idx = 0; idx < 4; idx++, pv++)
|
||||
*pv = 0;
|
||||
for (idx = 0; idx < 2; idx++, pv++)
|
||||
*pv = 0ULL;
|
||||
(*func)();
|
||||
dst = (unsigned long long *) &vec_out;
|
||||
printf("#%d: %s %08x => %016llx\n", i, test_group.name, viargs[i], *dst);
|
||||
if (isLE)
|
||||
dst++;
|
||||
printf("#%d: %s %016llx => %016llx\n", i, test_group.name, vdargs[i], *dst);
|
||||
}
|
||||
k++;
|
||||
printf("\n");
|
||||
|
||||
@ -651,26 +651,26 @@ Test VSX floating point instructions
|
||||
|
||||
|
||||
Test VSX vector and scalar single argument instructions
|
||||
#0: xscvdpspn conv(3ec00000) = 3ec00000
|
||||
#1: xscvdpspn conv(42780000) = 42780000
|
||||
#2: xscvdpspn conv(00000000) = 00000000
|
||||
#3: xscvdpspn conv(7f800000) = 7f800000
|
||||
#4: xscvdpspn conv(00000000) = 00000000
|
||||
#5: xscvdpspn conv(00000000) = 00000000
|
||||
#6: xscvdpspn conv(80000000) = 80000000
|
||||
#7: xscvdpspn conv(7f800000) = 7f800000
|
||||
#8: xscvdpspn conv(ff800000) = ff800000
|
||||
#9: xscvdpspn conv(7fbfffff) = 7fbfffff
|
||||
#10: xscvdpspn conv(ffbfffff) = ffbfffff
|
||||
#11: xscvdpspn conv(7fc00000) = 7fc00000
|
||||
#12: xscvdpspn conv(ffc00000) = ffc00000
|
||||
#13: xscvdpspn conv(80000000) = 80000000
|
||||
#14: xscvdpspn conv(c683287b) = c683287b
|
||||
#15: xscvdpspn conv(49192c2d) = 49192c2d
|
||||
#16: xscvdpspn conv(49c1288d) = 49c1288d
|
||||
#17: xscvdpspn conv(418977ad) = 418977ad
|
||||
#18: xscvdpspn conv(428a5faf) = 428a5faf
|
||||
#19: xscvdpspn conv(44bb5fcc) = 44bb5fcc
|
||||
#0: xscvdpspn conv(3fd8000000000000) = 3ec00000
|
||||
#1: xscvdpspn conv(404f000000000000) = 42780000
|
||||
#2: xscvdpspn conv(0018000000b77501) = 00000000
|
||||
#3: xscvdpspn conv(7fe800000000051b) = 7f800000
|
||||
#4: xscvdpspn conv(0123214569900000) = 00000000
|
||||
#5: xscvdpspn conv(0000000000000000) = 00000000
|
||||
#6: xscvdpspn conv(8000000000000000) = 80000000
|
||||
#7: xscvdpspn conv(7ff0000000000000) = 7f800000
|
||||
#8: xscvdpspn conv(fff0000000000000) = ff800000
|
||||
#9: xscvdpspn conv(7ff7ffffffffffff) = 7fbfffff
|
||||
#10: xscvdpspn conv(fff7ffffffffffff) = ffbfffff
|
||||
#11: xscvdpspn conv(7ff8000000000000) = 7fc00000
|
||||
#12: xscvdpspn conv(fff8000000000000) = ffc00000
|
||||
#13: xscvdpspn conv(8008340000078000) = 80000000
|
||||
#14: xscvdpspn conv(c0d0650f5a07b353) = c683287b
|
||||
#15: xscvdpspn conv(41232585a9900000) = 49192c2d
|
||||
#16: xscvdpspn conv(41382511a2000000) = 49c1288d
|
||||
#17: xscvdpspn conv(40312ef5a9300000) = 418977ad
|
||||
#18: xscvdpspn conv(40514bf5d2300000) = 428a5faf
|
||||
#19: xscvdpspn conv(40976bf982440000) = 44bb5fcc
|
||||
|
||||
#0: xscvspdpn conv(3ec00000) = 3fd8000000000000
|
||||
#1: xscvspdpn conv(42780000) = 404f000000000000
|
||||
@ -783,23 +783,15 @@ Test VSX logic instructions
|
||||
#2: xxlnand (80000001 89abcdef 00112233 74556677, 80000001 89abcdef 00112233 74556677) ==> 7ffffffe 76543210 ffeeddcc 8baa9988
|
||||
|
||||
Test VSX scalar integer conversion instructions
|
||||
#0: xscvsxdsp 80000001 => c3e0000000000000
|
||||
#1: xscvsxdsp 89abcdef => c3dd950c80000000
|
||||
#2: xscvsxdsp 00112233 => 4331223380000000
|
||||
#3: xscvsxdsp 74556677 => 43dd1559a0000000
|
||||
#4: xscvsxdsp 00001abb => 42babb89a0000000
|
||||
#5: xscvsxdsp 00000001 => 41f89abce0000000
|
||||
#6: xscvsxdsp 31929394 => 43c8c949c0000000
|
||||
#7: xscvsxdsp a1a2a3a4 => c3d7975720000000
|
||||
#0: xscvsxdsp 0102030405060708 => 4370203040000000
|
||||
#1: xscvsxdsp 090a0b0c0e0d0e0f => 43a2141620000000
|
||||
#2: xscvsxdsp f1f2f3f4f5f6f7f8 => c3ac1a1820000000
|
||||
#3: xscvsxdsp f9fafbfcfefdfeff => c398141000000000
|
||||
|
||||
#0: xscvuxdsp 80000001 => 43e0000000000000
|
||||
#1: xscvuxdsp 89abcdef => 43e13579c0000000
|
||||
#2: xscvuxdsp 00112233 => 4331223380000000
|
||||
#3: xscvuxdsp 74556677 => 43dd1559a0000000
|
||||
#4: xscvuxdsp 00001abb => 42babb89a0000000
|
||||
#5: xscvuxdsp 00000001 => 41f89abce0000000
|
||||
#6: xscvuxdsp 31929394 => 43c8c949c0000000
|
||||
#7: xscvuxdsp a1a2a3a4 => 43e4345480000000
|
||||
#0: xscvuxdsp 0102030405060708 => 4370203040000000
|
||||
#1: xscvuxdsp 090a0b0c0e0d0e0f => 43a2141620000000
|
||||
#2: xscvuxdsp f1f2f3f4f5f6f7f8 => 43ee3e5e80000000
|
||||
#3: xscvuxdsp f9fafbfcfefdfeff => 43ef3f5f80000000
|
||||
|
||||
|
||||
Test VSX load/store dp to sp instructions
|
||||
@ -812,14 +804,13 @@ stxsspx: 41232585a0000000 ==> 49192c2d
|
||||
stxsspx: 40514bf5e0000000 ==> 428a5faf
|
||||
|
||||
|
||||
stxsiwx: 80000001 ==> 80000001
|
||||
stxsiwx: 89abcdef ==> 89abcdef
|
||||
stxsiwx: 00112233 ==> 00112233
|
||||
stxsiwx: 74556677 ==> 74556677
|
||||
stxsiwx: 00001abb ==> 00001abb
|
||||
stxsiwx: 00000001 ==> 00000001
|
||||
stxsiwx: 31929394 ==> 31929394
|
||||
stxsiwx: a1a2a3a4 ==> a1a2a3a4
|
||||
stxsiwx: 3ec00000 ==> 3ec00000
|
||||
stxsiwx: 7f800000 ==> 7f800000
|
||||
stxsiwx: 80000000 ==> 80000000
|
||||
stxsiwx: 7fbfffff ==> 7fbfffff
|
||||
stxsiwx: ffc00000 ==> ffc00000
|
||||
stxsiwx: 49192c2d ==> 49192c2d
|
||||
stxsiwx: 428a5faf ==> 428a5faf
|
||||
|
||||
|
||||
lxsiwax: 80000001 ==> ffffffff80000001
|
||||
@ -832,14 +823,13 @@ lxsiwax: 31929394 ==> 0000000031929394
|
||||
lxsiwax: a1a2a3a4 ==> ffffffffa1a2a3a4
|
||||
|
||||
|
||||
lxsiwzx: 89abcdef ==> 00000000abcdef00
|
||||
lxsiwzx: 00112233 ==> 0000000011223374
|
||||
lxsiwzx: 74556677 ==> 0000000055667700
|
||||
lxsiwzx: 00001abb ==> 00000000001abb00
|
||||
lxsiwzx: 00000001 ==> 0000000000000131
|
||||
lxsiwzx: 31929394 ==> 00000000929394a1
|
||||
lxsiwzx: a1a2a3a4 ==> 00000000a2a3a400
|
||||
lxsiwzx: 00000000 ==> 0000000000000010
|
||||
lxsiwzx: 89abcdef ==> 0000000089abcdef
|
||||
lxsiwzx: 00112233 ==> 0000000000112233
|
||||
lxsiwzx: 74556677 ==> 0000000074556677
|
||||
lxsiwzx: 00001abb ==> 0000000000001abb
|
||||
lxsiwzx: 00000001 ==> 0000000000000001
|
||||
lxsiwzx: 31929394 ==> 0000000031929394
|
||||
lxsiwzx: a1a2a3a4 ==> 00000000a1a2a3a4
|
||||
|
||||
|
||||
lxsspx: 3ec00000 ==> 3fd8000000000000
|
||||
|
||||
@ -31,7 +31,8 @@ check_PROGRAMS = \
|
||||
x86_amd64_features \
|
||||
s390x_features \
|
||||
mips_features \
|
||||
power_insn_available
|
||||
power_insn_available \
|
||||
is_ppc64_BE
|
||||
|
||||
AM_CFLAGS += $(AM_FLAG_M3264_PRI)
|
||||
AM_CXXFLAGS += $(AM_FLAG_M3264_PRI)
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
#!/bin/sh
|
||||
|
||||
# We use this script to check whether or not the processor supports Power ISA 2.06 or later.
|
||||
DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )"
|
||||
DIR="$( cd "$( dirname "$0" )" && pwd )"
|
||||
LD_SHOW_AUXV=1 $DIR/true | grep arch_2_06 > /dev/null 2>&1
|
||||
|
||||
if [ "$?" -ne "0" ]; then
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
|
||||
# We use this script to check whether or not the processor supports
|
||||
# Power ISA 2.07.
|
||||
DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )"
|
||||
DIR="$( cd "$( dirname "$0" )" && pwd )"
|
||||
LD_SHOW_AUXV=1 $DIR/true | grep arch_2_07 > /dev/null 2>&1
|
||||
|
||||
if [ "$?" -ne "0" ]; then
|
||||
|
||||
14
tests/is_ppc64_BE.c
Normal file
14
tests/is_ppc64_BE.c
Normal file
@ -0,0 +1,14 @@
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
// This program returns 0 if executing on ppc64 big endian; otherwise returns 1
|
||||
|
||||
int main(void)
|
||||
{
|
||||
#if defined(VGP_ppc64be_linux)
|
||||
return 0;
|
||||
#else
|
||||
return 1;
|
||||
#endif
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user