This set of tests covers MIPS r6 specific instructions:
none/tests/mips32/MIPS32r6int
none/tests/mips32/branch_pc
none/tests/mips32/branches_r6
none/tests/mips32/fp_r6
none/tests/mips32/pc_instructions_r6
none/tests/mips64/MIPS64r6int
none/tests/mips64/branch_pc
none/tests/mips64/branches_r6
none/tests/mips64/fp_r6
none/tests/mips64/pc_instructions_r6
none/tests/mips64/r6_instructions
The following tests had to be changed to be applicaple for Rev6:
none/tests/libvex_test.c
none/tests/mips32/LoadStore
none/tests/mips32/LoadStore1
none/tests/mips32/MIPS32int
none/tests/mips32/MoveIns
none/tests/mips32/branches
none/tests/mips32/change_fp_mode
none/tests/mips32/mips32_dsp
none/tests/mips32/vfp
none/tests/mips64/arithmetic_instruction
none/tests/mips64/branches
none/tests/mips64/fpu_arithmetic
none/tests/mips64/fpu_load_store
none/tests/mips64/load_store
none/tests/mips64/load_store_multiple
none/tests/mips64/move_instructions
The following tests are not applicable for Rev6:
none/tests/mips32/fpu_branches
none/tests/mips32/unaligned_load_store
none/tests/mips64/branch_and_jump_instructions
none/tests/mips64/change_fp_mode
none/tests/mips64/fpu_branches
none/tests/mips64/load_store_unaligned
none/tests/mips64/unaligned_load
none/tests/mips64/unaligned_load_store.
Contributed by:
Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic.
Related BZ issue - #387410.
Bits 18 (NAN2008) and 19 (ABS2008) in FCSR are preset by hardware and can
differ between platforms. Hence, we should clear these bits before printing
FCSR value in order to have the same output on different platforms.
This fixes several failures (tests modified by this change) that occur on
MIPS P5600 board. The P5600 is a core that implements MIPS32 Release 5 arch.
This set of tests covers the whole MSA instruction set:
none/tests/mips32/msa_arithmetic
none/tests/mips32/msa_comparison
none/tests/mips32/msa_data_transfer
none/tests/mips32/msa_fpu
none/tests/mips32/msa_logical_and_shift
none/tests/mips32/msa_shuffle
none/tests/mips64/msa_arithmetic (symlink to mips32)
none/tests/mips64/msa_comparison (symlink to mips32)
none/tests/mips64/msa_data_transfer
none/tests/mips64/msa_fpu (symlink to mips32)
none/tests/mips64/msa_logical_and_shift (symlink to mips32)
none/tests/mips64/msa_shuffle (symlink to mips32)
Contributed by:
Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic.
Related BZ issue - #382563.
Update the test cvm_atomic_thread so it can be executed on BE boards too.
Reuse the stdout.exp file.
Based on patch from Tamara Vlahovic.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16298
Leave the old exp file that covers cases in which __addtf3 and __subtf3
did not take into account rounding modes. New exp file is the same file
that already exists in mips32 folder, so we just create a symbolic link
to it.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16201
Add BE variant of exp file for cvm_atomic test.
This fixes none/tests/mips64/cvm_atomic for Cavium MIPS64 BE systems.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16183
Force "hardfloat" mode for inline assembly that uses FPU instructions,
but pop original mode at the end of the assembly. Unhandled FPU
instructions will be handled by the signal handler (env_unsup_insn).
Skip MIPS specific tests for FPU if the code gets compiled for soft-
float.
This should allow Valgrind to be compiled as a soft-float binary, but
that executable should be used for soft-float systems only.
Related VEX change - r3261.
Related issue - BZ#351282.
Patch by Aleksandar Rikalo.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16039
Clear floating point condition codes in the test after calling external
function (in this case printf), as it might have clobbered fcc bits in
fcsr.
This resolves none/tests/mips64/round.c failure on some systems.
Patch by Aleksandra Karadzic.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16038
Adding a program (change_fp_mode) to test correct fpu emulation and
fp mode switch using prctl syscalls.
Patch by Aleksandar Rikalo.
Related bug - BZ #366079.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16004
A little style improvement for load_indexed_instructions test including
addition of new instruction to be tested - lhx (supported as of VEX r3152).
Related issue - BZ #345987.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15340
Extend the test to introduce cases for SEQI and SNEI when immediate is
equal to the content of the GPR rs. Minor code style changes added.
Patch by Maran Pakkirisamy.
Related issue - BZ #341997.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15043
This is a follow up to VEX r3028. This change adds two test cases
for Cavium instructions BBIT032 and BBIT132.
Issue tracked in BZ #339288.
Patch by Maran Pakkirisamy.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14792
Cavium toolchain defaults to soft-float, so it is important to enable full
build of the test suite to work in that case as well.
This boils down to protecting FPU-specific code segments with
#if defined(__mips_hard_float)
#endif
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14572
Check whether the target platform is meant to have an FPU before executing
tests that make use of a floating-point unit.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14571
Tests that should be executed on MIPS64 platforms that support lwx, ldx
and lbux.
Relevant VEX change - r2819.
Patch by Zahid Anwar, with some changes.
Related to Bugzilla issue 326444. It closes this issue now.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13808
Read-memory tests are endian sensitive.
Add BE version of cvm_lx_ins.stdout.exp that has been tested on
Cavium Octeon II in BE mode.
Related to Bugzilla issue 326444.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13805
Tests for lhux, lwux, and lbx for Cavium Octeon II.
Patch by Zahid Anwar, with changes.
Related to Bugzilla issue 326444.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13786
make dist will not copy header files if they are not explicitly listed
in EXTRA_DIST. This change adds missing header files from none/test/mips64.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13701
Change the input values so that the binary values
is representing exactly the same float values.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13632
Change the existing tests to print the value of the FCSR
register after the mips fpu instruction is executed.
Add tests that are testing the value of FCSR register.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13560
Fixes make dist error.
Typo spotted and reported by Maran Pakkirisamy <maranp@linux.vnet.ibm.com>
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13424
Follow up to the previous change in which mips64 specific tests were added.
It covers both MIPS64-LE and MIPS64-BE.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13411
This change is a follow up to r13385. It removes physical copies of the
allexec c-files in none/tests/mips32/ and none/tests/mips64/ and defines
them as soft-links to a common file like other arches do.
Credits to Philippe for noticing it.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13388
