mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-03 18:13:01 +00:00
mips32/mips64: Add tests for lwl and lwr for mips32 and mips64.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13526
This commit is contained in:
Dejan Jevtic
parent
c09895b8e3
commit
63d3dd8351
@ -28,7 +28,9 @@ EXTRA_DIST = \
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mips32_dsp.stdout.exp-mips32 mips32_dsp.stderr.exp \
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mips32_dsp.vgtest \
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mips32_dspr2.stdout.exp mips32_dspr2.stderr.exp \
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mips32_dspr2.stdout.exp-mips32 mips32_dspr2.vgtest
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mips32_dspr2.stdout.exp-mips32 mips32_dspr2.vgtest \
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unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
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unaligned_load_store.stderr.exp unaligned_load_store.vgtest
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check_PROGRAMS = \
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allexec \
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@ -45,7 +47,8 @@ check_PROGRAMS = \
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SignalException \
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bug320057-mips32 \
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mips32_dsp \
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mips32_dspr2
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mips32_dspr2 \
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unaligned_load_store
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AM_CFLAGS += @FLAG_M32@
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AM_CXXFLAGS += @FLAG_M32@
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67
none/tests/mips32/unaligned_load_store.c
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67
none/tests/mips32/unaligned_load_store.c
Normal file
@ -0,0 +1,67 @@
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#include <stdio.h>
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unsigned int mem[] = {
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0xaabbccdd, 0x11223344, 0x01823194, 0x01823a08,
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0x00000000, 0x77ff528c, 0x77deb460, 0x00000001
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};
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void printMem(char* s)
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{
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int i;
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printf("%s\n", s);
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for (i=0; i<7 ; i=i+1)
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printf("mem[%d]: 0x%x\n", i, mem[i]);
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}
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int main ()
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{
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printMem("PRE lwl");
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__asm__ volatile("move $a0, %0" "\n\t"
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"lw $t0, 0($a0)" "\n\t"
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"lwl $t0, 4($a0)" "\n\t"
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"sw $t0, 8($a0)" "\n\t"
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"lw $t1, 0($a0)" "\n\t"
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"lwl $t1, 5($a0)" "\n\t"
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"sw $t1, 12($a0)" "\n\t"
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"lw $t2, 0($a0)" "\n\t"
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"lwl $t2, 6($a0)" "\n\t"
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"sw $t2, 16($a0)" "\n\t"
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"lw $t3, 0($a0)" "\n\t"
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"lwl $t3, 7($a0)" "\n\t"
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"sw $t3, 20($a0)" "\n\t"
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:
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: "r" (mem)
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: "a0", "t0", "t1", "t2", "t3", "cc", "memory"
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);
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printMem("POST lwl");
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mem[0] = 0xaabbccdd;
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mem[1] = 0x11223344;
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mem[2] = 0x01823194;
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mem[3] = 0x01823a08;
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mem[4] = 0x00000000;
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mem[5] = 0x77ff528c;
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mem[6] = 0x77deb460;
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mem[7] = 0x00000001;
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printMem("PRE lwr");
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__asm__ volatile("move $a0, %0" "\n\t"
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"lw $t0, 0($a0)" "\n\t"
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"lwr $t0, 4($a0)" "\n\t"
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"sw $t0, 8($a0)" "\n\t"
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"lw $t1, 0($a0)" "\n\t"
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"lwr $t1, 5($a0)" "\n\t"
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"sw $t1, 12($a0)" "\n\t"
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"lw $t2, 0($a0)" "\n\t"
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"lwr $t2, 6($a0)" "\n\t"
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"sw $t2, 16($a0)" "\n\t"
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"lw $t3, 0($a0)" "\n\t"
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"lwr $t3, 7($a0)" "\n\t"
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"sw $t3, 20($a0)" "\n\t"
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:
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: "r" (mem)
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: "a0", "t0", "t1", "t2", "t3", "cc", "memory"
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);
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printMem("POST lwr");
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return 0;
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}
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0
none/tests/mips32/unaligned_load_store.stderr.exp
Normal file
0
none/tests/mips32/unaligned_load_store.stderr.exp
Normal file
32
none/tests/mips32/unaligned_load_store.stdout.exp-BE
Normal file
32
none/tests/mips32/unaligned_load_store.stdout.exp-BE
Normal file
@ -0,0 +1,32 @@
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PRE lwl
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x1823194
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mem[3]: 0x1823a08
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mem[4]: 0x0
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mem[5]: 0x77ff528c
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mem[6]: 0x77deb460
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POST lwl
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x11223344
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mem[3]: 0x223344dd
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mem[4]: 0x3344ccdd
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mem[5]: 0x44bbccdd
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mem[6]: 0x77deb460
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PRE lwr
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x1823194
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mem[3]: 0x1823a08
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mem[4]: 0x0
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mem[5]: 0x77ff528c
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mem[6]: 0x77deb460
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POST lwr
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0xaabbcc11
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mem[3]: 0xaabb1122
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mem[4]: 0xaa112233
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mem[5]: 0x11223344
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mem[6]: 0x77deb460
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32
none/tests/mips32/unaligned_load_store.stdout.exp-LE
Normal file
32
none/tests/mips32/unaligned_load_store.stdout.exp-LE
Normal file
@ -0,0 +1,32 @@
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PRE lwl
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x1823194
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mem[3]: 0x1823a08
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mem[4]: 0x0
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mem[5]: 0x77ff528c
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mem[6]: 0x77deb460
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POST lwl
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x44bbccdd
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mem[3]: 0x3344ccdd
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mem[4]: 0x223344dd
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mem[5]: 0x11223344
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mem[6]: 0x77deb460
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PRE lwr
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x1823194
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mem[3]: 0x1823a08
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mem[4]: 0x0
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mem[5]: 0x77ff528c
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mem[6]: 0x77deb460
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POST lwr
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x11223344
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mem[3]: 0xaa112233
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mem[4]: 0xaabb1122
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mem[5]: 0xaabbcc11
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mem[6]: 0x77deb460
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2
none/tests/mips32/unaligned_load_store.vgtest
Normal file
2
none/tests/mips32/unaligned_load_store.vgtest
Normal file
@ -0,0 +1,2 @@
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prog: unaligned_load_store
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vgopts: -q
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@ -37,7 +37,9 @@ EXTRA_DIST = \
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test_block_size.stdout.exp test_block_size.stderr.exp \
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test_block_size.vgtest \
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unaligned_load.stdout.exp-BE unaligned_load.stdout.exp-LE \
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unaligned_load.stderr.exp unaligned_load.vgtest
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unaligned_load.stderr.exp unaligned_load.vgtest \
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unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
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unaligned_load_store.stderr.exp unaligned_load_store.vgtest
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check_PROGRAMS = \
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allexec \
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@ -58,7 +60,8 @@ check_PROGRAMS = \
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round \
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shift_instructions \
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test_block_size \
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unaligned_load
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unaligned_load \
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unaligned_load_store
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AM_CFLAGS += @FLAG_M64@
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AM_CXXFLAGS += @FLAG_M64@
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67
none/tests/mips64/unaligned_load_store.c
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67
none/tests/mips64/unaligned_load_store.c
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@ -0,0 +1,67 @@
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#include <stdio.h>
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unsigned int mem[] = {
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0xaabbccdd, 0x11223344, 0x01823194, 0x01823a08,
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0x00000000, 0x77ff528c, 0x77deb460, 0x00000001
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};
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void printMem(char* s)
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{
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int i;
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printf("%s\n", s);
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for (i=0; i<7 ; i=i+1)
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printf("mem[%d]: 0x%x\n", i, mem[i]);
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}
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int main ()
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{
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printMem("PRE lwl");
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__asm__ volatile("move $a0, %0" "\n\t"
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"lw $t0, 0($a0)" "\n\t"
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"lwl $t0, 4($a0)" "\n\t"
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"sw $t0, 8($a0)" "\n\t"
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"lw $t1, 0($a0)" "\n\t"
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"lwl $t1, 5($a0)" "\n\t"
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"sw $t1, 12($a0)" "\n\t"
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"lw $t2, 0($a0)" "\n\t"
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"lwl $t2, 6($a0)" "\n\t"
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"sw $t2, 16($a0)" "\n\t"
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"lw $t3, 0($a0)" "\n\t"
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"lwl $t3, 7($a0)" "\n\t"
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"sw $t3, 20($a0)" "\n\t"
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:
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: "r" (mem)
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: "a0", "t0", "t1", "t2", "t3", "cc", "memory"
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);
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printMem("POST lwl");
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mem[0] = 0xaabbccdd;
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mem[1] = 0x11223344;
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mem[2] = 0x01823194;
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mem[3] = 0x01823a08;
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mem[4] = 0x00000000;
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mem[5] = 0x77ff528c;
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mem[6] = 0x77deb460;
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mem[7] = 0x00000001;
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printMem("PRE lwr");
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__asm__ volatile("move $a0, %0" "\n\t"
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"lw $t0, 0($a0)" "\n\t"
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"lwr $t0, 4($a0)" "\n\t"
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"sw $t0, 8($a0)" "\n\t"
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"lw $t1, 0($a0)" "\n\t"
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"lwr $t1, 5($a0)" "\n\t"
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"sw $t1, 12($a0)" "\n\t"
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"lw $t2, 0($a0)" "\n\t"
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"lwr $t2, 6($a0)" "\n\t"
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"sw $t2, 16($a0)" "\n\t"
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"lw $t3, 0($a0)" "\n\t"
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"lwr $t3, 7($a0)" "\n\t"
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"sw $t3, 20($a0)" "\n\t"
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:
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: "r" (mem)
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: "a0", "t0", "t1", "t2", "t3", "cc", "memory"
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);
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printMem("POST lwr");
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return 0;
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}
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0
none/tests/mips64/unaligned_load_store.stderr.exp
Normal file
0
none/tests/mips64/unaligned_load_store.stderr.exp
Normal file
32
none/tests/mips64/unaligned_load_store.stdout.exp-BE
Normal file
32
none/tests/mips64/unaligned_load_store.stdout.exp-BE
Normal file
@ -0,0 +1,32 @@
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PRE lwl
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x1823194
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mem[3]: 0x1823a08
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mem[4]: 0x0
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mem[5]: 0x77ff528c
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mem[6]: 0x77deb460
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POST lwl
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x11223344
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mem[3]: 0x223344dd
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mem[4]: 0x3344ccdd
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mem[5]: 0x44bbccdd
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mem[6]: 0x77deb460
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PRE lwr
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x1823194
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mem[3]: 0x1823a08
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mem[4]: 0x0
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mem[5]: 0x77ff528c
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mem[6]: 0x77deb460
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POST lwr
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0xaabbcc11
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mem[3]: 0xaabb1122
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mem[4]: 0xaa112233
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mem[5]: 0x11223344
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mem[6]: 0x77deb460
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32
none/tests/mips64/unaligned_load_store.stdout.exp-LE
Normal file
32
none/tests/mips64/unaligned_load_store.stdout.exp-LE
Normal file
@ -0,0 +1,32 @@
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PRE lwl
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x1823194
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mem[3]: 0x1823a08
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mem[4]: 0x0
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mem[5]: 0x77ff528c
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mem[6]: 0x77deb460
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POST lwl
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x44bbccdd
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mem[3]: 0x3344ccdd
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mem[4]: 0x223344dd
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mem[5]: 0x11223344
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mem[6]: 0x77deb460
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PRE lwr
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x1823194
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mem[3]: 0x1823a08
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mem[4]: 0x0
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mem[5]: 0x77ff528c
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mem[6]: 0x77deb460
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POST lwr
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mem[0]: 0xaabbccdd
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mem[1]: 0x11223344
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mem[2]: 0x11223344
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mem[3]: 0xaa112233
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mem[4]: 0xaabb1122
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mem[5]: 0xaabbcc11
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mem[6]: 0x77deb460
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2
none/tests/mips64/unaligned_load_store.vgtest
Normal file
2
none/tests/mips64/unaligned_load_store.vgtest
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@ -0,0 +1,2 @@
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prog: unaligned_load_store
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vgopts: -q
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