Thanks to Jakub Jelinek. The test is broken. It blindly assumes the
toplevel inline asm is placed into some sensible section, but that is
a wrong assumption. The right thing is to start the inline asm with
.text directive and end with .previous. The reason gcc 10 breaks it
is the -fno-common default, the int r1, ... vars are emitted into .bss
section and that is the section that is current when the inline asm is
emitted previously they were in .common at the end of the assembly file.
GCC10 defaults to -fno-common which produces this error:
guest_s390_defs.h:291: multiple definition of `s390x_vec_op_t
This is because GCC10 detects there are multiple definitions of the
variable s390x_vec_op_t. We don't want to define a variable though.
We had wanted to define a type (one that currently isn't used).
Fix this by making it a typedef enum.
https://bugzilla.redhat.com/show_bug.cgi?id=1794482
Guard withinEpsOf[FD] within none/tests/mips32/msa_fpu.c
Enclose the recently introduced functions with preprocessor guards,
much like the rest of the code is inside the main function.
Also mark the functions as static.
Minor code formatting.
Mark the immediate as signed for Iex_Get and Ist_Put for Ity_V128 on BE.
The Malu_MADD case in emit_MIPSInst in VEX/priv/host_mips_defs.c expects a
signed immediate, hence the change.
This fixes an assert in host_mips_defs.c.
Change the math tests to check whether the results are approximate to the
expected values instead of checking for exact matches since the calculations
in question are allowed to be approximate.
This fixes
/none/tests/mips64/test_math and
/none/tests/mips64/msa_fpu
on mips64r6.
This might happen when the source contains something like
if (something_involving_pcmpxstrx && foo) { .. }
which might use amd64g_dirtyhelper_PCMPxSTRx.
Instruction decoding was not correct. In some cases, BEQC has been decoded
as BNEC and vice versa.
It caused problems with musl malloc() function.
Patch by Stefan Maksimovic.
- Restore guest sigmask in VG_(sigframe_destroy)
- Use "syscall[32]" asm idiom instead of "syscall" with immediate parameter
in VG_(nanomips_linux_SUBST_FOR_rt_sigreturn)
- Call ML_(fixup_guest_state_to_restart_syscall) from PRE(sys_rt_sigreturn)
- Tiny code refactor of sigframe-nanomips-linux.c
This fixes none/tests/thread-exits.
UASWM and UALWM have not been implemented correctly.
Code used to implement SWM and LWM has been reused without making all of
the required adjustments.
This fixes memcpy() and memset() libc functions.
This code portion introduced a SEGFAULT:
- if (&i->NMin.Cas.sz){
+ if (i->NMin.Cas.sz == 8) {
The implementation of Ist_Cas has been fixed and missing logging has been
added as well.
During a save (push) instruction adjusting the SP is required before doing
a store, otherwise Memcheck reports warning because of a write operation
outside of the stack area.
- Reset syscall return register (a0) in clone_new_thread()
- Use "syscall[32]" asm idiom instead of "syscall" with immediate parameter
in ML_ (call_on_new_stack_0_1)()
- Optimize stack usage in ML_ (call_on_new_stack_0_1)()
- Code refactor of ML_ (call_on_new_stack_0_1)()
It partially fixes all tests which use clone system call, e.g. none/tests/pth_atfork1.
Patch by Aleksandar Rikalo.
Patches from Bug #400872 (Add nanoMIPS support to Valgrind) have been
merged.
Update README.mips with a correct configure line applicable for the latest
nanomips toolchain package in public.
This splits function iselCondCode into iselCondCode_C and iselCondCode_R, the
former of which is the old one that computes boolean expressions into an amd64
condition code, but the latter being new, and computes boolean expressions
into the lowest bit of an integer register. This enables much better code
generation for Or1/And1 trees, which now result quite commonly from the new
&&-recovery machinery in the front end.
Until now these have been handled by possibly widening the value to 64 bits,
if necessary, followed by a 64-bit shift. That wastes instructions and code
space.
This has unfortunately become necessary because optimising compilers are
generating 64-bit equality comparisons on partially defined values on this
target. There will shortly be two followup commits which partially mitigate
the resulting performance loss.
.. hence treating it as a dependency-breaking idiom. Also handle the
resulting IRConst_V256(0xFFFFFFFF) in the amd64 insn selector.
(dup of 96de5118f5332ae145912ebe91b8fa143df74b8d from 'grail')
Possibly fixes#409429.
This isn't a good result. It merely disables the new functionality on MIPS
because enabling it causes segfaults, even with --tool=none, the cause of
which are not obvious. It is only chasing through conditional branches that
is disabled, though. Chasing through unconditional branches (jumps and calls
to known destinations) is still enabled.
* guest_generic_bb_to_IR.c bb_to_IR(): Disable, hopefully temporarily, the key
&&-recovery transformation on MIPS.
* VEX/priv/host_mips_isel.c iselWordExpr_R_wrk(), iselCondCode_wrk():
- add support for Iop_And1, Iop_Or1, and IRConst_U1. This code is my best
guess about what is correct, but is #if 0'd for now.
- Properly guard some Iex_Binop cases that lacked a leading check that the
expression actually was a Binop.
This isn't a good result. It merely disables the new functionality on s390x,
for the reason stated below.
* guest_generic_bb_to_IR.c bb_to_IR(): Disable, hopefully temporarily, the key
&&-recovery transformation on s390x, since it causes Memcheck to crash for
reasons I couldn't figure out. It also exposes some missing Iex_ITE cases
in the s390x insn selector, although those shouldn't be a big deal to fix.
Maybe it's some strangeness to do with the s390x "ex" instruction. I don't
exactly understand how that trickery works, but from some study of it, I
didn't see anything obviously wrong.
It is only chasing through conditional branches that is disabled for s390x.
Chasing through unconditional branches (jumps and calls to known
destinations) is still enabled.
* host_s390_isel.c s390_isel_cc(): No functional change. Code has been added
here to handle the new Iop_And1 and Iop_Or1, and it is somewhat tested, but
is not needed until conditional branch chasing is enabled on s390x.
* do_minimal_initial_iropt_BB: for ppc64, flatten rather than assert flatness.
(Kludge. Sigh.)
* priv/host_ppc_isel.c iselCondCode_wrk(): handle And1 and Or1, the
not-particularly-optimal way
* priv/host_ppc_isel.c iselCondCode_wrk(): handle Ico_U1(0).
* priv/guest_generic_bb_to_IR.c expr_is_guardable(), stmt_is_guardable():
add some missing cases
* do_minimal_initial_iropt_BB: add comment (no functional change)
* priv/host_arm_isel.c iselCondCode_wrk(): handle And1 and Or1, the
not-particularly-optimal way
* guest_arm64_toIR.c: use |sigill_diag| to guard auxiliary diagnostic printing
in case of decode failure
* guest_generic_bb_to_IR.c expr_is_guardable(), stmt_is_guardable(): handle a
few more cases that didn't turn up so far on x86 or amd64
* host_arm64_defs.[ch]:
- new instruction ARM64Instr_Set64, to copy a condition code value into a
register (the CSET instruction)
- use this to reimplement Iop_And1 and Iop_Or1
