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mips: add tests for mips32/mips64 R6

Browse Source 
This set of tests covers MIPS r6 specific instructions:

  none/tests/mips32/MIPS32r6int
  none/tests/mips32/branch_pc
  none/tests/mips32/branches_r6
  none/tests/mips32/fp_r6
  none/tests/mips32/pc_instructions_r6

  none/tests/mips64/MIPS64r6int
  none/tests/mips64/branch_pc
  none/tests/mips64/branches_r6
  none/tests/mips64/fp_r6
  none/tests/mips64/pc_instructions_r6
  none/tests/mips64/r6_instructions

The following tests had to be changed to be applicaple for Rev6:

  none/tests/libvex_test.c

  none/tests/mips32/LoadStore
  none/tests/mips32/LoadStore1
  none/tests/mips32/MIPS32int
  none/tests/mips32/MoveIns
  none/tests/mips32/branches
  none/tests/mips32/change_fp_mode
  none/tests/mips32/mips32_dsp
  none/tests/mips32/vfp

  none/tests/mips64/arithmetic_instruction
  none/tests/mips64/branches
  none/tests/mips64/fpu_arithmetic
  none/tests/mips64/fpu_load_store
  none/tests/mips64/load_store
  none/tests/mips64/load_store_multiple
  none/tests/mips64/move_instructions

The following tests are not applicable for Rev6:

  none/tests/mips32/fpu_branches
  none/tests/mips32/unaligned_load_store

  none/tests/mips64/branch_and_jump_instructions
  none/tests/mips64/change_fp_mode
  none/tests/mips64/fpu_branches
  none/tests/mips64/load_store_unaligned
  none/tests/mips64/unaligned_load
  none/tests/mips64/unaligned_load_store.

Contributed by:
  Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic.

Related BZ issue - #387410.
This commit is contained in:
Petar Jovanovic 2018-02-01 18:37:28 +01:00
parent fd120874fb
commit 9fc2bfba5c
106 changed files with 76275 additions and 119 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
.gitignore vendored
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@ -1593,9 +1593,12 @@
/none/tests/mips32/.deps
/none/tests/mips32/allexec
/none/tests/mips32/block_size
/none/tests/mips32/branch_pc
/none/tests/mips32/branches
/none/tests/mips32/branches_r6
/none/tests/mips32/bug320057-mips32
/none/tests/mips32/change_fp_mode
/none/tests/mips32/fp_r6
/none/tests/mips32/fpu_branches
/none/tests/mips32/FPUarithmetic
/none/tests/mips32/LoadStore
@ -1603,6 +1606,7 @@
/none/tests/mips32/mips32_dsp
/none/tests/mips32/mips32_dspr2
/none/tests/mips32/MIPS32int
/none/tests/mips32/MIPS32r6int
/none/tests/mips32/MoveIns
/none/tests/mips32/msa_arithmetic
/none/tests/mips32/msa_comparison
@ -1611,6 +1615,7 @@
/none/tests/mips32/msa_logical_and_shift
/none/tests/mips32/msa_shuffle
/none/tests/mips32/LoadStore1
/none/tests/mips32/pc_instructions_r6
/none/tests/mips32/round
/none/tests/mips32/round_fpu64
/none/tests/mips32/SignalException
@ -1619,6 +1624,7 @@
/none/tests/mips32/unaligned_load_store
/none/tests/mips32/vfp
# /none/tests/mips64/
/none/tests/mips64/Makefile
/none/tests/mips64/Makefile.in

5
none/tests/libvex_test.c
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@ -126,8 +126,13 @@ static UInt arch_hwcaps (VexArch va) {
case VexArchPPC32: return 0;
case VexArchPPC64: return 0;
case VexArchS390X: return VEX_HWCAPS_S390X_LDISP;
#if (__mips_isa_rev>=6)
case VexArchMIPS32: return VEX_PRID_COMP_MIPS | VEX_MIPS_CPU_ISA_M32R6;
case VexArchMIPS64: return VEX_PRID_COMP_MIPS | VEX_MIPS_CPU_ISA_M64R6;
#else
case VexArchMIPS32: return VEX_PRID_COMP_MIPS;
case VexArchMIPS64: return VEX_PRID_COMP_MIPS;
#endif
default: failure_exit();
}
}

2
none/tests/mips32/LoadStore.c
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@ -223,6 +223,7 @@ int main()
ppMem(mem1, 16);
ppMem1(mem, 16);
#if (__mips_isa_rev < 6)
printf("swl\n");
TESTINST1("swl $t0, 0($t1)", 0, 0, t0, t1);
TESTINST1("swl $t0, 0($t1)", 0x31415927, 0, t0, t1);
@ -350,5 +351,6 @@ int main()
ppMem0(mem2, 12);
TESTINSTsw(0x2aaee700, 32, t0, t1);
ppMem0(mem2, 12);
#endif
return 0;
}

171
none/tests/mips32/LoadStore.stdout.exp-r6-BE Normal file
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@ -0,0 +1,171 @@
sb
sb $t0, 0($t1) :: RTval: 0x0, out: 0x0
sb $t0, 0($t1) :: RTval: 0x0, out: 0x1f1e1f
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x271f1e1f
sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xff000000
sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xff1f1e1f
sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x1f1e1f
sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x1f0000
sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xff000000
sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xff000000
sb $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xff000000
sb $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xff03ffff
sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ff00
sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ff03
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x271f001f
sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x1f001f
sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f000000
sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f1f001f
sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71000000
sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x711f001f
sb $t0, 0($t1) :: RTval: 0xf, out: 0xf000000
sb $t0, 0($t1) :: RTval: 0xf, out: 0xf1f001f
sb $t0, 0($t1) :: RTval: 0x1, out: 0x1000000
sb $t0, 0($t1) :: RTval: 0x1, out: 0x11f001f
sb $t0, 0($t1) :: RTval: 0x35, out: 0x35000000
sb $t0, 0($t1) :: RTval: 0x35, out: 0x351f001f
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000000
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff1f0000
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000000
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff1f0000
sb $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
sb $t0, 32($t1) :: RTval: 0xffffffff, out: 0xff343f3e
sb $t0, 36($t1) :: RTval: 0xffffffff, out: 0xff000000
sb $t0, 36($t1) :: RTval: 0xffffffff, out: 0xff353d3c
sb $t0, 40($t1) :: RTval: 0x31415927, out: 0x27000000
sb $t0, 40($t1) :: RTval: 0x31415927, out: 0x273a3c3b
sb $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xff000000
sb $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xff373b3a
sb $t0, 48($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 48($t1) :: RTval: 0x80000000, out: 0x4f4e45
sb $t0, 52($t1) :: RTval: 0x28f, out: 0x8f000000
sb $t0, 52($t1) :: RTval: 0x28f, out: 0x8f464d46
MEM1:
0x3500ff00, 0xff00, 0xff00ff00, 0x0
0x0, 0x0, 0x0, 0x0
0xffffffff, 0xff000000, 0x27000000, 0xff000000
0x0, 0x8f000000, 0x0, 0x0
MEM:
0x351fff1f, 0xff00, 0xff00ff03, 0xffffffff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
0xff343f3e, 0xff353d3c, 0x273a3c3b, 0xff373b3a
0x4f4e45, 0x8f464d46, 0x474d474c, 0x4a484a4c
sh
sh $t0, 0($t1) :: RTval: 0x0, out: 0x0
sh $t0, 0($t1) :: RTval: 0x0, out: 0x1e1f
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270000
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59271e1f
sh $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xffff1e1f
sh $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 0($t1) :: RTval: 0x80000000, out: 0x1e1f
sh $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffffffff
sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270000
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270000
sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0000
sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0000
sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710000
sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710000
sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0000
sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0000
sh $t0, 0($t1) :: RTval: 0x1, out: 0x10000
sh $t0, 0($t1) :: RTval: 0x1, out: 0x10000
sh $t0, 0($t1) :: RTval: 0x35, out: 0x350000
sh $t0, 0($t1) :: RTval: 0x35, out: 0x350000
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff0000
sh $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffff0000
sh $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffff3f3e
sh $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffff0000
sh $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffff3d3c
sh $t0, 40($t1) :: RTval: 0x31415927, out: 0x59270000
sh $t0, 40($t1) :: RTval: 0x31415927, out: 0x59273c3b
sh $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xffff3b3a
sh $t0, 48($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 48($t1) :: RTval: 0x80000000, out: 0x4e45
sh $t0, 52($t1) :: RTval: 0x28f, out: 0x28f0000
sh $t0, 52($t1) :: RTval: 0x28f, out: 0x28f4d46
MEM1:
0x35ffff, 0xffff, 0xffffffff, 0x0
0x0, 0x0, 0x0, 0x0
0xffff0000, 0xffff0000, 0x59270000, 0xffff0000
0x0, 0x28f0000, 0x0, 0x0
MEM:
0x35ffff, 0xffff, 0xffffffff, 0xffffffff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
0xffff3f3e, 0xffff3d3c, 0x59273c3b, 0xffff3b3a
0x4e45, 0x28f4d46, 0x474d474c, 0x4a484a4c
sw
sw $t0, 0($t1) :: RTval: 0x0, out: 0x0
sw $t0, 0($t1) :: RTval: 0x0, out: 0x0
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
MEM1:
0xffff, 0xffff7fff, 0xffffffff, 0xffff0000
0x0, 0x0, 0x0, 0x0
0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
0x80000000, 0x28f, 0x0, 0x0
MEM:
0xffff, 0xffff7fff, 0xffffffff, 0xffffffff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
0x80000000, 0x28f, 0x474d474c, 0x4a484a4c

171
none/tests/mips32/LoadStore.stdout.exp-r6-LE Normal file
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@ -0,0 +1,171 @@
sb
sb $t0, 0($t1) :: RTval: 0x0, out: 0x0
sb $t0, 0($t1) :: RTval: 0x0, out: 0x121f1e00
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f1e27
sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xff
sb $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x121f1eff
sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 0($t1) :: RTval: 0x80000000, out: 0x121f1e00
sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x1200
sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xff
sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x300ff
sb $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xff
sb $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffff00ff
sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ff
sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ff
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x12001e27
sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x12001e00
sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f
sb $t0, 0($t1) :: RTval: 0x28f, out: 0x12001e8f
sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71
sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x12001e71
sb $t0, 0($t1) :: RTval: 0xf, out: 0xf
sb $t0, 0($t1) :: RTval: 0xf, out: 0x12001e0f
sb $t0, 0($t1) :: RTval: 0x1, out: 0x1
sb $t0, 0($t1) :: RTval: 0x1, out: 0x12001e01
sb $t0, 0($t1) :: RTval: 0x35, out: 0x35
sb $t0, 0($t1) :: RTval: 0x35, out: 0x12001e35
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x12ff
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x12ff
sb $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
sb $t0, 32($t1) :: RTval: 0xffffffff, out: 0x3f343fff
sb $t0, 36($t1) :: RTval: 0xffffffff, out: 0xff
sb $t0, 36($t1) :: RTval: 0xffffffff, out: 0x3e353dff
sb $t0, 40($t1) :: RTval: 0x31415927, out: 0x27
sb $t0, 40($t1) :: RTval: 0x31415927, out: 0x363a3c27
sb $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xff
sb $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x3b373bff
sb $t0, 48($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 48($t1) :: RTval: 0x80000000, out: 0x454f4e00
sb $t0, 52($t1) :: RTval: 0x28f, out: 0x8f
sb $t0, 52($t1) :: RTval: 0x28f, out: 0x4e464d8f
MEM1:
0xff0035, 0xff0000, 0xff00ff, 0x0
0x0, 0x0, 0x0, 0x0
0xffffffff, 0xff, 0x27, 0xff
0x0, 0x8f, 0x0, 0x0
MEM:
0x12ff1e35, 0xff0000, 0xff00ff, 0xffffffff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
0x3f343fff, 0x3e353dff, 0x363a3c27, 0x3b373bff
0x454f4e00, 0x4e464d8f, 0x474d474c, 0x4a484a4c
sh
sh $t0, 0($t1) :: RTval: 0x0, out: 0x0
sh $t0, 0($t1) :: RTval: 0x0, out: 0x121f0000
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x5927
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x121f5927
sh $t0, 0($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x121fffff
sh $t0, 0($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 0($t1) :: RTval: 0x80000000, out: 0x121f0000
sh $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 2($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x3ffff
sh $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 10($t1) :: RTval: 0x7fffffff, out: 0xffffffff
sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x5927
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x5927
sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd71
sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd71
sh $t0, 0($t1) :: RTval: 0xf, out: 0xf
sh $t0, 0($t1) :: RTval: 0xf, out: 0xf
sh $t0, 0($t1) :: RTval: 0x1, out: 0x1
sh $t0, 0($t1) :: RTval: 0x1, out: 0x1
sh $t0, 0($t1) :: RTval: 0x35, out: 0x35
sh $t0, 0($t1) :: RTval: 0x35, out: 0x35
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff
sh $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffff
sh $t0, 32($t1) :: RTval: 0xffffffff, out: 0x3f34ffff
sh $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffff
sh $t0, 36($t1) :: RTval: 0xffffffff, out: 0x3e35ffff
sh $t0, 40($t1) :: RTval: 0x31415927, out: 0x5927
sh $t0, 40($t1) :: RTval: 0x31415927, out: 0x363a5927
sh $t0, 44($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x3b37ffff
sh $t0, 48($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 48($t1) :: RTval: 0x80000000, out: 0x454f0000
sh $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
sh $t0, 52($t1) :: RTval: 0x28f, out: 0x4e46028f
MEM1:
0xffff0035, 0xffff0000, 0xffffffff, 0x0
0x0, 0x0, 0x0, 0x0
0xffff, 0xffff, 0x5927, 0xffff
0x0, 0x28f, 0x0, 0x0
MEM:
0xffff0035, 0xffff0000, 0xffffffff, 0xffffffff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
0x3f34ffff, 0x3e35ffff, 0x363a5927, 0x3b37ffff
0x454f0000, 0x4e46028f, 0x474d474c, 0x4a484a4c
sw
sw $t0, 0($t1) :: RTval: 0x0, out: 0x0
sw $t0, 0($t1) :: RTval: 0x0, out: 0x0
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 0($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 0($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 2($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 10($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 32($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 36($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 40($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 44($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 48($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 52($t1) :: RTval: 0x28f, out: 0x28f
MEM1:
0xffff0035, 0xffffffff, 0xffffffff, 0x7fff
0x0, 0x0, 0x0, 0x0
0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
0x80000000, 0x28f, 0x0, 0x0
MEM:
0xffff0035, 0xffffffff, 0xffffffff, 0xffff7fff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2d2a
0xffffffff, 0xffffffff, 0x31415927, 0x7fffffff
0x80000000, 0x28f, 0x474d474c, 0x4a484a4c

2
none/tests/mips32/LoadStore1.c
View File

@ -223,6 +223,7 @@ int main()
ppMem(mem1, 16);
ppMem1(mem, 16);
#if (__mips_isa_rev < 6)
printf("swl\n");
TESTINST1("swl $t0, 1($t1)", 0, 1, t0, t1);
TESTINST1("swl $t0, 3($t1)", 0x31415927, 3, t0, t1);
@ -350,6 +351,7 @@ int main()
ppMem0(mem2, 12);
TESTINSTsw(0x2aaee700, 32, t0, t1);
ppMem0(mem2, 12);
#endif
return 0;
}

171
none/tests/mips32/LoadStore1.stdout.exp-r6-BE Normal file
View File

@ -0,0 +1,171 @@
sb
sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27000000
sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27000000
sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff000000
sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff000000
sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x1e0000
sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27
sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27
sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xff000000
sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff
sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000
sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f000000
sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f000000
sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71000000
sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71000000
sb $t0, 0($t1) :: RTval: 0xf, out: 0xf000000
sb $t0, 0($t1) :: RTval: 0xf, out: 0xf000000
sb $t0, 0($t1) :: RTval: 0x1, out: 0x1000000
sb $t0, 0($t1) :: RTval: 0x1, out: 0x1000000
sb $t0, 0($t1) :: RTval: 0x35, out: 0x35000000
sb $t0, 0($t1) :: RTval: 0x35, out: 0x35000000
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027
sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0xff3f343f
sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff000000
sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff3e353d
sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x27000000
sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x273c3b3b
sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0xff000000
sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0xff3b3b37
sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x3b3a45
sb $t0, 51($t1) :: RTval: 0x28f, out: 0x8f000000
sb $t0, 51($t1) :: RTval: 0x28f, out: 0x8f4e464d
MEM1:
0x3500ff00, 0x27ffff, 0xff0000ff, 0x0
0x0, 0x0, 0x0, 0xff
0xffffffff, 0x0, 0x27ff00, 0x0
0x8f, 0x0, 0x0, 0x0
MEM:
0x3500ff00, 0x27ffff, 0xff0000ff, 0xffffffff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2dff
0x3f343fff, 0x3e353d3c, 0x3627ff3b, 0x3b003b3a
0x454f4e8f, 0x4e464d46, 0x474d474c, 0x4a484a4c
sh
sh $t0, 1($t1) :: RTval: 0x0, out: 0x0
sh $t0, 1($t1) :: RTval: 0x0, out: 0x1f00
sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x59270000
sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x59270000
sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 9($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 9($t1) :: RTval: 0x80000000, out: 0x3ff
sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffff00ff
sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffff00ff
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270059
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270059
sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x59
sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x59
sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0059
sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0059
sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710059
sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710059
sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0059
sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0059
sh $t0, 0($t1) :: RTval: 0x1, out: 0x10059
sh $t0, 0($t1) :: RTval: 0x1, out: 0x10059
sh $t0, 0($t1) :: RTval: 0x35, out: 0x350059
sh $t0, 0($t1) :: RTval: 0x35, out: 0x350059
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff
sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffff0000
sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffff343f
sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0xffff0000
sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0xffff353d
sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x59270000
sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x59273b3b
sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xffff4f4e
sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x454e
sh $t0, 51($t1) :: RTval: 0x28f, out: 0x28f0000
sh $t0, 51($t1) :: RTval: 0x28f, out: 0x28f464d
MEM1:
0x35ffff, 0x27ffffff, 0xffff00ff, 0xff000000
0x0, 0x0, 0x0, 0xff
0xff0000ff, 0xff000000, 0x592700, 0xff
0xff000002, 0x8f000000, 0x0, 0x0
MEM:
0x35ffff, 0x27ffffff, 0xffff00ff, 0xffffffff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2dff
0xff343fff, 0xff353d3c, 0x3659273b, 0x3b373bff
0xff000002, 0x8f464d46, 0x474d474c, 0x4a484a4c
sw
sw $t0, 1($t1) :: RTval: 0x0, out: 0x0
sw $t0, 1($t1) :: RTval: 0x0, out: 0x0
sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0x0
sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0xffff
sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
MEM1:
0xffff, 0xffff7fff, 0xffffffff, 0x7f
0xffffff00, 0x0, 0x0, 0xff
0xffffff00, 0xffffff, 0xff7fff80, 0x0
0x314100, 0x28f00, 0x0, 0x0
MEM:
0xffff, 0xffff7fff, 0xffffffff, 0xffff7f
0xffffff2f, 0x242c2b2b, 0x252a2e2b, 0x262d2dff
0xffffff3e, 0x3effffff, 0xff7fff80, 0x3a
0x45314100, 0x28f46, 0x474d474c, 0x4a484a4c

171
none/tests/mips32/LoadStore1.stdout.exp-r6-LE Normal file
View File

@ -0,0 +1,171 @@
sb
sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27
sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x3000027
sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff
sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0x3ff
sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x1f00
sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27000000
sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27000000
sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff
sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x3ffff
sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xff
sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff
sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27
sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f
sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f
sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71
sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71
sb $t0, 0($t1) :: RTval: 0xf, out: 0xf
sb $t0, 0($t1) :: RTval: 0xf, out: 0xf
sb $t0, 0($t1) :: RTval: 0x1, out: 0x1
sb $t0, 0($t1) :: RTval: 0x1, out: 0x1
sb $t0, 0($t1) :: RTval: 0x35, out: 0x35
sb $t0, 0($t1) :: RTval: 0x35, out: 0x35
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff
sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0x343f3eff
sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff
sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0x353d3cff
sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x27
sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x3a363a27
sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0xff
sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0x3b3a36ff
sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x453b3700
sb $t0, 51($t1) :: RTval: 0x28f, out: 0x8f
sb $t0, 51($t1) :: RTval: 0x28f, out: 0x464d468f
MEM1:
0xff0035, 0xffff2700, 0xff0000ff, 0x0
0x0, 0x0, 0x0, 0xff000000
0xffffffff, 0x0, 0xff2700, 0x0
0x8f000000, 0x0, 0x0, 0x0
MEM:
0xff0035, 0xffff2700, 0xff0000ff, 0xffffffff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0xff2d2d2a
0xff343f3e, 0x3e353d3c, 0x36ff273b, 0x3b37003a
0x8f4f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c
sh
sh $t0, 1($t1) :: RTval: 0x0, out: 0x0
sh $t0, 1($t1) :: RTval: 0x0, out: 0x120000
sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x5927
sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x5927
sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x300ffff
sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 9($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 9($t1) :: RTval: 0x80000000, out: 0xff000000
sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ffff
sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ffff
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x27005927
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x27005927
sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x27000000
sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x27000000
sh $t0, 0($t1) :: RTval: 0x28f, out: 0x2700028f
sh $t0, 0($t1) :: RTval: 0x28f, out: 0x2700028f
sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x2700fd71
sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x2700fd71
sh $t0, 0($t1) :: RTval: 0xf, out: 0x2700000f
sh $t0, 0($t1) :: RTval: 0xf, out: 0x2700000f
sh $t0, 0($t1) :: RTval: 0x1, out: 0x27000001
sh $t0, 0($t1) :: RTval: 0x1, out: 0x27000001
sh $t0, 0($t1) :: RTval: 0x35, out: 0x27000035
sh $t0, 0($t1) :: RTval: 0x35, out: 0x27000035
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff
sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffff
sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0x343fffff
sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0xffff
sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0x353dffff
sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x5927
sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x3a365927
sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0x4f4effff
sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x46450000
sh $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
sh $t0, 51($t1) :: RTval: 0x28f, out: 0x464d028f
MEM1:
0xffff0035, 0xffffff59, 0xff00ffff, 0xff
0x0, 0x0, 0x0, 0xff000000
0xff0000ff, 0xff, 0x592700, 0xff000000
0x8f0000ff, 0x2, 0x0, 0x0
MEM:
0xffff0035, 0xffffff59, 0xff00ffff, 0xffffffff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0xff2d2d2a
0xff343fff, 0x3e353dff, 0x3659273b, 0xff373b3a
0x8f0000ff, 0x4e464d02, 0x474d474c, 0x4a484a4c
sw
sw $t0, 1($t1) :: RTval: 0x0, out: 0x0
sw $t0, 1($t1) :: RTval: 0x0, out: 0x0
sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0x8000
sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0xffff8000
sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
MEM1:
0xffff0035, 0xffffffff, 0xffffffff, 0xff000080
0x7fffff, 0x0, 0x0, 0xff000000
0xffffff, 0xffffff00, 0xffffff, 0x800000
0x8f592700, 0x2, 0x0, 0x0
MEM:
0xffff0035, 0xffffffff, 0xffffffff, 0xffffff80
0x237fffff, 0x242c2b2b, 0x252a2e2b, 0xff2d2d2a
0x3fffffff, 0xffffff3c, 0xffffff, 0x3b800000
0x8f592745, 0x4e000002, 0x474d474c, 0x4a484a4c

10
none/tests/mips32/MIPS32int.c
View File

@ -143,6 +143,7 @@ int main(int argc, char **argv)
TESTINST1("add $t0, $t1, $t2", 0, 0x80000000, t0, t1, t2);
TESTINST1("add $t0, $t1, $t2", 0x7fffffff, 0x80000000, t0, t1, t2);
#if (__mips_isa_rev < 6)
printf("ADDI\n");
TESTINST2("addi $t0, $t1, 0", 0, 0, t0, t1);
TESTINST2("addi $t0, $t1, 1", 0, 1, t0, t1);
@ -153,6 +154,7 @@ int main(int argc, char **argv)
TESTINST2("addi $t0, $t1, 0", 0x80000000, 0, t0, t1);
TESTINST2("addi $t0, $t1, 0", -1, 0, t0, t1);
TESTINST2("addi $t0, $t1, 0", 0x80000000, 0, t0, t1);
#endif
printf("ADDIU\n");
TESTINST2("addiu $t0, $t1, 0", 0, 0, t0, t1);
@ -234,6 +236,7 @@ int main(int argc, char **argv)
TESTINST3("clz $t0, $t1", 0x10, t0, t1);
TESTINST3("clz $t0, $t1", 0xffffffff, t0, t1);
#if (__mips_isa_rev < 6)
printf("DIV\n");
TESTINST3a("div $t0, $t1", 0x6, 0x2, t0, t1);
TESTINST3a("div $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1);
@ -248,6 +251,7 @@ int main(int argc, char **argv)
TESTINST3a("divu $t0, $t1", 0x1, 0xffffffff, t0, t1);
TESTINST3a("divu $t0, $t1", 0x2, 0x6, t0, t1);
TESTINST3a("divu $t0, $t1", 0x0, 0x2, t0, t1);
#endif
#if (__mips==32) && (__mips_isa_rev>=2)
printf("EXT\n");
@ -797,6 +801,7 @@ int main(int argc, char **argv)
TESTINSN5LOAD("lw $t0, 34($t1)", 0, 34, t0);
TESTINSN5LOAD("lw $t0, 38($t1)", 0, 38, t0);
#if (__mips_isa_rev < 6)
printf("LWL\n");
TESTINSN5LOAD("lwl $t0, 3($t1)", 0, 3, t0);
TESTINSN5LOAD("lwl $t0, 6($t1)", 0, 6, t0);
@ -959,6 +964,7 @@ int main(int argc, char **argv)
TESTINST3a("msubu $t0, $t1", 0xffffffff, 0xffffffff, t0, t1);
TESTINST3a("msubu $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1);
TESTINST3a("msubu $t0, $t1", 0x0000ffff, 0x0000ffff, t0, t1);
#endif
printf("MUL\n");
TESTINST1("mul $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
@ -993,6 +999,7 @@ int main(int argc, char **argv)
TESTINST1("mul $t0, $t1, $t2", 0x7fffffff, 0x7fffffff, t0, t1, t2);
TESTINST1("mul $t0, $t1, $t2", 0x0000ffff, 0x0000ffff, t0, t1, t2);
#if (__mips_isa_rev < 6)
printf("MULT\n");
TESTINST3a("mult $t0, $t1", 0x31415927, 0xffffffff, t0, t1);
TESTINST3a("mult $t0, $t1", 0x31415927, 0xee00ee00, t0, t1);
@ -1058,6 +1065,7 @@ int main(int argc, char **argv)
TESTINST3a("multu $t0, $t1", 0xffffffff, 0xffffffff, t0, t1);
TESTINST3a("multu $t0, $t1", 0x7fffffff, 0x7fffffff, t0, t1);
TESTINST3a("multu $t0, $t1", 0x0000ffff, 0x0000ffff, t0, t1);
#endif
printf("NOR\n");
TESTINST1("nor $t0, $t1, $t2", 0x31415927, 0xffffffff, t0, t1, t2);
@ -1763,6 +1771,7 @@ int main(int argc, char **argv)
TESTINST2("xori $t0, $t1, 0x7fff", 0x7fffffff, 0x7fff, t0, t1);
TESTINST2("xori $t0, $t1, 0x0000", 0x0000ffff, 0x0000, t0, t1);
#if (__mips_isa_rev < 6)
printf("MFHI MFLO\n");
TESTINSN_HILO(0x31415927);
TESTINSN_HILO(0);
@ -1774,6 +1783,7 @@ int main(int argc, char **argv)
TESTINSN_HILO(0x7fff);
TESTINSN_HILO(0x0dd0);
TESTINSN_HILO(0xff00);
#endif
return 0;
}

1325
none/tests/mips32/MIPS32int.stdout.exp-mips32r6-BE Normal file
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File diff suppressed because it is too large Load Diff

1325
none/tests/mips32/MIPS32int.stdout.exp-mips32r6-LE Normal file
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File diff suppressed because it is too large Load Diff

2903
none/tests/mips32/MIPS32r6int.c Normal file
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File diff suppressed because it is too large Load Diff

0
none/tests/mips32/MIPS32r6int.stderr.exp Normal file
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2801
none/tests/mips32/MIPS32r6int.stdout.exp Normal file
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File diff suppressed because it is too large Load Diff

3
none/tests/mips32/MIPS32r6int.vgtest Normal file
View File

@ -0,0 +1,3 @@
prereq: (../../../tests/mips_features mipsr6)
prog: MIPS32r6int
vgopts: -q

24
none/tests/mips32/Makefile.am
View File

@ -5,22 +5,28 @@ dist_noinst_SCRIPTS = filter_stderr
EXTRA_DIST = \
block_size.stdout.exp block_size.stderr.exp block_size.vgtest \
branch_pc.stdout.exp branch_pc.stderr.exp branch_pc.vgtest \
branches.stdout.exp branches.stderr.exp branches.vgtest \
branches.stdout.exp-r6 \
branches_r6.stdout.exp branches_r6.stderr.exp branches_r6.vgtest \
bug320057-mips32.stdout.exp bug320057-mips32.stderr.exp \
bug320057-mips32.vgtest \
change_fp_mode.stdout.exp change_fp_mode.stdout.exp-fpu32 \
change_fp_mode.stderr.exp change_fp_mode.vgtest \
change_fp_mode.stdout.exp-r6 \
FPUarithmetic.stdout.exp FPUarithmetic.stdout.exp-mips32 \
FPUarithmetic.stderr.exp FPUarithmetic.vgtest \
fpu_branches.stdout.exp fpu_branches.stderr.exp fpu_branches.vgtest \
LoadStore.stdout.exp LoadStore.stdout.exp-BE LoadStore.stderr.exp \
LoadStore.vgtest \
LoadStore.vgtest LoadStore.stdout.exp-r6-LE LoadStore.stdout.exp-r6-BE \
LoadStore1.stdout.exp LoadStore1.stdout.exp-LE LoadStore1.stderr.exp \
LoadStore1.vgtest \
LoadStore1.vgtest LoadStore1.stdout.exp-r6-LE LoadStore1.stdout.exp-r6-BE\
MemCpyTest.stdout.exp MemCpyTest.stderr.exp MemCpyTest.vgtest \
MIPS32int.stdout.exp-mips32-BE MIPS32int.stdout.exp-mips32r2-BE \
MIPS32int.stdout.exp-mips32-LE MIPS32int.stdout.exp-mips32r2-LE \
MIPS32int.stderr.exp MIPS32int.vgtest \
MIPS32int.stdout.exp-mips32r6-LE MIPS32int.stdout.exp-mips32r6-BE \
MIPS32r6int.stdout.exp MIPS32r6int.stderr.exp MIPS32r6int.vgtest \
mips32_dsp.stdout.exp-LE mips32_dsp.stdout.exp-BE \
mips32_dsp.stderr.exp mips32_dsp.vgtest \
mips32_dspr2.stdout.exp mips32_dspr2.stderr.exp \
@ -28,6 +34,9 @@ EXTRA_DIST = \
MoveIns.stdout.exp MoveIns.stdout.exp-BE \
MoveIns.stdout.exp-mips32r2-BE MoveIns.stdout.exp-mips32r2-LE \
MoveIns.stderr.exp MoveIns.vgtest \
MoveIns.stdout.exp-mips32r6-BE MoveIns.stdout.exp-mips32r6-LE \
pc_instructions_r6.stdout.exp pc_instructions_r6.stderr.exp \
pc_instructions_r6.vgtest \
msa_arithmetic.stderr.exp msa_arithmetic.stdout.exp msa_arithmetic.vgtest \
msa_comparison.stderr.exp msa_comparison.stdout.exp msa_comparison.vgtest \
msa_data_transfer.stderr.exp msa_data_transfer.stdout.exp \
@ -39,6 +48,7 @@ EXTRA_DIST = \
round_fpu64.stdout.exp round_fpu64.stdout.exp-fpu32 \
round_fpu64.stderr.exp round_fpu64.vgtest \
round.stdout.exp round.stderr.exp round.vgtest \
fp_r6.stdout.exp fp_r6.stderr.exp fp_r6.vgtest \
SignalException.stderr.exp SignalException.vgtest \
test_fcsr.stdout.exp test_fcsr.stderr.exp test_fcsr.vgtest \
test_math.stdout.exp test_math.stderr.exp test_math.vgtest \
@ -54,12 +64,15 @@ check_PROGRAMS = \
allexec \
block_size \
branches \
branch_pc \
branches_r6 \
change_fp_mode \
FPUarithmetic \
LoadStore \
LoadStore1 \
MemCpyTest \
MIPS32int \
MIPS32r6int \
MoveIns \
round \
vfp \
@ -67,6 +80,13 @@ check_PROGRAMS = \
bug320057-mips32 \
mips32_dsp \
mips32_dspr2 \
unaligned_load_store \
pc_instructions_r6 \
test_fcsr \
test_math \
round_fpu64 \
fp_r6 \
fpu_branches \
msa_arithmetic \
msa_comparison \
msa_data_transfer \

2
none/tests/mips32/MoveIns.c
View File

@ -424,6 +424,7 @@ int main()
TESTINSNMOVE1d("mov.d $f24, $f26", 56, f24, f26);
TESTINSNMOVE1d("mov.d $f24, $f26", 64, f24, f26);
#if (__mips_isa_rev < 6)
printf("MOVF\n");
TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0, 0xffffffff, t0, t1, 1);
TESTINSNMOVE2("movf $t0, $t1, $fcc0", 0xffffffff, 0xffffffff, t0, t1, 0);
@ -660,6 +661,7 @@ int main()
TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 52, 0xffffffff, f0, f2, t3);
TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 56, 0x80000000, f0, f2, t3);
TESTINSNMOVEN1s("movz.d $f0, $f2, $t3", 60, 0x7fffffff, f0, f2, t3);
#endif
return 0;
}

146
none/tests/mips32/MoveIns.stdout.exp-mips32r6-BE Normal file
View File

@ -0,0 +1,146 @@
MFC1
mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
mfc1 $v1, $f8 :: fs -nan, rt 0xffffffff
mfc1 $s0, $f9 :: fs -nan, rt 0xffffffff
mfc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
mfc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
mfc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
mfc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
mfc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
mfc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
mfc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
mfc1 $a0, $f17 :: fs 4.676074, rt 0x4095a266
mfc1 $a1, $f18 :: fs 272008302207532160516096.000000, rt 0x66666666
mfc1 $a2, $f19 :: fs -1.875000, rt 0xbff00000
mfc1 $a3, $f20 :: fs 0.000000, rt 0x0
mfc1 $v0, $f21 :: fs 1.875000, rt 0x3ff00000
mfc1 $v1, $f22 :: fs 0.000000, rt 0x0
mfc1 $t8, $f23 :: fs 0.000000, rt 0x252a2e2b
mfc1 $t9, $f24 :: fs 0.000000, rt 0x262d2d2a
mfc1 $t1, $f25 :: fs -nan, rt 0xffffffff
mfc1 $t2, $f26 :: fs -nan, rt 0xffffffff
MTC1
mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
mtc1 $v1, $f8 :: fs -nan, rt 0xffffffff
mtc1 $s0, $f9 :: fs -nan, rt 0xffffffff
mtc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
mtc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
mtc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
mtc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
mtc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
mtc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
mtc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
mtc1 $a0, $f17 :: fs -0.000000, rt 0xa2666666
mtc1 $a1, $f18 :: fs 272421228250166506553344.000000, rt 0x6666bff0
mtc1 $a2, $f19 :: fs 0.000000, rt 0x0
mtc1 $a3, $f20 :: fs 0.000000, rt 0x3ff0
mtc1 $v0, $f21 :: fs 0.000000, rt 0x0
mtc1 $v1, $f22 :: fs 0.000000, rt 0x252a
mtc1 $t8, $f23 :: fs 0.000000, rt 0x2e2b262d
mtc1 $t9, $f24 :: fs 0.000000, rt 0x2d2affff
mtc1 $t1, $f25 :: fs -nan, rt 0xffffffff
mtc1 $t2, $f26 :: fs -nan, rt 0xffff41d2
MFHC1
mfhc1 $t1, $f0 :: rt 0x12345678
mfhc1 $t2, $f2 :: rt 0x66785bd6
mfhc1 $t3, $f4 :: rt 0xbff550ff
mfhc1 $v0, $f6 :: rt 0x47892
mfhc1 $v1, $f8 :: rt 0x3ff00012
mfhc1 $a0, $f10 :: rt 0x123654
mfhc1 $a1, $f12 :: rt 0x252a2e2b
mfhc1 $a2, $f14 :: rt 0x26852147
mfhc1 $a3, $f16 :: rt 0x12345678
mfhc1 $s0, $f18 :: rt 0x66785bd6
mfhc1 $s1, $f20 :: rt 0x789651ff
mfhc1 $s2, $f22 :: rt 0xff23f4
mfhc1 $s3, $f24 :: rt 0x3ff00012
mfhc1 $s4, $f26 :: rt 0xaabbcdfe
mfhc1 $s5, $f28 :: rt 0xa1b2b2a1
mfhc1 $s6, $f30 :: rt 0x25698741
MTHC1
mthc1 $t2, $f0 :: out: 4095a26687654321
mthc1 $t3, $f2 :: out: 6666666668466667
mthc1 $v0, $f4 :: out: bff0000007788000
mthc1 $v1, $f6 :: out: 36500000
mthc1 $a0, $f8 :: out: 3ff0000056789600
mthc1 $a1, $f10 :: out: 78000000
mthc1 $a2, $f12 :: out: 252a2e2b252a2e2b
mthc1 $a3, $f14 :: out: 262d2d2a962d2d2a
mthc1 $s0, $f16 :: out: ffffffff87654321
mthc1 $s1, $f18 :: out: ffffffff68466667
mthc1 $s2, $f20 :: out: 41d2658007788055
mthc1 $s3, $f22 :: out: b487e5c9f1f5f6f8
mthc1 $s4, $f24 :: out: 4202658056789600
mthc1 $s5, $f26 :: out: b750e388efcd1256
mthc1 $s6, $f28 :: out: 3e45798ea3a5a6aa
mthc1 $s7, $f30 :: out: e2308c3a23654786
MOV.S
mov.s $f0, $f0 :: fs 0.000000, rt 0x0
mov.s $f0, $f1 :: fs 456.248962, rt 0x43e41fde
mov.s $f1, $f2 :: fs 3.000000, rt 0x40400000
mov.s $f2, $f3 :: fs -1.000000, rt 0xbf800000
mov.s $f3, $f4 :: fs 1384.599976, rt 0x44ad1333
mov.s $f4, $f5 :: fs -7.294568, rt 0xc0e96d19
mov.s $f5, $f6 :: fs 1000000000.000000, rt 0x4e6e6b28
mov.s $f6, $f7 :: fs -5786.470215, rt 0xc5b4d3c3
mov.s $f7, $f8 :: fs 1752.000000, rt 0x44db0000
mov.s $f8, $f9 :: fs 0.002457, rt 0x3b210e02
mov.s $f9, $f10 :: fs 0.000000, rt 0x322bcc77
mov.s $f10, $f11 :: fs -248562.765625, rt 0xc872bcb1
mov.s $f11, $f12 :: fs -45786.476562, rt 0xc732da7a
mov.s $f12, $f13 :: fs 456.248962, rt 0x43e41fde
mov.s $f13, $f14 :: fs 34.000462, rt 0x42080079
mov.s $f14, $f15 :: fs 45786.476562, rt 0x4732da7a
mov.s $f15, $f16 :: fs 1752065.000000, rt 0x49d5e008
mov.s $f16, $f17 :: fs 0.000000, rt 0x0
mov.s $f17, $f18 :: fs 456.248962, rt 0x43e41fde
mov.s $f18, $f19 :: fs 3.000000, rt 0x40400000
mov.s $f19, $f20 :: fs -1.000000, rt 0xbf800000
mov.s $f20, $f21 :: fs 1384.599976, rt 0x44ad1333
mov.s $f21, $f22 :: fs -7.294568, rt 0xc0e96d19
mov.s $f22, $f23 :: fs 1000000000.000000, rt 0x4e6e6b28
mov.s $f23, $f24 :: fs -5786.470215, rt 0xc5b4d3c3
mov.s $f24, $f25 :: fs 1752.000000, rt 0x44db0000
mov.s $f25, $f26 :: fs 0.002457, rt 0x3b210e02
MOV.D
mov.d $f0, $f0 ::fs 0.000000, rt 0x43e41fde
mov.d $f0, $f0 ::fs 32.000023, rt 0xbf800000
mov.d $f0, $f2 ::fs 68651422688883217793024.000000, rt 0xc0e96d19
mov.d $f2, $f4 ::fs 6560668703763947508025308754622564314214011401697745896073690307624960.000000, rt 0xc5b4d3c3
mov.d $f2, $f4 ::fs 510015646723392374046720.000000, rt 0x3b210e02
mov.d $f4, $f6 ::fs 0.000000, rt 0xc872bcb1
mov.d $f4, $f6 ::fs -97892595594330935155564225983676416.000000, rt 0x43e41fde
mov.d $f6, $f8 ::fs 12885895398.356678, rt 0x4732da7a
mov.d $f6, $f8 ::fs 499539571012599806217935122808662584365932347392.000000, rt 0x42d60000
mov.d $f8, $f10 ::fs 0.000000, rt 0x43e41fde
mov.d $f8, $f10 ::fs 32.000023, rt 0xbf800000
mov.d $f10, $f12 ::fs 68651422688883217793024.000000, rt 0xc0e96d19
mov.d $f10, $f12 ::fs 6560668703763947508025308754622564314214011401697745896073690307624960.000000, rt 0xc5b4d3c3
mov.d $f12, $f14 ::fs 510015646723392374046720.000000, rt 0x3b210e02
mov.d $f12, $f14 ::fs 0.000000, rt 0xc872bcb1
mov.d $f14, $f16 ::fs -97892595594330935155564225983676416.000000, rt 0x43e41fde
mov.d $f14, $f16 ::fs 12885895398.356678, rt 0x4732da7a
mov.d $f16, $f18 ::fs 499539571012599806217935122808662584365932347392.000000, rt 0x42d60000
mov.d $f16, $f18 ::fs 0.000000, rt 0x43e41fde
mov.d $f18, $f20 ::fs 32.000023, rt 0xbf800000
mov.d $f18, $f20 ::fs 68651422688883217793024.000000, rt 0xc0e96d19
mov.d $f20, $f22 ::fs 6560668703763947508025308754622564314214011401697745896073690307624960.000000, rt 0xc5b4d3c3
mov.d $f20, $f22 ::fs 510015646723392374046720.000000, rt 0x3b210e02
mov.d $f22, $f24 ::fs 0.000000, rt 0xc872bcb1
mov.d $f22, $f24 ::fs -97892595594330935155564225983676416.000000, rt 0x43e41fde
mov.d $f24, $f26 ::fs 12885895398.356678, rt 0x4732da7a
mov.d $f24, $f26 ::fs 499539571012599806217935122808662584365932347392.000000, rt 0x42d60000

146
none/tests/mips32/MoveIns.stdout.exp-mips32r6-LE Normal file
View File

@ -0,0 +1,146 @@
MFC1
mfc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
mfc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
mfc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
mfc1 $t4, $f3 :: fs 0.000000, rt 0x0
mfc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
mfc1 $t6, $f5 :: fs 0.000000, rt 0x0
mfc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
mfc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
mfc1 $v1, $f8 :: fs -nan, rt 0xffffffff
mfc1 $s0, $f9 :: fs -nan, rt 0xffffffff
mfc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
mfc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
mfc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
mfc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
mfc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
mfc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
mfc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
mfc1 $a0, $f17 :: fs 4.676074, rt 0x4095a266
mfc1 $a1, $f18 :: fs 272008302207532160516096.000000, rt 0x66666666
mfc1 $a2, $f19 :: fs -1.875000, rt 0xbff00000
mfc1 $a3, $f20 :: fs 0.000000, rt 0x0
mfc1 $v0, $f21 :: fs 1.875000, rt 0x3ff00000
mfc1 $v1, $f22 :: fs 0.000000, rt 0x0
mfc1 $t8, $f23 :: fs 0.000000, rt 0x252a2e2b
mfc1 $t9, $f24 :: fs 0.000000, rt 0x262d2d2a
mfc1 $t1, $f25 :: fs -nan, rt 0xffffffff
mfc1 $t2, $f26 :: fs -nan, rt 0xffffffff
MTC1
mtc1 $t1, $f0 :: fs 4.676074, rt 0x4095a266
mtc1 $t2, $f1 :: fs 272008302207532160516096.000000, rt 0x66666666
mtc1 $t3, $f2 :: fs -1.875000, rt 0xbff00000
mtc1 $t4, $f3 :: fs 0.000000, rt 0x0
mtc1 $t5, $f4 :: fs 1.875000, rt 0x3ff00000
mtc1 $t6, $f5 :: fs 0.000000, rt 0x0
mtc1 $t7, $f6 :: fs 0.000000, rt 0x252a2e2b
mtc1 $v0, $f7 :: fs 0.000000, rt 0x262d2d2a
mtc1 $v1, $f8 :: fs -nan, rt 0xffffffff
mtc1 $s0, $f9 :: fs -nan, rt 0xffffffff
mtc1 $s1, $f10 :: fs 26.299561, rt 0x41d26580
mtc1 $s2, $f11 :: fs -0.000000, rt 0xb487e5c9
mtc1 $s3, $f12 :: fs 32.599121, rt 0x42026580
mtc1 $s4, $f13 :: fs -0.000012, rt 0xb750e388
mtc1 $s5, $f14 :: fs 0.192847, rt 0x3e45798e
mtc1 $s6, $f15 :: fs -814182836421710053376.000000, rt 0xe2308c3a
mtc1 $s7, $f16 :: fs 1.496914, rt 0x3fbf9add
mtc1 $a0, $f17 :: fs 271833904815561865428992.000000, rt 0x66664095
mtc1 $a1, $f18 :: fs 0.000000, rt 0x6666
mtc1 $a2, $f19 :: fs 0.000000, rt 0xbff0
mtc1 $a3, $f20 :: fs 0.000000, rt 0x0
mtc1 $v0, $f21 :: fs 0.000000, rt 0x3ff0
mtc1 $v1, $f22 :: fs 0.000000, rt 0x2e2b0000
mtc1 $t8, $f23 :: fs 0.000000, rt 0x2d2a252a
mtc1 $t9, $f24 :: fs -nan, rt 0xffff262d
mtc1 $t1, $f25 :: fs -nan, rt 0xffffffff
mtc1 $t2, $f26 :: fs 76148150529073774329856.000000, rt 0x6580ffff
MFHC1
mfhc1 $t1, $f0 :: rt 0x12345678
mfhc1 $t2, $f2 :: rt 0x66785bd6
mfhc1 $t3, $f4 :: rt 0xbff550ff
mfhc1 $v0, $f6 :: rt 0x47892
mfhc1 $v1, $f8 :: rt 0x3ff00012
mfhc1 $a0, $f10 :: rt 0x123654
mfhc1 $a1, $f12 :: rt 0x252a2e2b
mfhc1 $a2, $f14 :: rt 0x26852147
mfhc1 $a3, $f16 :: rt 0x12345678
mfhc1 $s0, $f18 :: rt 0x66785bd6
mfhc1 $s1, $f20 :: rt 0x789651ff
mfhc1 $s2, $f22 :: rt 0xff23f4
mfhc1 $s3, $f24 :: rt 0x3ff00012
mfhc1 $s4, $f26 :: rt 0xaabbcdfe
mfhc1 $s5, $f28 :: rt 0xa1b2b2a1
mfhc1 $s6, $f30 :: rt 0x25698741
MTHC1
mthc1 $t2, $f0 :: out: 4095a26687654321
mthc1 $t3, $f2 :: out: 6666666668466667
mthc1 $v0, $f4 :: out: bff0000007788000
mthc1 $v1, $f6 :: out: 36500000
mthc1 $a0, $f8 :: out: 3ff0000056789600
mthc1 $a1, $f10 :: out: 78000000
mthc1 $a2, $f12 :: out: 252a2e2b252a2e2b
mthc1 $a3, $f14 :: out: 262d2d2a962d2d2a
mthc1 $s0, $f16 :: out: ffffffff87654321
mthc1 $s1, $f18 :: out: ffffffff68466667
mthc1 $s2, $f20 :: out: 41d2658007788055
mthc1 $s3, $f22 :: out: b487e5c9f1f5f6f8
mthc1 $s4, $f24 :: out: 4202658056789600
mthc1 $s5, $f26 :: out: b750e388efcd1256
mthc1 $s6, $f28 :: out: 3e45798ea3a5a6aa
mthc1 $s7, $f30 :: out: e2308c3a23654786
MOV.S
mov.s $f0, $f0 :: fs 0.000000, rt 0x0
mov.s $f0, $f1 :: fs 456.248962, rt 0x43e41fde
mov.s $f1, $f2 :: fs 3.000000, rt 0x40400000
mov.s $f2, $f3 :: fs -1.000000, rt 0xbf800000
mov.s $f3, $f4 :: fs 1384.599976, rt 0x44ad1333
mov.s $f4, $f5 :: fs -7.294568, rt 0xc0e96d19
mov.s $f5, $f6 :: fs 1000000000.000000, rt 0x4e6e6b28
mov.s $f6, $f7 :: fs -5786.470215, rt 0xc5b4d3c3
mov.s $f7, $f8 :: fs 1752.000000, rt 0x44db0000
mov.s $f8, $f9 :: fs 0.002457, rt 0x3b210e02
mov.s $f9, $f10 :: fs 0.000000, rt 0x322bcc77
mov.s $f10, $f11 :: fs -248562.765625, rt 0xc872bcb1
mov.s $f11, $f12 :: fs -45786.476562, rt 0xc732da7a
mov.s $f12, $f13 :: fs 456.248962, rt 0x43e41fde
mov.s $f13, $f14 :: fs 34.000462, rt 0x42080079
mov.s $f14, $f15 :: fs 45786.476562, rt 0x4732da7a
mov.s $f15, $f16 :: fs 1752065.000000, rt 0x49d5e008
mov.s $f16, $f17 :: fs 0.000000, rt 0x0
mov.s $f17, $f18 :: fs 456.248962, rt 0x43e41fde
mov.s $f18, $f19 :: fs 3.000000, rt 0x40400000
mov.s $f19, $f20 :: fs -1.000000, rt 0xbf800000
mov.s $f20, $f21 :: fs 1384.599976, rt 0x44ad1333
mov.s $f21, $f22 :: fs -7.294568, rt 0xc0e96d19
mov.s $f22, $f23 :: fs 1000000000.000000, rt 0x4e6e6b28
mov.s $f23, $f24 :: fs -5786.470215, rt 0xc5b4d3c3
mov.s $f24, $f25 :: fs 1752.000000, rt 0x44db0000
mov.s $f25, $f26 :: fs 0.002457, rt 0x3b210e02
MOV.D
mov.d $f0, $f0 ::fs 11600973572943642624.000000, rt 0x0
mov.d $f0, $f0 ::fs -0.007813, rt 0x40400000
mov.d $f0, $f2 ::fs -52072.789633, rt 0x44ad1333
mov.d $f2, $f4 ::fs -6445705852632282607665545216.000000, rt 0x4e6e6b28
mov.d $f2, $f4 ::fs 0.000000, rt 0x44db0000
mov.d $f4, $f6 ::fs -102014360350703794652958156923702465265664.000000, rt 0x322bcc77
mov.d $f4, $f6 ::fs 11600980417357008896.000000, rt 0xc732da7a
mov.d $f6, $f8 ::fs 97892595018733988536880335157198848.000000, rt 0x42080079
mov.d $f6, $f8 ::fs 96757042599808.125000, rt 0x49d5e008
mov.d $f8, $f10 ::fs 11600973572943642624.000000, rt 0x0
mov.d $f8, $f10 ::fs -0.007813, rt 0x40400000
mov.d $f10, $f12 ::fs -52072.789633, rt 0x44ad1333
mov.d $f10, $f12 ::fs -6445705852632282607665545216.000000, rt 0x4e6e6b28
mov.d $f12, $f14 ::fs 0.000000, rt 0x44db0000
mov.d $f12, $f14 ::fs -102014360350703794652958156923702465265664.000000, rt 0x322bcc77
mov.d $f14, $f16 ::fs 11600980417357008896.000000, rt 0xc732da7a
mov.d $f14, $f16 ::fs 97892595018733988536880335157198848.000000, rt 0x42080079
mov.d $f16, $f18 ::fs 96757042599808.125000, rt 0x49d5e008
mov.d $f16, $f18 ::fs 11600973572943642624.000000, rt 0x0
mov.d $f18, $f20 ::fs -0.007813, rt 0x40400000
mov.d $f18, $f20 ::fs -52072.789633, rt 0x44ad1333
mov.d $f20, $f22 ::fs -6445705852632282607665545216.000000, rt 0x4e6e6b28
mov.d $f20, $f22 ::fs 0.000000, rt 0x44db0000
mov.d $f22, $f24 ::fs -102014360350703794652958156923702465265664.000000, rt 0x322bcc77
mov.d $f22, $f24 ::fs 11600980417357008896.000000, rt 0xc732da7a
mov.d $f24, $f26 ::fs 97892595018733988536880335157198848.000000, rt 0x42080079
mov.d $f24, $f26 ::fs 96757042599808.125000, rt 0x49d5e008

3
none/tests/mips32/SignalException.c
View File

@ -60,7 +60,8 @@ static void test1(void)
static void test2()
{
__asm__ volatile("li $t0, 0x7fffffff\n\t"
"addi $a0, $t0, 0x7fff\n\t"
"li $a0, 0x7fff\n\t"
"add $a0, $t0, $a0\n\t"
: : : "t0", "a0", "cc", "memory");
}

90
none/tests/mips32/branch_pc.c Normal file
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@ -0,0 +1,90 @@
#include <stdio.h>
typedef union
{
double dbl;
long long bits[10];
} u_double;
u_double condition[2] = { {.bits = { 0x3FF0000000000001ULL, 0x3FF0000000000000ULL,
0x00000000ffffffffULL, 0x1234563388994400ULL,
0x0000004412369801ULL, 0x111111eeeeeee220ULL,
0xAAAAABBBBBCCCDDDULL, 0xaa55cc2266dd2200ULL }}};
const double a[] = { 0.5, 0.0, 0.8, 0.10, 0.128, 5.0, 8.15, 9.456 };
#define TEST(instruction, LID, FD, FS, FDval, condition) \
{ \
unsigned int result; \
__asm__ volatile ( \
".set noreorder" "\n\t" \
"l.d $"#FD", %1" "\n\t" \
"l.d $"#FS", %2" "\n\t" \
"move $v0, $0" "\n\t" \
instruction " $"#FD", end21"instruction#LID "\n\t" \
"addiu $v0, 3" "\n\t" \
"addiu $v0, 11" "\n\t" \
"end12"instruction#LID":" "\n\t" \
"bal r_end"instruction#LID "\n\t" \
"addiu $v0, 19" "\n\t" \
"addiu $v0, 20" "\n\t" \
"end21"instruction#LID":" "\n\t" \
instruction" $"#FS", end12"instruction#LID "\n\t" \
"addiu $v0, 7" "\n\t" \
"addiu $v0, 1" "\n\t" \
"r_end"instruction#LID ":" "\n\t" \
"move %0, $v0" "\n\t" \
: "=&r"(result) \
: "m" (FDval), "m" (condition), "r" (LID) \
: #FD, #FS, "$v0", "memory" \
); \
printf(instruction":: result: %x\n", result); \
}
int main() {
#if (__mips_isa_rev>=6)
printf("bc1eqz\n");
TEST("bc1eqz", 0, f0, f1, a[0], condition[0]);
TEST("bc1eqz", 1, f1, f2, a[0], condition[1]);
TEST("bc1eqz", 3, f2, f3, a[1], condition[1]);
TEST("bc1eqz", 4, f3, f4, a[1], condition[2]);
TEST("bc1eqz", 6, f4, f5, a[2], condition[2]);
TEST("bc1eqz", 7, f5, f6, a[2], condition[3]);
TEST("bc1eqz", 8, f6, f7, a[3], condition[3]);
TEST("bc1eqz", 9, f7, f8, a[3], condition[4]);
TEST("bc1eqz", 10, f8, f9, a[4], condition[4]);
TEST("bc1eqz", 11, f9, f10, a[4], condition[5]);
TEST("bc1eqz", 12, f10, f11, a[5], condition[5]);
TEST("bc1eqz", 13, f11, f12, a[6], condition[5]);
TEST("bc1eqz", 14, f12, f13, a[6], condition[6]);
TEST("bc1eqz", 15, f13, f14, a[6], condition[7]);
TEST("bc1eqz", 16, f14, f15, a[7], condition[7]);
TEST("bc1eqz", 17, f15, f16, a[7], condition[8]);
TEST("bc1eqz", 18, f16, f17, a[8], condition[8]);
printf("\nbc1nez\n");
TEST("bc1nez", 0, f0, f1, a[0], condition[0]);
TEST("bc1nez", 1, f1, f2, a[0], condition[1]);
TEST("bc1nez", 3, f2, f3, a[1], condition[1]);
TEST("bc1nez", 4, f3, f4, a[1], condition[2]);
TEST("bc1nez", 6, f4, f5, a[2], condition[2]);
TEST("bc1nez", 7, f5, f6, a[2], condition[3]);
TEST("bc1nez", 8, f6, f7, a[3], condition[3]);
TEST("bc1nez", 9, f7, f8, a[3], condition[4]);
TEST("bc1nez", 10, f8, f9, a[4], condition[4]);
TEST("bc1nez", 11, f9, f10, a[4], condition[5]);
TEST("bc1nez", 12, f10, f11, a[5], condition[5]);
TEST("bc1nez", 13, f11, f12, a[6], condition[5]);
TEST("bc1nez", 14, f12, f13, a[6], condition[6]);
TEST("bc1nez", 15, f13, f14, a[6], condition[7]);
TEST("bc1nez", 16, f14, f15, a[7], condition[7]);
TEST("bc1nez", 17, f15, f16, a[7], condition[8]);
TEST("bc1nez", 18, f16, f17, a[8], condition[8]);
#endif
return 0;
}

0
none/tests/mips32/branch_pc.stderr.exp Normal file
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37
none/tests/mips32/branch_pc.stdout.exp Normal file
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@ -0,0 +1,37 @@
bc1eqz
bc1eqz:: result: b
bc1eqz:: result: 1d
bc1eqz:: result: 1d
bc1eqz:: result: 1d
bc1eqz:: result: 1d
bc1eqz:: result: 1d
bc1eqz:: result: 1d
bc1eqz:: result: 1d
bc1eqz:: result: 1d
bc1eqz:: result: 1d
bc1eqz:: result: 1d
bc1eqz:: result: 21
bc1eqz:: result: 21
bc1eqz:: result: 21
bc1eqz:: result: 1d
bc1eqz:: result: 1d
bc1eqz:: result: 1d
bc1nez
bc1nez:: result: 21
bc1nez:: result: 21
bc1nez:: result: 21
bc1nez:: result: 21
bc1nez:: result: 21
bc1nez:: result: 21
bc1nez:: result: 21
bc1nez:: result: 21
bc1nez:: result: 21
bc1nez:: result: 21
bc1nez:: result: 21
bc1nez:: result: b
bc1nez:: result: b
bc1nez:: result: b
bc1nez:: result: 21
bc1nez:: result: 21
bc1nez:: result: 21

3
none/tests/mips32/branch_pc.vgtest Normal file
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@ -0,0 +1,3 @@
prereq: ../../../tests/mips_features fpu && (../../../tests/mips_features mipsr6)
prog: branch_pc
vgopts: -q

66
none/tests/mips32/branches.c
View File

@ -9,9 +9,9 @@
"move $" #RD ", %1\n\t" \
"b end"#RSval"\n\t" \
"nop\n\t" \
"addi $" #RD ", $" #RD", 5\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"end"#RSval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"move %0, $" #RD "\n\t" \
".set pop \n\t" \
: "=&r" (out) \
@ -30,10 +30,10 @@
".set noreorder \n\t" \
"move $" #RD ", %1\n\t" \
"b end12"#RSval"\n\t" \
"addi $" #RD ", $" #RD", 3\n\t" \
"addi $" #RD ", $" #RD", 5\n\t" \
"addiu $" #RD ", $" #RD", 3\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"end12"#RSval":\n\t" \
"addi $" #RD ", $" #RD", 3\n\t" \
"addiu $" #RD ", $" #RD", 3\n\t" \
"move %0, $" #RD "\n\t" \
".set pop \n\t" \
: "=&r" (out) \
@ -53,11 +53,11 @@
"move $" #RD ", %1\n\t" \
"bal end21"#RSval"\n\t" \
"nop\n\t" \
"addi $" #RD ", $" #RD", 5\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"b r_end"#RSval"\n\t" \
"nop\n\t" \
"end21"#RSval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"jr $ra\n\t" \
"r_end"#RSval":\n\t" \
"move %0, $" #RD "\n\t" \
@ -80,12 +80,12 @@
"la $t0, end31"#RSval"\n\t" \
"jal $t0\n\t" \
"nop\n\t" \
"addi $" #RD ", $" #RD", 5\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"la $t0, r_end11"#RSval"\n\t" \
"j $t0\n\t" \
"nop\n\t" \
"end31"#RSval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"jr $ra\n\t" \
"r_end11"#RSval":\n\t" \
"move %0, $" #RD "\n\t" \
@ -108,12 +108,12 @@
"la $t0, end41"#RSval"\n\t" \
"jalr $t1, $t0\n\t" \
"nop\n\t" \
"addi $" #RD ", $" #RD", 5\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"la $t0, r_end21"#RSval"\n\t" \
"j $t0\n\t" \
"nop\n\t" \
"end41"#RSval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"jr $t1\n\t" \
"r_end21"#RSval":\n\t" \
"move %0, $" #RD "\n\t" \
@ -137,9 +137,9 @@
"move $" #RD ", %3\n\t" \
instruction" $" #RS ", $" #RT ", end"instruction#RDval"\n\t" \
"nop\n\t" \
"addi $" #RD ", $" #RD", 5\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"end"instruction#RDval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"move %0, $" #RD "\n\t" \
".set pop \n\t" \
: "=&r" (out) \
@ -160,9 +160,9 @@
"move $" #RD ", %2\n\t" \
instruction" $" #RS ", end"instruction#RDval"\n\t" \
"nop\n\t" \
"addi $" #RD ", $" #RD", 5\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"end"instruction#RDval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"move %0, $" #RD "\n\t" \
".set pop \n\t" \
: "=&r" (out) \
@ -183,11 +183,11 @@
"move $" #RS ", %1\n\t" \
instruction" $" #RS ", end21"instruction#RDval"\n\t" \
"nop\n\t" \
"addi $" #RD ", $" #RD", 5\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"b r_end"instruction#RDval"\n\t" \
"nop\n\t" \
"end21"instruction#RDval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"jr $ra\n\t" \
"r_end"instruction#RDval":\n\t" \
"move %0, $" #RD "\n\t" \
@ -210,10 +210,10 @@
"move $" #RT ", %2\n\t" \
"move $" #RD ", %3\n\t" \
instruction" $" #RS ", $" #RT ", end"instruction#RDval"\n\t" \
"addi $" #RD ", $" #RD", 3\n\t" \
"addi $" #RD ", $" #RD", 5\n\t" \
"addiu $" #RD ", $" #RD", 3\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"end"instruction#RDval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"move %0, $" #RD "\n\t" \
".set pop \n\t" \
: "=&r" (out) \
@ -233,10 +233,10 @@
"move $" #RS ", %1\n\t" \
"move $" #RD ", %2\n\t" \
instruction" $" #RS ", end"instruction#RDval"\n\t" \
"addi $" #RD ", $" #RD", 3\n\t" \
"addi $" #RD ", $" #RD", 5\n\t" \
"addiu $" #RD ", $" #RD", 3\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"end"instruction#RDval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"move %0, $" #RD "\n\t" \
".set pop \n\t" \
: "=&r" (out) \
@ -256,12 +256,12 @@
"move $" #RD ", %2\n\t" \
"move $" #RS ", %1\n\t" \
instruction" $" #RS ", end21"instruction#RDval"\n\t" \
"addi $" #RD ", $" #RD", 3\n\t" \
"addi $" #RD ", $" #RD", 5\n\t" \
"addiu $" #RD ", $" #RD", 3\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"b r_end"instruction#RDval"\n\t" \
"nop\n\t" \
"end21"instruction#RDval":\n\t" \
"addi $" #RD ", $" #RD", 1\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"jr $ra\n\t" \
"r_end"instruction#RDval":\n\t" \
"move %0, $" #RD "\n\t" \
@ -276,7 +276,7 @@
int main()
{
printf("b \n");
printf("b\n");
TESTINST1(0, v0);
TESTINST1(1, v1);
TESTINST1(2, a0);
@ -302,7 +302,7 @@ int main()
TESTINST1(22, t8);
TESTINST1(23, t9);
printf("b \n");
printf("b\n");
TESTINST2(0, v0);
TESTINST2(1, v1);
TESTINST2(2, a0);
@ -328,7 +328,7 @@ int main()
TESTINST2(22, t8);
TESTINST2(23, t9);
printf("b, bal, jr \n");
printf("b, bal, jr\n");
TESTINST3(0, v0);
TESTINST3(1, v1);
TESTINST3(2, a0);
@ -480,6 +480,7 @@ int main()
TESTINST5("bltz", 14, -1, v0, t9);
TESTINST5("bltz", 15, -1, t9, t8);
#if (__mips_isa_rev < 6)
printf("BGEZAL\n");
TESTINST6("bgezal", 0, 0, v0, v1);
TESTINST6("bgezal", 1, 1, v1, a0);
@ -515,6 +516,7 @@ int main()
TESTINST6("bltzal", 13, 0xfff, s0, s1);
TESTINST6("bltzal", 14, -1, v0, t9);
TESTINST6("bltzal", 15, -1, t9, t8);
#endif
printf("BNEZ\n");
TESTINST5("bnez", 0, 0, v0, v1);
@ -534,6 +536,7 @@ int main()
TESTINST5("bnez", 14, -1, v0, t9);
TESTINST5("bnez", 15, -1, t9, t8);
#if (__mips_isa_rev < 6)
printf("beql\n");
TESTINST4l("beql", 0, 0, 1, v0, v1, a0);
TESTINST4l("beql", 1, 1, 1, v1, a0, a1);
@ -677,8 +680,9 @@ int main()
TESTINST4l("bnel", 13, 0xfff, 0xdd, s0, s1, s2);
TESTINST4l("bnel", 14, -1, 0x5, v0, t9, t8);
TESTINST4l("bnel", 15, -1, -1, t9, t8, a3);
#endif
printf("j, jal, jr \n");
printf("j, jal, jr\n");
TESTINST3j(0, v0);
TESTINST3j(1, v1);
TESTINST3j(2, a0);
@ -704,7 +708,7 @@ int main()
TESTINST3j(22, t8);
TESTINST3j(23, t9);
printf("j, jalr, jr \n");
printf("j, jalr, jr\n");
TESTINST3ja(0, v0);
TESTINST3ja(1, v1);
TESTINST3ja(2, a0);

10
none/tests/mips32/branches.stdout.exp
View File

@ -1,4 +1,4 @@
b
b
B :: 1, RSval: 0
B :: 2, RSval: 1
B :: 3, RSval: 2
@ -23,7 +23,7 @@ B :: 21, RSval: 20
B :: 22, RSval: 21
B :: 23, RSval: 22
B :: 24, RSval: 23
b
b
B :: 6, RSval: 0
B :: 7, RSval: 1
B :: 8, RSval: 2
@ -48,7 +48,7 @@ B :: 26, RSval: 20
B :: 27, RSval: 21
B :: 28, RSval: 22
B :: 29, RSval: 23
b, bal, jr
b, bal, jr
B BAL JR :: 6, RSval: 0
B BAL JR :: 7, RSval: 1
B BAL JR :: 8, RSval: 2
@ -379,7 +379,7 @@ bnel :: 18, RSval: 85, RTval: 85
bnel :: 17, RSval: 4095, RTval: 221
bnel :: 18, RSval: -1, RTval: 5
bnel :: 21, RSval: -1, RTval: -1
j, jal, jr
j, jal, jr
J JAL JR :: 6, RSval: 0
J JAL JR :: 7, RSval: 1
J JAL JR :: 8, RSval: 2
@ -404,7 +404,7 @@ J JAL JR :: 26, RSval: 20
J JAL JR :: 27, RSval: 21
J JAL JR :: 28, RSval: 22
J JAL JR :: 29, RSval: 23
j, jalr, jr
j, jalr, jr
J JALR JR :: 6, RSval: 0
J JALR JR :: 7, RSval: 1
J JALR JR :: 8, RSval: 2

261
none/tests/mips32/branches.stdout.exp-r6 Normal file
View File

@ -0,0 +1,261 @@
b
B :: 1, RSval: 0
B :: 2, RSval: 1
B :: 3, RSval: 2
B :: 4, RSval: 3
B :: 5, RSval: 4
B :: 6, RSval: 5
B :: 7, RSval: 6
B :: 8, RSval: 7
B :: 9, RSval: 8
B :: 10, RSval: 9
B :: 11, RSval: 10
B :: 12, RSval: 11
B :: 13, RSval: 12
B :: 14, RSval: 13
B :: 15, RSval: 14
B :: 16, RSval: 15
B :: 17, RSval: 16
B :: 18, RSval: 17
B :: 19, RSval: 18
B :: 20, RSval: 19
B :: 21, RSval: 20
B :: 22, RSval: 21
B :: 23, RSval: 22
B :: 24, RSval: 23
b
B :: 6, RSval: 0
B :: 7, RSval: 1
B :: 8, RSval: 2
B :: 9, RSval: 3
B :: 10, RSval: 4
B :: 11, RSval: 5
B :: 12, RSval: 6
B :: 13, RSval: 7
B :: 14, RSval: 8
B :: 15, RSval: 9
B :: 16, RSval: 10
B :: 17, RSval: 11
B :: 18, RSval: 12
B :: 19, RSval: 13
B :: 20, RSval: 14
B :: 21, RSval: 15
B :: 22, RSval: 16
B :: 23, RSval: 17
B :: 24, RSval: 18
B :: 25, RSval: 19
B :: 26, RSval: 20
B :: 27, RSval: 21
B :: 28, RSval: 22
B :: 29, RSval: 23
b, bal, jr
B BAL JR :: 6, RSval: 0
B BAL JR :: 7, RSval: 1
B BAL JR :: 8, RSval: 2
B BAL JR :: 9, RSval: 3
B BAL JR :: 10, RSval: 4
B BAL JR :: 11, RSval: 5
B BAL JR :: 12, RSval: 6
B BAL JR :: 13, RSval: 7
B BAL JR :: 14, RSval: 8
B BAL JR :: 15, RSval: 9
B BAL JR :: 16, RSval: 10
B BAL JR :: 17, RSval: 11
B BAL JR :: 18, RSval: 12
B BAL JR :: 19, RSval: 13
B BAL JR :: 20, RSval: 14
B BAL JR :: 21, RSval: 15
B BAL JR :: 22, RSval: 16
B BAL JR :: 23, RSval: 17
B BAL JR :: 24, RSval: 18
B BAL JR :: 25, RSval: 19
B BAL JR :: 26, RSval: 20
B BAL JR :: 27, RSval: 21
B BAL JR :: 28, RSval: 22
B BAL JR :: 29, RSval: 23
beq
beq :: 6, RSval: 0, RTval: 1
beq :: 2, RSval: 1, RTval: 1
beq :: 3, RSval: -1, RTval: -1
beq :: 9, RSval: -1, RTval: -2
beq :: 10, RSval: -2, RTval: -1
beq :: 6, RSval: -1, RTval: -1
beq :: 7, RSval: 5, RTval: 5
beq :: 13, RSval: -3, RTval: -4
beq :: 9, RSval: 125, RTval: 125
beq :: 10, RSval: -2147483648, RTval: -2147483648
beq :: 16, RSval: -1, RTval: -2147483648
beq :: 12, RSval: 598, RTval: 598
beq :: 13, RSval: 85, RTval: 85
beq :: 19, RSval: 4095, RTval: 221
beq :: 20, RSval: -1, RTval: 5
beq :: 16, RSval: -1, RTval: -1
bne
bne :: 1, RSval: 0, RTval: 1
bne :: 7, RSval: 1, RTval: 1
bne :: 8, RSval: -1, RTval: -1
bne :: 4, RSval: -1, RTval: -2
bne :: 5, RSval: -2, RTval: -1
bne :: 11, RSval: -1, RTval: -1
bne :: 12, RSval: 5, RTval: 5
bne :: 8, RSval: -3, RTval: -4
bne :: 14, RSval: 125, RTval: 125
bne :: 15, RSval: -2147483648, RTval: -2147483648
bne :: 11, RSval: -1, RTval: -2147483648
bne :: 17, RSval: 598, RTval: 598
bne :: 18, RSval: 85, RTval: 85
bne :: 14, RSval: 4095, RTval: 221
bne :: 15, RSval: -1, RTval: 5
bne :: 21, RSval: -1, RTval: -1
BEQZ
beqz :: 1, RSval: 0
beqz :: 7, RSval: 1
beqz :: 8, RSval: -1
beqz :: 9, RSval: -1
beqz :: 10, RSval: -2
beqz :: 11, RSval: -1
beqz :: 12, RSval: 5
beqz :: 13, RSval: -3
beqz :: 14, RSval: 125
beqz :: 15, RSval: -2147483648
beqz :: 16, RSval: -1
beqz :: 17, RSval: 598
beqz :: 18, RSval: 85
beqz :: 19, RSval: 4095
beqz :: 20, RSval: -1
beqz :: 21, RSval: -1
BGEZ
bgez :: 1, RSval: 0
bgez :: 2, RSval: 1
bgez :: 8, RSval: -1
bgez :: 9, RSval: -1
bgez :: 10, RSval: -2
bgez :: 11, RSval: -1
bgez :: 7, RSval: 5
bgez :: 13, RSval: -3
bgez :: 9, RSval: 125
bgez :: 15, RSval: -2147483648
bgez :: 16, RSval: -1
bgez :: 12, RSval: 598
bgez :: 13, RSval: 85
bgez :: 14, RSval: 4095
bgez :: 20, RSval: -1
bgez :: 21, RSval: -1
BGTZ
bgtz :: 6, RSval: 0
bgtz :: 2, RSval: 1
bgtz :: 8, RSval: -1
bgtz :: 9, RSval: -1
bgtz :: 10, RSval: -2
bgtz :: 11, RSval: -1
bgtz :: 7, RSval: 5
bgtz :: 13, RSval: -3
bgtz :: 9, RSval: 125
bgtz :: 15, RSval: -2147483648
bgtz :: 16, RSval: -1
bgtz :: 12, RSval: 598
bgtz :: 13, RSval: 85
bgtz :: 14, RSval: 4095
bgtz :: 20, RSval: -1
bgtz :: 21, RSval: -1
BLEZ
blez :: 1, RSval: 0
blez :: 7, RSval: 1
blez :: 3, RSval: -1
blez :: 4, RSval: -1
blez :: 5, RSval: -2
blez :: 6, RSval: -1
blez :: 12, RSval: 5
blez :: 8, RSval: -3
blez :: 14, RSval: 125
blez :: 10, RSval: -2147483648
blez :: 11, RSval: -1
blez :: 17, RSval: 598
blez :: 18, RSval: 85
blez :: 19, RSval: 4095
blez :: 15, RSval: -1
blez :: 16, RSval: -1
BLTZ
bltz :: 6, RSval: 0
bltz :: 7, RSval: 1
bltz :: 3, RSval: -1
bltz :: 4, RSval: -1
bltz :: 5, RSval: -2
bltz :: 6, RSval: -1
bltz :: 12, RSval: 5
bltz :: 8, RSval: -3
bltz :: 14, RSval: 125
bltz :: 10, RSval: -2147483648
bltz :: 11, RSval: -1
bltz :: 17, RSval: 598
bltz :: 18, RSval: 85
bltz :: 19, RSval: 4095
bltz :: 15, RSval: -1
bltz :: 16, RSval: -1
BNEZ
bnez :: 6, RSval: 0
bnez :: 2, RSval: 1
bnez :: 3, RSval: -1
bnez :: 4, RSval: -1
bnez :: 5, RSval: -2
bnez :: 6, RSval: -1
bnez :: 7, RSval: 5
bnez :: 8, RSval: -3
bnez :: 9, RSval: 125
bnez :: 10, RSval: -2147483648
bnez :: 11, RSval: -1
bnez :: 12, RSval: 598
bnez :: 13, RSval: 85
bnez :: 14, RSval: 4095
bnez :: 15, RSval: -1
bnez :: 16, RSval: -1
j, jal, jr
J JAL JR :: 6, RSval: 0
J JAL JR :: 7, RSval: 1
J JAL JR :: 8, RSval: 2
J JAL JR :: 9, RSval: 3
J JAL JR :: 10, RSval: 4
J JAL JR :: 11, RSval: 5
J JAL JR :: 12, RSval: 6
J JAL JR :: 13, RSval: 7
J JAL JR :: 14, RSval: 8
J JAL JR :: 15, RSval: 9
J JAL JR :: 16, RSval: 10
J JAL JR :: 17, RSval: 11
J JAL JR :: 18, RSval: 12
J JAL JR :: 19, RSval: 13
J JAL JR :: 20, RSval: 14
J JAL JR :: 21, RSval: 15
J JAL JR :: 22, RSval: 16
J JAL JR :: 23, RSval: 17
J JAL JR :: 24, RSval: 18
J JAL JR :: 25, RSval: 19
J JAL JR :: 26, RSval: 20
J JAL JR :: 27, RSval: 21
J JAL JR :: 28, RSval: 22
J JAL JR :: 29, RSval: 23
j, jalr, jr
J JALR JR :: 6, RSval: 0
J JALR JR :: 7, RSval: 1
J JALR JR :: 8, RSval: 2
J JALR JR :: 9, RSval: 3
J JALR JR :: 10, RSval: 4
J JALR JR :: 11, RSval: 5
J JALR JR :: 12, RSval: 6
J JALR JR :: 13, RSval: 7
J JALR JR :: 14, RSval: 8
J JALR JR :: 15, RSval: 9
J JALR JR :: 16, RSval: 10
J JALR JR :: 17, RSval: 11
J JALR JR :: 18, RSval: 12
J JALR JR :: 19, RSval: 13
J JALR JR :: 20, RSval: 14
J JALR JR :: 21, RSval: 15
J JALR JR :: 22, RSval: 16
J JALR JR :: 23, RSval: 17
J JALR JR :: 24, RSval: 18
J JALR JR :: 25, RSval: 19
J JALR JR :: 26, RSval: 20
J JALR JR :: 27, RSval: 21
J JALR JR :: 28, RSval: 22
J JALR JR :: 29, RSval: 23

548
none/tests/mips32/branches_r6.c Normal file
View File

@ -0,0 +1,548 @@
#include <stdio.h>
#if (__mips == 64)
#define LOAD_ADDRESS "dla"
#else
#define LOAD_ADDRESS "la"
#endif
#define TESTINST1(label, instruction,TID, RD) \
{ \
unsigned int out = 0; \
__asm__ volatile( \
".set push \n\t" \
".set noreorder \n\t" \
"bal end31"#TID"\n\t" \
"move $" #RD ", $0 \n\t" \
"end12"#TID":\n\t" \
"addiu $" #RD ", $" #RD", -1\n\t" \
"end13"#TID":\n\t" \
"addiu $" #RD ", $" #RD", -1\n\t" \
"end14"#TID":\n\t" \
"addiu $" #RD ", $" #RD", -1\n\t" \
"end15"#TID":\n\t" \
"addiu $" #RD ", $" #RD", -1\n\t" \
"end16"#TID":\n\t" \
"addiu $" #RD ", $" #RD", -1\n\t" \
"bal r_end"#TID "\n\t" \
"nop \n\t" \
"end31"#TID":\n\t" \
instruction " " label #TID "\n\t" \
"end21"#TID":\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"end22"#TID":\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"end23"#TID":\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"end24"#TID":\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"end25"#TID":\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"r_end"#TID":\n\t" \
"move %0, $" #RD "\n\t" \
".set pop \n\t" \
: "=&r" (out) \
:\
: #RD, "cc", "memory" \
); \
printf(instruction" :: %x, RSval: %x\n", \
out, TID); \
}
#define TESTINST2(instruction, RDval, RSval, RD, RS) \
{ \
unsigned int out = 0; \
__asm__ volatile( \
"move $" #RD ", %2\n\t" \
"move $" #RS ", %1\n\t" \
instruction" $" #RS ", end21"instruction#RDval"\n\t" \
"nop\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"b r_end"instruction#RDval"\n\t" \
"nop\n\t" \
"end21"instruction#RDval":\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"jr $ra\n\t" \
"r_end"instruction#RDval":\n\t" \
"move %0, $" #RD "\n\t" \
: "=&r" (out) \
: "r" (RSval), "r" (RDval) \
: #RD, #RS, "cc", "memory" \
); \
printf(instruction" :: %x, RSval: %x\n", \
out, RSval); \
}
#define TESTINST3(instruction, RDval, RSval, RD, RS) \
{ \
unsigned int out = 0; \
__asm__ volatile( \
"move $" #RS ", %1\n\t" \
"move $" #RD ", %2\n\t" \
instruction" $" #RS ", end"instruction#RDval"\n\t" \
"nop\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"end"instruction#RDval":\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"move %0, $" #RD "\n\t" \
: "=&r" (out) \
: "r" (RSval), "r" (RDval) \
: #RD, #RS, "cc", "memory" \
); \
printf(instruction" :: %x, RSval: %x\n", \
out, RSval); \
}
#define TESTINST4(instruction, RDval, RSval, RTval, RD, RS, RT) \
{ \
unsigned int out = 0; \
__asm__ volatile( \
"move $" #RS ", %1\n\t" \
"move $" #RT ", %2\n\t" \
"move $" #RD ", %3\n\t" \
instruction" $" #RS ", $" #RT ", end"instruction#RDval"\n\t" \
"nop\n\t" \
"addiu $" #RD ", $" #RD", 5\n\t" \
"end"instruction#RDval":\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"move %0, $" #RD "\n\t" \
: "=&r" (out) \
: "r" (RSval), "r" (RTval), "r" (RDval) \
: #RD, #RS, #RT, "cc", "memory" \
); \
printf(instruction" :: %x, RSval: %x, RTval: %x\n", \
out, RSval, RTval); \
}
#define TESTINST3ja(instruction, RSval, RD) \
{ \
unsigned int out = 0; \
unsigned int out1 = 0; \
unsigned int out2 = 0; \
__asm__ volatile( \
"move $" #RD ", %3\n\t" \
LOAD_ADDRESS " $t0, r_end"instruction#RSval"\n\t" \
LOAD_ADDRESS " $t1, end"instruction#RSval "\n\t" \
instruction " $t0, "#RSval"\n\t" \
"end"instruction#RSval":\n\t" \
"addiu $" #RD ", $" #RD", 100\n\t" \
"nop \n\t" \
"r_end"instruction#RSval":\n\t" \
"addiu $" #RD ", $" #RD", 1\n\t" \
"move %0, $" #RD "\n\t" \
"move %1, $t1 \n\t" \
"move %2, $ra \n\t" \
: "=&r" (out), "=&r" (out1), "=&r" (out2) \
: "r" (RSval) \
: #RD, "t0", "t1", "ra", "cc", "memory" \
); \
printf(instruction ":: %x, RSval: %x, $t1 == $ra: %x\n", \
out, RSval, (out1 == out2)); \
}
int main() {
#if (__mips_isa_rev>=6)
printf("balc\n");
TESTINST1("end12", "balc", 0, v0);
TESTINST1("end13", "balc", 1, v0);
TESTINST1("end14", "balc", 2, v0);
TESTINST1("end15", "balc", 3, v0);
TESTINST1("end16", "balc", 4, v0);
TESTINST1("end21", "balc", 5, v0);
TESTINST1("end22", "balc", 6, v0);
TESTINST1("end23", "balc", 7, v0);
TESTINST1("end24", "balc", 8, v0);
TESTINST1("end25", "balc", 9, v0);
printf("bc\n");
TESTINST1("end12", "bc", 10, v0);
TESTINST1("end13", "bc", 11, v0);
TESTINST1("end14", "bc", 12, v0);
TESTINST1("end15", "bc", 13, v0);
TESTINST1("end16", "bc", 14, v0);
TESTINST1("end21", "bc", 15, v0);
TESTINST1("end22", "bc", 16, v0);
TESTINST1("end23", "bc", 17, v0);
TESTINST1("end24", "bc", 18, v0);
TESTINST1("end25", "bc", 19, v0);
printf("bgezalc\n");
TESTINST2("bgezalc", 0, 0, v0, v1);
TESTINST2("bgezalc", 1, 1, v1, a0);
TESTINST2("bgezalc", 2, 0xffffffff, a0, a1);
TESTINST2("bgezalc", 3, 0xffffffff, a1, a2);
TESTINST2("bgezalc", 4, 0xfffffffe, a2, t0);
TESTINST2("bgezalc", 5, 0xffffffff, a3, t0);
TESTINST2("bgezalc", 6, 0x5, t0, t1);
TESTINST2("bgezalc", 7, -3, t1, t2);
TESTINST2("bgezalc", 8, 125, t2, t3);
TESTINST2("bgezalc", 9, 0x80000000, t3, 12);
TESTINST2("bgezalc", 10, 0xffffffff, 12, 13);
TESTINST2("bgezalc", 11, 0x256, 13, 14);
TESTINST2("bgezalc", 12, 0x55, 14, 15);
TESTINST2("bgezalc", 13, 0xfff, s0, s1);
TESTINST2("bgezalc", 14, -1, v0, t9);
TESTINST2("bgezalc", 15, -1, t9, t8);
printf("bgtzalc\n");
TESTINST2("bgtzalc", 0, 0, v0, v1);
TESTINST2("bgtzalc", 1, 1, v1, a0);
TESTINST2("bgtzalc", 2, 0xffffffff, a0, a1);
TESTINST2("bgtzalc", 3, 0xffffffff, a1, a2);
TESTINST2("bgtzalc", 4, 0xfffffffe, a2, t0);
TESTINST2("bgtzalc", 5, 0xffffffff, a3, t0);
TESTINST2("bgtzalc", 6, 0x5, t0, t1);
TESTINST2("bgtzalc", 7, -3, t1, t2);
TESTINST2("bgtzalc", 8, 125, t2, t3);
TESTINST2("bgtzalc", 9, 0x80000000, t3, 12);
TESTINST2("bgtzalc", 10, 0xffffffff, 12, 13);
TESTINST2("bgtzalc", 11, 0x256, 13, 14);
TESTINST2("bgtzalc", 12, 0x55, 14, 15);
TESTINST2("bgtzalc", 13, 0xfff, s0, s1);
TESTINST2("bgtzalc", 14, -1, v0, t9);
TESTINST2("bgtzalc", 15, -1, t9, t8);
printf("blezalc\n");
TESTINST2("blezalc", 0, 0, v0, v1);
TESTINST2("blezalc", 1, 1, v1, a0);
TESTINST2("blezalc", 2, 0xffffffff, a0, a1);
TESTINST2("blezalc", 3, 0xffffffff, a1, a2);
TESTINST2("blezalc", 4, 0xfffffffe, a2, t0);
TESTINST2("blezalc", 5, 0xffffffff, a3, t0);
TESTINST2("blezalc", 6, 0x5, t0, t1);
TESTINST2("blezalc", 7, -3, t1, t2);
TESTINST2("blezalc", 8, 125, t2, t3);
TESTINST2("blezalc", 9, 0x80000000, t3, 12);
TESTINST2("blezalc", 10, 0xffffffff, 12, 13);
TESTINST2("blezalc", 11, 0x256, 13, 14);
TESTINST2("blezalc", 12, 0x55, 14, 15);
TESTINST2("blezalc", 13, 0xfff, s0, s1);
TESTINST2("blezalc", 14, -1, v0, t9);
TESTINST2("blezalc", 15, -1, t9, t8);
printf("bltzalc\n");
TESTINST2("bltzalc", 0, 0, v0, v1);
TESTINST2("bltzalc", 1, 1, v1, a0);
TESTINST2("bltzalc", 2, 0xffffffff, a0, a1);
TESTINST2("bltzalc", 3, 0xffffffff, a1, a2);
TESTINST2("bltzalc", 4, 0xfffffffe, a2, t0);
TESTINST2("bltzalc", 5, 0xffffffff, a3, t0);
TESTINST2("bltzalc", 6, 0x5, t0, t1);
TESTINST2("bltzalc", 7, -3, t1, t2);
TESTINST2("bltzalc", 8, 125, t2, t3);
TESTINST2("bltzalc", 9, 0x80000000, t3, 12);
TESTINST2("bltzalc", 10, 0xffffffff, 12, 13);
TESTINST2("bltzalc", 11, 0x256, 13, 14);
TESTINST2("bltzalc", 12, 0x55, 14, 15);
TESTINST2("bltzalc", 13, 0xfff, s0, s1);
TESTINST2("bltzalc", 14, -1, v0, t9);
TESTINST2("bltzalc", 15, -1, t9, t8);
printf("beqzalc\n");
TESTINST2("beqzalc", 0, 0, v0, v1);
TESTINST2("beqzalc", 1, 1, v1, a0);
TESTINST2("beqzalc", 2, 0xffffffff, a0, a1);
TESTINST2("beqzalc", 3, 0xffffffff, a1, a2);
TESTINST2("beqzalc", 4, 0xfffffffe, a2, t0);
TESTINST2("beqzalc", 5, 0xffffffff, a3, t0);
TESTINST2("beqzalc", 6, 0x5, t0, t1);
TESTINST2("beqzalc", 7, -3, t1, t2);
TESTINST2("beqzalc", 8, 125, t2, t3);
TESTINST2("beqzalc", 9, 0x80000000, t3, 12);
TESTINST2("beqzalc", 10, 0xffffffff, 12, 13);
TESTINST2("beqzalc", 11, 0x256, 13, 14);
TESTINST2("beqzalc", 12, 0x55, 14, 15);
TESTINST2("beqzalc", 13, 0xfff, s0, s1);
TESTINST2("beqzalc", 14, -1, v0, t9);
TESTINST2("beqzalc", 15, -1, t9, t8);
printf("bnezalc\n");
TESTINST2("bnezalc", 0, 0, v0, v1);
TESTINST2("bnezalc", 1, 1, v1, a0);
TESTINST2("bnezalc", 2, 0xffffffff, a0, a1);
TESTINST2("bnezalc", 3, 0xffffffff, a1, a2);
TESTINST2("bnezalc", 4, 0xfffffffe, a2, t0);
TESTINST2("bnezalc", 5, 0xffffffff, a3, t0);
TESTINST2("bnezalc", 6, 0x5, t0, t1);
TESTINST2("bnezalc", 7, -3, t1, t2);
TESTINST2("bnezalc", 8, 125, t2, t3);
TESTINST2("bnezalc", 9, 0x80000000, t3, 12);
TESTINST2("bnezalc", 10, 0xffffffff, 12, 13);
TESTINST2("bnezalc", 11, 0x256, 13, 14);
TESTINST2("bnezalc", 12, 0x55, 14, 15);
TESTINST2("bnezalc", 13, 0xfff, s0, s1);
TESTINST2("bnezalc", 14, -1, v0, t9);
TESTINST2("bnezalc", 15, -1, t9, t8);
printf("blezc\n");
TESTINST3("blezc", 0, 0, v0, v1);
TESTINST3("blezc", 1, 1, v1, a0);
TESTINST3("blezc", 2, 0xffffffff, a0, a1);
TESTINST3("blezc", 3, 0xffffffff, a1, a2);
TESTINST3("blezc", 4, 0xfffffffe, a2, t0);
TESTINST3("blezc", 5, 0xffffffff, a3, t0);
TESTINST3("blezc", 6, 0x5, t0, t1);
TESTINST3("blezc", 7, -3, t1, t2);
TESTINST3("blezc", 8, 125, t2, t3);
TESTINST3("blezc", 9, 0x80000000, t3, 12);
TESTINST3("blezc", 10, 0xffffffff, 12, 13);
TESTINST3("blezc", 11, 0x256, 13, 14);
TESTINST3("blezc", 12, 0x55, 14, 15);
TESTINST3("blezc", 13, 0xfff, s0, s1);
TESTINST3("blezc", 14, -1, v0, t9);
TESTINST3("blezc", 15, -1, t9, t8);
printf("bgezc\n");
TESTINST3("bgezc", 0, 0, v0, v1);
TESTINST3("bgezc", 1, 1, v1, a0);
TESTINST3("bgezc", 2, 0xffffffff, a0, a1);
TESTINST3("bgezc", 3, 0xffffffff, a1, a2);
TESTINST3("bgezc", 4, 0xfffffffe, a2, t0);
TESTINST3("bgezc", 5, 0xffffffff, a3, t0);
TESTINST3("bgezc", 6, 0x5, t0, t1);
TESTINST3("bgezc", 7, -3, t1, t2);
TESTINST3("bgezc", 8, 125, t2, t3);
TESTINST3("bgezc", 9, 0x80000000, t3, 12);
TESTINST3("bgezc", 10, 0xffffffff, 12, 13);
TESTINST3("bgezc", 11, 0x256, 13, 14);
TESTINST3("bgezc", 12, 0x55, 14, 15);
TESTINST3("bgezc", 13, 0xfff, s0, s1);
TESTINST3("bgezc", 14, -1, v0, t9);
TESTINST3("bgezc", 15, -1, t9, t8);
printf("bgtzc\n");
TESTINST3("bgtzc", 0, 0, v0, v1);
TESTINST3("bgtzc", 1, 1, v1, a0);
TESTINST3("bgtzc", 2, 0xffffffff, a0, a1);
TESTINST3("bgtzc", 3, 0xffffffff, a1, a2);
TESTINST3("bgtzc", 4, 0xfffffffe, a2, t0);
TESTINST3("bgtzc", 5, 0xffffffff, a3, t0);
TESTINST3("bgtzc", 6, 0x5, t0, t1);
TESTINST3("bgtzc", 7, -3, t1, t2);
TESTINST3("bgtzc", 8, 125, t2, t3);
TESTINST3("bgtzc", 9, 0x80000000, t3, 12);
TESTINST3("bgtzc", 10, 0xffffffff, 12, 13);
TESTINST3("bgtzc", 11, 0x256, 13, 14);
TESTINST3("bgtzc", 12, 0x55, 14, 15);
TESTINST3("bgtzc", 13, 0xfff, s0, s1);
TESTINST3("bgtzc", 14, -1, v0, t9);
TESTINST3("bgtzc", 15, -1, t9, t8);
printf("bgec\n");
TESTINST4("bgec", 0, 0, 1, v0, v1, a0);
TESTINST4("bgec", 1, 1, 1, v1, a0, a1);
TESTINST4("bgec", 2, 0xffffffff, 0xffffffff, a0, a1, a2);
TESTINST4("bgec", 3, 0xffffffff, 0xfffffffe, a1, a2, a3);
TESTINST4("bgec", 4, 0xfffffffe, 0xffffffff, a2, t0, t1);
TESTINST4("bgec", 5, 0xffffffff, 0xffffffff, a3, t0, t1);
TESTINST4("bgec", 6, 0x5, 0x5, t0, t1, t2);
TESTINST4("bgec", 7, -3, -4, t1, t2, t3);
TESTINST4("bgec", 8, 125, 125, t2, t3, 12);
TESTINST4("bgec", 9, 0x80000000, 0x80000000, t3, 12, 13);
TESTINST4("bgec", 10, 0xffffffff, 0x80000000, 12, 13, 14);
TESTINST4("bgec", 11, 0x256, 0x256, 13, 14, 15);
TESTINST4("bgec", 12, 0x55, 0x55, 14, 15, s0);
TESTINST4("bgec", 13, 0xfff, 0xdd, s0, s1, s2);
TESTINST4("bgec", 14, -1, 0x5, v0, t9, t8);
TESTINST4("bgec", 15, -1, -1, t9, t8, a3);
printf("bltc\n");
TESTINST4("bltc", 0, 0, 1, v0, v1, a0);
TESTINST4("bltc", 1, 1, 1, v1, a0, a1);
TESTINST4("bltc", 2, 0xffffffff, 0xffffffff, a0, a1, a2);
TESTINST4("bltc", 3, 0xffffffff, 0xfffffffe, a1, a2, a3);
TESTINST4("bltc", 4, 0xfffffffe, 0xffffffff, a2, t0, t1);
TESTINST4("bltc", 5, 0xffffffff, 0xffffffff, a3, t0, t1);
TESTINST4("bltc", 6, 0x5, 0x5, t0, t1, t2);
TESTINST4("bltc", 7, -3, -4, t1, t2, t3);
TESTINST4("bltc", 8, 125, 125, t2, t3, 12);
TESTINST4("bltc", 9, 0x80000000, 0x80000000, t3, 12, 13);
TESTINST4("bltc", 10, 0xffffffff, 0x80000000, 12, 13, 14);
TESTINST4("bltc", 11, 0x256, 0x256, 13, 14, 15);
TESTINST4("bltc", 12, 0x55, 0x55, 14, 15, s0);
TESTINST4("bltc", 13, 0xfff, 0xdd, s0, s1, s2);
TESTINST4("bltc", 14, -1, 0x5, v0, t9, t8);
TESTINST4("bltc", 15, -1, -1, t9, t8, a3);
printf("bltzc\n");
TESTINST3("bltzc", 0, 0, v0, v1);
TESTINST3("bltzc", 1, 1, v1, a0);
TESTINST3("bltzc", 2, 0xffffffff, a0, a1);
TESTINST3("bltzc", 3, 0xffffffff, a1, a2);
TESTINST3("bltzc", 4, 0xfffffffe, a2, t0);
TESTINST3("bltzc", 5, 0xffffffff, a3, t0);
TESTINST3("bltzc", 6, 0x5, t0, t1);
TESTINST3("bltzc", 7, -3, t1, t2);
TESTINST3("bltzc", 8, 125, t2, t3);
TESTINST3("bltzc", 9, 0x80000000, t3, 12);
TESTINST3("bltzc", 10, 0xffffffff, 12, 13);
TESTINST3("bltzc", 11, 0x256, 13, 14);
TESTINST3("bltzc", 12, 0x55, 14, 15);
TESTINST3("bltzc", 13, 0xfff, s0, s1);
TESTINST3("bltzc", 14, -1, v0, t9);
TESTINST3("bltzc", 15, -1, t9, t8);
printf("bgeuc\n");
TESTINST4("bgeuc", 0, 0, 1, v0, v1, a0);
TESTINST4("bgeuc", 1, 1, 1, v1, a0, a1);
TESTINST4("bgeuc", 2, 0xffffffff, 0xffffffff, a0, a1, a2);
TESTINST4("bgeuc", 3, 0xffffffff, 0xfffffffe, a1, a2, a3);
TESTINST4("bgeuc", 4, 0xfffffffe, 0xffffffff, a2, t0, t1);
TESTINST4("bgeuc", 5, 0xffffffff, 0xffffffff, a3, t0, t1);
TESTINST4("bgeuc", 6, 0x5, 0x5, t0, t1, t2);
TESTINST4("bgeuc", 7, -3, -4, t1, t2, t3);
TESTINST4("bgeuc", 8, 125, 125, t2, t3, 12);
TESTINST4("bgeuc", 9, 0x80000000, 0x80000000, t3, 12, 13);
TESTINST4("bgeuc", 10, 0xffffffff, 0x80000000, 12, 13, 14);
TESTINST4("bgeuc", 11, 0x256, 0x256, 13, 14, 15);
TESTINST4("bgeuc", 12, 0x55, 0x55, 14, 15, s0);
TESTINST4("bgeuc", 13, 0xfff, 0xdd, s0, s1, s2);
TESTINST4("bgeuc", 14, -1, 0x5, v0, t9, t8);
TESTINST4("bgeuc", 15, -1, -1, t9, t8, a3);
printf("bltuc\n");
TESTINST4("bltuc", 0, 0, 1, v0, v1, a0);
TESTINST4("bltuc", 1, 1, 1, v1, a0, a1);
TESTINST4("bltuc", 2, 0xffffffff, 0xffffffff, a0, a1, a2);
TESTINST4("bltuc", 3, 0xffffffff, 0xfffffffe, a1, a2, a3);
TESTINST4("bltuc", 4, 0xfffffffe, 0xffffffff, a2, t0, t1);
TESTINST4("bltuc", 5, 0xffffffff, 0xffffffff, a3, t0, t1);
TESTINST4("bltuc", 6, 0x5, 0x5, t0, t1, t2);
TESTINST4("bltuc", 7, -3, -4, t1, t2, t3);
TESTINST4("bltuc", 8, 125, 125, t2, t3, 12);
TESTINST4("bltuc", 9, 0x80000000, 0x80000000, t3, 12, 13);
TESTINST4("bltuc", 10, 0xffffffff, 0x80000000, 12, 13, 14);
TESTINST4("bltuc", 11, 0x256, 0x256, 13, 14, 15);
TESTINST4("bltuc", 12, 0x55, 0x55, 14, 15, s0);
TESTINST4("bltuc", 13, 0xfff, 0xdd, s0, s1, s2);
TESTINST4("bltuc", 14, -1, 0x5, v0, t9, t8);
TESTINST4("bltuc", 15, -1, -1, t9, t8, a3);
printf("beqc\n");
TESTINST4("beqc", 0, 0, 1, v0, v1, a0);
TESTINST4("beqc", 1, 1, 1, v1, a0, a1);
TESTINST4("beqc", 2, 0xffffffff, 0xffffffff, a0, a1, a2);
TESTINST4("beqc", 3, 0xffffffff, 0xfffffffe, a1, a2, a3);
TESTINST4("beqc", 4, 0xfffffffe, 0xffffffff, a2, t0, t1);
TESTINST4("beqc", 5, 0xffffffff, 0xffffffff, a3, t0, t1);
TESTINST4("beqc", 6, 0x5, 0x5, t0, t1, t2);
TESTINST4("beqc", 7, -3, -4, t1, t2, t3);
TESTINST4("beqc", 8, 125, 125, t2, t3, 12);
TESTINST4("beqc", 9, 0x80000000, 0x80000000, t3, 12, 13);
TESTINST4("beqc", 10, 0xffffffff, 0x80000000, 12, 13, 14);
TESTINST4("beqc", 11, 0x256, 0x256, 13, 14, 15);
TESTINST4("beqc", 12, 0x55, 0x55, 14, 15, s0);
TESTINST4("beqc", 13, 0xfff, 0xdd, s0, s1, s2);
TESTINST4("beqc", 14, -1, 0x5, v0, t9, t8);
TESTINST4("beqc", 15, -1, -1, t9, t8, a3);
printf("bnec\n");
TESTINST4("bnec", 0, 0, 1, v0, v1, a0);
TESTINST4("bnec", 1, 1, 1, v1, a0, a1);
TESTINST4("bnec", 2, 0xffffffff, 0xffffffff, a0, a1, a2);
TESTINST4("bnec", 3, 0xffffffff, 0xfffffffe, a1, a2, a3);
TESTINST4("bnec", 4, 0xfffffffe, 0xffffffff, a2, t0, t1);
TESTINST4("bnec", 5, 0xffffffff, 0xffffffff, a3, t0, t1);
TESTINST4("bnec", 6, 0x5, 0x5, t0, t1, t2);
TESTINST4("bnec", 7, -3, -4, t1, t2, t3);
TESTINST4("bnec", 8, 125, 125, t2, t3, 12);
TESTINST4("bnec", 9, 0x80000000, 0x80000000, t3, 12, 13);
TESTINST4("bnec", 10, 0xffffffff, 0x80000000, 12, 13, 14);
TESTINST4("bnec", 11, 0x256, 0x256, 13, 14, 15);
TESTINST4("bnec", 12, 0x55, 0x55, 14, 15, s0);
TESTINST4("bnec", 13, 0xfff, 0xdd, s0, s1, s2);
TESTINST4("bnec", 14, -1, 0x5, v0, t9, t8);
TESTINST4("bnec", 15, -1, -1, t9, t8, a3);
printf("beqzc\n");
TESTINST3("beqzc", 0, 0, v0, v1);
TESTINST3("beqzc", 1, 1, v1, a0);
TESTINST3("beqzc", 2, 0xffffffff, a0, a1);
TESTINST3("beqzc", 3, 0xffffffff, a1, a2);
TESTINST3("beqzc", 4, 0xfffffffe, a2, t0);
TESTINST3("beqzc", 5, 0xffffffff, a3, t0);
TESTINST3("beqzc", 6, 0x5, t0, t1);
TESTINST3("beqzc", 7, -3, t1, t2);
TESTINST3("beqzc", 8, 125, t2, t3);
TESTINST3("beqzc", 9, 0x80000000, t3, 12);
TESTINST3("beqzc", 10, 0xffffffff, 12, 13);
TESTINST3("beqzc", 11, 0x256, 13, 14);
TESTINST3("beqzc", 12, 0x55, 14, 15);
TESTINST3("beqzc", 13, 0xfff, s0, s1);
TESTINST3("beqzc", 14, -1, v0, t9);
TESTINST3("beqzc", 15, -1, t9, t8);
printf("bnezc\n");
TESTINST3("bnezc", 0, 0, v0, v1);
TESTINST3("bnezc", 1, 1, v1, a0);
TESTINST3("bnezc", 2, 0xffffffff, a0, a1);
TESTINST3("bnezc", 3, 0xffffffff, a1, a2);
TESTINST3("bnezc", 4, 0xfffffffe, a2, t0);
TESTINST3("bnezc", 5, 0xffffffff, a3, t0);
TESTINST3("bnezc", 6, 0x5, t0, t1);
TESTINST3("bnezc", 7, -3, t1, t2);
TESTINST3("bnezc", 8, 125, t2, t3);
TESTINST3("bnezc", 9, 0x80000000, t3, 12);
TESTINST3("bnezc", 10, 0xffffffff, 12, 13);
TESTINST3("bnezc", 11, 0x256, 13, 14);
TESTINST3("bnezc", 12, 0x55, 14, 15);
TESTINST3("bnezc", 13, 0xfff, s0, s1);
TESTINST3("bnezc", 14, -1, v0, t9);
TESTINST3("bnezc", 15, -1, t9, t8);
printf("bovc\n");
TESTINST4("bovc", 0, 0, 1, v0, v1, a0);
TESTINST4("bovc", 1, 1, 1, v1, a0, a1);
TESTINST4("bovc", 2, 0xffffffff, 0xffffffff, a0, a1, a2);
TESTINST4("bovc", 3, 0xffffffff, 0xfffffffe, a1, a2, a3);
TESTINST4("bovc", 4, 0xfffffffe, 0xffffffff, a2, t0, t1);
TESTINST4("bovc", 5, 0xffffffff, 0xffffffff, a3, t0, t1);
TESTINST4("bovc", 6, 0x5, 0x5, t0, t1, t2);
TESTINST4("bovc", 7, -3, -4, t1, t2, t3);
TESTINST4("bovc", 8, 125, 125, t2, t3, 12);
TESTINST4("bovc", 9, 0x80000000, 0x80000000, t3, 12, 13);
TESTINST4("bovc", 10, 0xffffffff, 0x80000000, 12, 13, 14);
TESTINST4("bovc", 11, 0x256, 0x256, 13, 14, 15);
TESTINST4("bovc", 12, 0x55, 0x55, 14, 15, s0);
TESTINST4("bovc", 13, 0xfff, 0xdd, s0, s1, s2);
TESTINST4("bovc", 14, -1, 0x5, v0, t9, t8);
TESTINST4("bovc", 15, -1, -1, t9, t8, a3);
printf("bnvc\n");
TESTINST4("bnvc", 0, 0, 1, v0, v1, a0);
TESTINST4("bnvc", 1, 1, 1, v1, a0, a1);
TESTINST4("bnvc", 2, 0xffffffff, 0xffffffff, a0, a1, a2);
TESTINST4("bnvc", 3, 0xffffffff, 0xfffffffe, a1, a2, a3);
TESTINST4("bnvc", 4, 0xfffffffe, 0xffffffff, a2, t0, t1);
TESTINST4("bnvc", 5, 0xffffffff, 0xffffffff, a3, t0, t1);
TESTINST4("bnvc", 6, 0x5, 0x5, t0, t1, t2);
TESTINST4("bnvc", 7, -3, -4, t1, t2, t3);
TESTINST4("bnvc", 8, 125, 125, t2, t3, 12);
TESTINST4("bnvc", 9, 0x80000000, 0x80000000, t3, 12, 13);
TESTINST4("bnvc", 10, 0xffffffff, 0x80000000, 12, 13, 14);
TESTINST4("bnvc", 11, 0x256, 0x256, 13, 14, 15);
TESTINST4("bnvc", 12, 0x55, 0x55, 14, 15, s0);
TESTINST4("bnvc", 13, 0xfff, 0xdd, s0, s1, s2);
TESTINST4("bnvc", 14, -1, 0x5, v0, t9, t8);
TESTINST4("bnvc", 15, -1, -1, t9, t8, a3);
printf("jialc\n");
TESTINST3ja("jialc", 0, v0);
TESTINST3ja("jialc", 4, v0);
TESTINST3ja("jialc", 8, v0);
TESTINST3ja("jialc", 16, v0);
TESTINST3ja("jialc", 32, v0);
printf("jic\n");
TESTINST3ja("jic", 0, v0);
TESTINST3ja("jic", 4, v0);
TESTINST3ja("jic", 8, v0);
TESTINST3ja("jic", 16, v0);
TESTINST3ja("jic", 32, v0);
TESTINST3ja("jic", 64, v0);
#endif
return 0;
}

0
none/tests/mips32/branches_r6.stderr.exp Normal file
View File

374
none/tests/mips32/branches_r6.stdout.exp Normal file
View File

@ -0,0 +1,374 @@
balc
balc :: fffffffb, RSval: 0
balc :: fffffffc, RSval: 1
balc :: fffffffd, RSval: 2
balc :: fffffffe, RSval: 3
balc :: ffffffff, RSval: 4
balc :: 5, RSval: 5
balc :: 4, RSval: 6
balc :: 3, RSval: 7
balc :: 2, RSval: 8
balc :: 1, RSval: 9
bc
bc :: fffffffb, RSval: a
bc :: fffffffc, RSval: b
bc :: fffffffd, RSval: c
bc :: fffffffe, RSval: d
bc :: ffffffff, RSval: e
bc :: 5, RSval: f
bc :: 4, RSval: 10
bc :: 3, RSval: 11
bc :: 2, RSval: 12
bc :: 1, RSval: 13
bgezalc
bgezalc :: 6, RSval: 0
bgezalc :: 7, RSval: 1
bgezalc :: 7, RSval: ffffffff
bgezalc :: 8, RSval: ffffffff
bgezalc :: 9, RSval: fffffffe
bgezalc :: a, RSval: ffffffff
bgezalc :: c, RSval: 5
bgezalc :: c, RSval: fffffffd
bgezalc :: e, RSval: 7d
bgezalc :: e, RSval: 80000000
bgezalc :: f, RSval: ffffffff
bgezalc :: 11, RSval: 256
bgezalc :: 12, RSval: 55
bgezalc :: 13, RSval: fff
bgezalc :: 13, RSval: ffffffff
bgezalc :: 14, RSval: ffffffff
bgtzalc
bgtzalc :: 5, RSval: 0
bgtzalc :: 7, RSval: 1
bgtzalc :: 7, RSval: ffffffff
bgtzalc :: 8, RSval: ffffffff
bgtzalc :: 9, RSval: fffffffe
bgtzalc :: a, RSval: ffffffff
bgtzalc :: c, RSval: 5
bgtzalc :: c, RSval: fffffffd
bgtzalc :: e, RSval: 7d
bgtzalc :: e, RSval: 80000000
bgtzalc :: f, RSval: ffffffff
bgtzalc :: 11, RSval: 256
bgtzalc :: 12, RSval: 55
bgtzalc :: 13, RSval: fff
bgtzalc :: 13, RSval: ffffffff
bgtzalc :: 14, RSval: ffffffff
blezalc
blezalc :: 6, RSval: 0
blezalc :: 6, RSval: 1
blezalc :: 8, RSval: ffffffff
blezalc :: 9, RSval: ffffffff
blezalc :: a, RSval: fffffffe
blezalc :: b, RSval: ffffffff
blezalc :: b, RSval: 5
blezalc :: d, RSval: fffffffd
blezalc :: d, RSval: 7d
blezalc :: f, RSval: 80000000
blezalc :: 10, RSval: ffffffff
blezalc :: 10, RSval: 256
blezalc :: 11, RSval: 55
blezalc :: 12, RSval: fff
blezalc :: 14, RSval: ffffffff
blezalc :: 15, RSval: ffffffff
bltzalc
bltzalc :: 5, RSval: 0
bltzalc :: 6, RSval: 1
bltzalc :: 8, RSval: ffffffff
bltzalc :: 9, RSval: ffffffff
bltzalc :: a, RSval: fffffffe
bltzalc :: b, RSval: ffffffff
bltzalc :: b, RSval: 5
bltzalc :: d, RSval: fffffffd
bltzalc :: d, RSval: 7d
bltzalc :: f, RSval: 80000000
bltzalc :: 10, RSval: ffffffff
bltzalc :: 10, RSval: 256
bltzalc :: 11, RSval: 55
bltzalc :: 12, RSval: fff
bltzalc :: 14, RSval: ffffffff
bltzalc :: 15, RSval: ffffffff
beqzalc
beqzalc :: 6, RSval: 0
beqzalc :: 6, RSval: 1
beqzalc :: 7, RSval: ffffffff
beqzalc :: 8, RSval: ffffffff
beqzalc :: 9, RSval: fffffffe
beqzalc :: a, RSval: ffffffff
beqzalc :: b, RSval: 5
beqzalc :: c, RSval: fffffffd
beqzalc :: d, RSval: 7d
beqzalc :: e, RSval: 80000000
beqzalc :: f, RSval: ffffffff
beqzalc :: 10, RSval: 256
beqzalc :: 11, RSval: 55
beqzalc :: 12, RSval: fff
beqzalc :: 13, RSval: ffffffff
beqzalc :: 14, RSval: ffffffff
bnezalc
bnezalc :: 5, RSval: 0
bnezalc :: 7, RSval: 1
bnezalc :: 8, RSval: ffffffff
bnezalc :: 9, RSval: ffffffff
bnezalc :: a, RSval: fffffffe
bnezalc :: b, RSval: ffffffff
bnezalc :: c, RSval: 5
bnezalc :: d, RSval: fffffffd
bnezalc :: e, RSval: 7d
bnezalc :: f, RSval: 80000000
bnezalc :: 10, RSval: ffffffff
bnezalc :: 11, RSval: 256
bnezalc :: 12, RSval: 55
bnezalc :: 13, RSval: fff
bnezalc :: 14, RSval: ffffffff
bnezalc :: 15, RSval: ffffffff
blezc
blezc :: 1, RSval: 0
blezc :: 7, RSval: 1
blezc :: 3, RSval: ffffffff
blezc :: 4, RSval: ffffffff
blezc :: 5, RSval: fffffffe
blezc :: 6, RSval: ffffffff
blezc :: c, RSval: 5
blezc :: 8, RSval: fffffffd
blezc :: e, RSval: 7d
blezc :: a, RSval: 80000000
blezc :: b, RSval: ffffffff
blezc :: 11, RSval: 256
blezc :: 12, RSval: 55
blezc :: 13, RSval: fff
blezc :: f, RSval: ffffffff
blezc :: 10, RSval: ffffffff
bgezc
bgezc :: 1, RSval: 0
bgezc :: 2, RSval: 1
bgezc :: 8, RSval: ffffffff
bgezc :: 9, RSval: ffffffff
bgezc :: a, RSval: fffffffe
bgezc :: b, RSval: ffffffff
bgezc :: 7, RSval: 5
bgezc :: d, RSval: fffffffd
bgezc :: 9, RSval: 7d
bgezc :: f, RSval: 80000000
bgezc :: 10, RSval: ffffffff
bgezc :: c, RSval: 256
bgezc :: d, RSval: 55
bgezc :: e, RSval: fff
bgezc :: 14, RSval: ffffffff
bgezc :: 15, RSval: ffffffff
bgtzc
bgtzc :: 6, RSval: 0
bgtzc :: 2, RSval: 1
bgtzc :: 8, RSval: ffffffff
bgtzc :: 9, RSval: ffffffff
bgtzc :: a, RSval: fffffffe
bgtzc :: b, RSval: ffffffff
bgtzc :: 7, RSval: 5
bgtzc :: d, RSval: fffffffd
bgtzc :: 9, RSval: 7d
bgtzc :: f, RSval: 80000000
bgtzc :: 10, RSval: ffffffff
bgtzc :: c, RSval: 256
bgtzc :: d, RSval: 55
bgtzc :: e, RSval: fff
bgtzc :: 14, RSval: ffffffff
bgtzc :: 15, RSval: ffffffff
bgec
bgec :: 6, RSval: 0, RTval: 1
bgec :: 2, RSval: 1, RTval: 1
bgec :: 3, RSval: ffffffff, RTval: ffffffff
bgec :: 4, RSval: ffffffff, RTval: fffffffe
bgec :: a, RSval: fffffffe, RTval: ffffffff
bgec :: 6, RSval: ffffffff, RTval: ffffffff
bgec :: 7, RSval: 5, RTval: 5
bgec :: 8, RSval: fffffffd, RTval: fffffffc
bgec :: 9, RSval: 7d, RTval: 7d
bgec :: a, RSval: 80000000, RTval: 80000000
bgec :: b, RSval: ffffffff, RTval: 80000000
bgec :: c, RSval: 256, RTval: 256
bgec :: d, RSval: 55, RTval: 55
bgec :: e, RSval: fff, RTval: dd
bgec :: 14, RSval: ffffffff, RTval: 5
bgec :: 10, RSval: ffffffff, RTval: ffffffff
bltc
bltc :: 1, RSval: 0, RTval: 1
bltc :: 7, RSval: 1, RTval: 1
bltc :: 8, RSval: ffffffff, RTval: ffffffff
bltc :: 9, RSval: ffffffff, RTval: fffffffe
bltc :: 5, RSval: fffffffe, RTval: ffffffff
bltc :: b, RSval: ffffffff, RTval: ffffffff
bltc :: c, RSval: 5, RTval: 5
bltc :: d, RSval: fffffffd, RTval: fffffffc
bltc :: e, RSval: 7d, RTval: 7d
bltc :: f, RSval: 80000000, RTval: 80000000
bltc :: 10, RSval: ffffffff, RTval: 80000000
bltc :: 11, RSval: 256, RTval: 256
bltc :: 12, RSval: 55, RTval: 55
bltc :: 13, RSval: fff, RTval: dd
bltc :: f, RSval: ffffffff, RTval: 5
bltc :: 15, RSval: ffffffff, RTval: ffffffff
bltzc
bltzc :: 6, RSval: 0
bltzc :: 7, RSval: 1
bltzc :: 3, RSval: ffffffff
bltzc :: 4, RSval: ffffffff
bltzc :: 5, RSval: fffffffe
bltzc :: 6, RSval: ffffffff
bltzc :: c, RSval: 5
bltzc :: 8, RSval: fffffffd
bltzc :: e, RSval: 7d
bltzc :: a, RSval: 80000000
bltzc :: b, RSval: ffffffff
bltzc :: 11, RSval: 256
bltzc :: 12, RSval: 55
bltzc :: 13, RSval: fff
bltzc :: f, RSval: ffffffff
bltzc :: 10, RSval: ffffffff
bgeuc
bgeuc :: 6, RSval: 0, RTval: 1
bgeuc :: 2, RSval: 1, RTval: 1
bgeuc :: 3, RSval: ffffffff, RTval: ffffffff
bgeuc :: 4, RSval: ffffffff, RTval: fffffffe
bgeuc :: a, RSval: fffffffe, RTval: ffffffff
bgeuc :: 6, RSval: ffffffff, RTval: ffffffff
bgeuc :: 7, RSval: 5, RTval: 5
bgeuc :: 8, RSval: fffffffd, RTval: fffffffc
bgeuc :: 9, RSval: 7d, RTval: 7d
bgeuc :: a, RSval: 80000000, RTval: 80000000
bgeuc :: b, RSval: ffffffff, RTval: 80000000
bgeuc :: c, RSval: 256, RTval: 256
bgeuc :: d, RSval: 55, RTval: 55
bgeuc :: e, RSval: fff, RTval: dd
bgeuc :: f, RSval: ffffffff, RTval: 5
bgeuc :: 10, RSval: ffffffff, RTval: ffffffff
bltuc
bltuc :: 1, RSval: 0, RTval: 1
bltuc :: 7, RSval: 1, RTval: 1
bltuc :: 8, RSval: ffffffff, RTval: ffffffff
bltuc :: 9, RSval: ffffffff, RTval: fffffffe
bltuc :: 5, RSval: fffffffe, RTval: ffffffff
bltuc :: b, RSval: ffffffff, RTval: ffffffff
bltuc :: c, RSval: 5, RTval: 5
bltuc :: d, RSval: fffffffd, RTval: fffffffc
bltuc :: e, RSval: 7d, RTval: 7d
bltuc :: f, RSval: 80000000, RTval: 80000000
bltuc :: 10, RSval: ffffffff, RTval: 80000000
bltuc :: 11, RSval: 256, RTval: 256
bltuc :: 12, RSval: 55, RTval: 55
bltuc :: 13, RSval: fff, RTval: dd
bltuc :: 14, RSval: ffffffff, RTval: 5
bltuc :: 15, RSval: ffffffff, RTval: ffffffff
beqc
beqc :: 6, RSval: 0, RTval: 1
beqc :: 2, RSval: 1, RTval: 1
beqc :: 3, RSval: ffffffff, RTval: ffffffff
beqc :: 9, RSval: ffffffff, RTval: fffffffe
beqc :: a, RSval: fffffffe, RTval: ffffffff
beqc :: 6, RSval: ffffffff, RTval: ffffffff
beqc :: 7, RSval: 5, RTval: 5
beqc :: d, RSval: fffffffd, RTval: fffffffc
beqc :: 9, RSval: 7d, RTval: 7d
beqc :: a, RSval: 80000000, RTval: 80000000
beqc :: 10, RSval: ffffffff, RTval: 80000000
beqc :: c, RSval: 256, RTval: 256
beqc :: d, RSval: 55, RTval: 55
beqc :: 13, RSval: fff, RTval: dd
beqc :: 14, RSval: ffffffff, RTval: 5
beqc :: 10, RSval: ffffffff, RTval: ffffffff
bnec
bnec :: 1, RSval: 0, RTval: 1
bnec :: 7, RSval: 1, RTval: 1
bnec :: 8, RSval: ffffffff, RTval: ffffffff
bnec :: 4, RSval: ffffffff, RTval: fffffffe
bnec :: 5, RSval: fffffffe, RTval: ffffffff
bnec :: b, RSval: ffffffff, RTval: ffffffff
bnec :: c, RSval: 5, RTval: 5
bnec :: 8, RSval: fffffffd, RTval: fffffffc
bnec :: e, RSval: 7d, RTval: 7d
bnec :: f, RSval: 80000000, RTval: 80000000
bnec :: b, RSval: ffffffff, RTval: 80000000
bnec :: 11, RSval: 256, RTval: 256
bnec :: 12, RSval: 55, RTval: 55
bnec :: e, RSval: fff, RTval: dd
bnec :: f, RSval: ffffffff, RTval: 5
bnec :: 15, RSval: ffffffff, RTval: ffffffff
beqzc
beqzc :: 1, RSval: 0
beqzc :: 7, RSval: 1
beqzc :: 8, RSval: ffffffff
beqzc :: 9, RSval: ffffffff
beqzc :: a, RSval: fffffffe
beqzc :: b, RSval: ffffffff
beqzc :: c, RSval: 5
beqzc :: d, RSval: fffffffd
beqzc :: e, RSval: 7d
beqzc :: f, RSval: 80000000
beqzc :: 10, RSval: ffffffff
beqzc :: 11, RSval: 256
beqzc :: 12, RSval: 55
beqzc :: 13, RSval: fff
beqzc :: 14, RSval: ffffffff
beqzc :: 15, RSval: ffffffff
bnezc
bnezc :: 6, RSval: 0
bnezc :: 2, RSval: 1
bnezc :: 3, RSval: ffffffff
bnezc :: 4, RSval: ffffffff
bnezc :: 5, RSval: fffffffe
bnezc :: 6, RSval: ffffffff
bnezc :: 7, RSval: 5
bnezc :: 8, RSval: fffffffd
bnezc :: 9, RSval: 7d
bnezc :: a, RSval: 80000000
bnezc :: b, RSval: ffffffff
bnezc :: c, RSval: 256
bnezc :: d, RSval: 55
bnezc :: e, RSval: fff
bnezc :: f, RSval: ffffffff
bnezc :: 10, RSval: ffffffff
bovc
bovc :: 6, RSval: 0, RTval: 1
bovc :: 7, RSval: 1, RTval: 1
bovc :: 8, RSval: ffffffff, RTval: ffffffff
bovc :: 9, RSval: ffffffff, RTval: fffffffe
bovc :: a, RSval: fffffffe, RTval: ffffffff
bovc :: b, RSval: ffffffff, RTval: ffffffff
bovc :: c, RSval: 5, RTval: 5
bovc :: d, RSval: fffffffd, RTval: fffffffc
bovc :: e, RSval: 7d, RTval: 7d
bovc :: a, RSval: 80000000, RTval: 80000000
bovc :: b, RSval: ffffffff, RTval: 80000000
bovc :: 11, RSval: 256, RTval: 256
bovc :: 12, RSval: 55, RTval: 55
bovc :: 13, RSval: fff, RTval: dd
bovc :: 14, RSval: ffffffff, RTval: 5
bovc :: 15, RSval: ffffffff, RTval: ffffffff
bnvc
bnvc :: 1, RSval: 0, RTval: 1
bnvc :: 2, RSval: 1, RTval: 1
bnvc :: 3, RSval: ffffffff, RTval: ffffffff
bnvc :: 4, RSval: ffffffff, RTval: fffffffe
bnvc :: 5, RSval: fffffffe, RTval: ffffffff
bnvc :: 6, RSval: ffffffff, RTval: ffffffff
bnvc :: 7, RSval: 5, RTval: 5
bnvc :: 8, RSval: fffffffd, RTval: fffffffc
bnvc :: 9, RSval: 7d, RTval: 7d
bnvc :: f, RSval: 80000000, RTval: 80000000
bnvc :: 10, RSval: ffffffff, RTval: 80000000
bnvc :: c, RSval: 256, RTval: 256
bnvc :: d, RSval: 55, RTval: 55
bnvc :: e, RSval: fff, RTval: dd
bnvc :: f, RSval: ffffffff, RTval: 5
bnvc :: 10, RSval: ffffffff, RTval: ffffffff
jialc
jialc:: 1, RSval: 0, $t1 == $ra: 1
jialc:: 4, RSval: 4, $t1 == $ra: 1
jialc:: 1, RSval: 8, $t1 == $ra: 1
jialc:: 1, RSval: 10, $t1 == $ra: 0
jialc:: 0, RSval: 20, $t1 == $ra: 0
jic
jic:: 1, RSval: 0, $t1 == $ra: 0
jic:: 4, RSval: 4, $t1 == $ra: 0
jic:: 1, RSval: 8, $t1 == $ra: 0
jic:: 1, RSval: 10, $t1 == $ra: 0
jic:: 0, RSval: 20, $t1 == $ra: 0

3
none/tests/mips32/branches_r6.vgtest Normal file
View File

@ -0,0 +1,3 @@
prereq: (../../../tests/mips_features mipsr6)
prog: branches_r6
vgopts: -q

65
none/tests/mips32/change_fp_mode.c
View File

@ -15,6 +15,7 @@
/* Determine FP mode based on sdc1 behavior
returns 1 if FR = 1 mode is detected. */
static int get_fp_mode(void) {
unsigned long long result = 0;
__asm__ volatile(
@ -47,10 +48,15 @@ static void test(int* fr_prctl, int* fr_detected) {
}
printf("fr_prctl: %d, fr_detected: %d\n", *fr_prctl, *fr_detected);
#if (__mips_isa_rev >= 6)
if ((*fr_prctl != *fr_detected) && ((*fr_prctl != 3) || (*fr_detected != 0))) {
fatal_error("fr_prctl != fr_detected");
}
#else
if (*fr_prctl != *fr_detected) {
fatal_error("fr_prctl != fr_detected");
}
#endif
}
int main() {
@ -61,11 +67,66 @@ int main() {
/* FP64 */
if (fr_prctl == 1) {
#if (__mips_isa_rev >= 6)
unsigned int w;
unsigned long long l;
/* Change mode to FRE */
if (prctl(PR_SET_FP_MODE, 3) != 0) {
fatal_error("prctl(PR_SET_FP_MODE, 3) fails.");
}
printf("Write to odd, read from even... ");
w = 0x12345678;
l = 0xAAAAAAAABBBBBBBB;
__asm__ volatile (
"ldc1 $f0, 0(%1) \n\t"
"mtc1 %0, $f1 \n\t"
"sdc1 $f0, 0(%1) \n\t"
: : "r" (w), "r" (&l) : "memory", "$f0", "$f1"
);
if (l == 0x12345678BBBBBBBBull) printf("OK\n");
else printf ("Error: l = %llX\n", l);
printf("Write to even, read from odd... ");
w = 0xAAAAAAAA;
l = 0x12345678AAAAAAAA;
__asm__ volatile (
"ldc1 $f0, 0(%1) \n\t"
"mfc1 %0, $f1 \n\t"
: "+r" (w) : "r" (&l) : "$f0", "$f1"
);
if (w == 0x12345678ul) printf("OK\n");
else printf ("Error: w = %X\n", w);
printf("Write to low part, check high part... ");
w = 0xBBBBBBBB;
l = 0x12345678AAAAAAAA;
__asm__ volatile (
"ldc1 $f0, 0(%1) \n\t"
"mtc1 %0, $f0 \n\t"
"sdc1 $f0, 0(%1) \n\t"
: : "r" (w), "r" (&l) : "memory", "$f0"
);
if (l == 0x12345678BBBBBBBBull) printf("OK\n");
else printf ("Error: l = %llX\n", l);
#else
/* Change mode to FP32 */
if (prctl(PR_SET_FP_MODE, 0) != 0) {
fatal_error("prctl(PR_SET_FP_MODE, 0) fails.");
}
#endif
test(&fr_prctl, &fr_detected);
/* Change back FP mode */

6
none/tests/mips32/change_fp_mode.stdout.exp-r6 Normal file
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@ -0,0 +1,6 @@
fr_prctl: 1, fr_detected: 1
Write to odd, read from even... OK
Write to even, read from odd... OK
Write to low part, check high part... OK
fr_prctl: 3, fr_detected: 0
fr_prctl: 1, fr_detected: 1

7300
none/tests/mips32/fp_r6.c Normal file
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File diff suppressed because it is too large Load Diff

0
none/tests/mips32/fp_r6.stderr.exp Normal file
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7509
none/tests/mips32/fp_r6.stdout.exp Normal file
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File diff suppressed because it is too large Load Diff

3
none/tests/mips32/fp_r6.vgtest Normal file
View File

@ -0,0 +1,3 @@
prereq: ../../../tests/mips_features fpu && (../../../tests/mips_features mipsr6)
prog: fp_r6
vgopts: -q

3
none/tests/mips32/fpu_branches.c
View File

@ -1,4 +1,4 @@
#if defined(__mips_hard_float)
#if defined(__mips_hard_float) && (__mips_isa_rev<6)
#include <stdio.h>
@ -174,7 +174,6 @@ const double ft_d[] = {
int main()
{
int i = 0;
printf("--- BC1F --- if fs != ft then " \
"out = fs else out = fs + ft\n");
for (i = 0; i < MAX_ARR; i++) {

2
none/tests/mips32/fpu_branches.vgtest
View File

@ -1,3 +1,3 @@
prog: fpu_branches
prereq: ../../../tests/mips_features fpu
prereq: ../../../tests/mips_features fpu && !(../../../tests/mips_features mipsr6)
vgopts: -q

4
none/tests/mips32/mips32_dsp.c
View File

@ -104,9 +104,9 @@ void ppMem(unsigned int* _mem, int _len)
"move $" #RD ", %2 \n\t" \
instruction" end"instruction#RDval" \n\t" \
"nop \n\t" \
"addi $" #RD ", $" #RD", 5 \n\t" \
"addiu $" #RD ", $" #RD", 5 \n\t" \
"end"instruction#RDval": \n\t" \
"addi $" #RD ", $" #RD", 1 \n\t" \
"addiu $" #RD ", $" #RD", 1 \n\t" \
"move %0, $" #RD " \n\t" \
: "=&r" (out) \
: "r" (POSval), "r" (RDval) \

114
none/tests/mips32/pc_instructions_r6.c Normal file
View File

@ -0,0 +1,114 @@
#include <stdio.h>
#define TESTINST1(instruction, RSval, RD) \
{ \
unsigned int out; \
unsigned int out1; \
__asm__ volatile( \
".set push \n\t" \
".set noreorder \n\t" \
"jal end"instruction#RSval "\n\t" \
"nop \n\t" \
"end"instruction#RSval ": \n\t" \
instruction " $" #RD ", " #RSval " \n\t" \
"move %0, $" #RD "\n\t" \
"move %1, $ra \n\t" \
".set pop \n\t" \
: "=&r" (out), "=&r" (out1) \
: "r" (RSval) \
: #RD, "ra", "cc", "memory" \
); \
printf(instruction" :: out - ra %x, RSval 0x%08x\n", \
out - out1, RSval); \
}
#define TESTINST2(instruction, RSval, RD) \
{ \
unsigned int out; \
unsigned int out1; \
__asm__ volatile( \
".set push \n\t" \
".set noreorder \n\t" \
"jal end"instruction#RSval "\n\t" \
"nop \n\t" \
"end"instruction#RSval ": \n\t" \
instruction " $" #RD ", " #RSval " \n\t" \
"move %0, $" #RD "\n\t" \
"move %1, $ra \n\t" \
".set pop \n\t" \
: "=&r" (out), "=&r" (out1) \
: "r" (RSval) \
: #RD, "ra", "cc", "memory" \
); \
printf(instruction" :: out - ra %x, RSval 0x%08x\n", \
out - (out1 & ~0xffffffff), RSval); \
}
#define TESTINST3(instruction, RSval, RD) \
{ \
unsigned int out = 0; \
__asm__ __volatile__( \
".set push \n\t" \
".set noreorder \n\t" \
"lbl"instruction#RSval ": \n\t" \
"or $0, $0, $0 \n\t" \
"and $0, $0, $0 \n\t" \
instruction" $"#RD ", lbl"instruction#RSval "\n\t" \
"move %0, $"#RD "\n\t" \
".set pop \n\t" \
: "=r" (out) \
: \
: "t0", "t1" \
); \
printf("%s :: out: 0x%x\n", instruction, out); \
}
int main() {
#if (__mips_isa_rev>=6)
printf("addiupc\n");
TESTINST1("addiupc", 0, v0);
TESTINST1("addiupc", 4, v1);
TESTINST1("addiupc", 16, a0);
TESTINST1("addiupc", 64, a1);
TESTINST1("addiupc", 256, a3);
TESTINST1("addiupc", 1024, t0);
TESTINST1("addiupc", 4096, t1);
TESTINST1("addiupc", 16384, t2);
printf("\naluipc\n");
TESTINST2("aluipc", 0, v0);
TESTINST2("aluipc", 4, v1);
TESTINST2("aluipc", 16, a0);
TESTINST2("aluipc", 64, a1);
TESTINST2("aluipc", 256, a3);
TESTINST2("aluipc", 1024, t0);
TESTINST2("aluipc", 4096, t1);
TESTINST2("aluipc", 16384, t2);
printf("\nauipc\n");
TESTINST1("auipc", 0, v0);
TESTINST1("auipc", 4, v1);
TESTINST1("auipc", 16, a0);
TESTINST1("auipc", 64, a1);
TESTINST1("auipc", 256, a3);
TESTINST1("auipc", 1024, t0);
TESTINST1("auipc", 4096, t1);
TESTINST1("auipc", 16384, t2);
printf("\nlwpc\n");
TESTINST3("lwpc", 0, v0);
TESTINST3("lwpc", 4, v1);
TESTINST3("lwpc", 16, a0);
TESTINST3("lwpc", 64, a1);
TESTINST3("lwpc", 256, a3);
TESTINST3("lwpc", 1024, t0);
TESTINST3("lwpc", 4096, t1);
TESTINST3("lwpc", 16384, t2);
#endif
return 0;
}

0
none/tests/mips32/pc_instructions_r6.stderr.exp Normal file
View File

39
none/tests/mips32/pc_instructions_r6.stdout.exp Normal file
View File

@ -0,0 +1,39 @@
addiupc
addiupc :: out - ra 0, RSval 0x00000000
addiupc :: out - ra 4, RSval 0x00000004
addiupc :: out - ra 10, RSval 0x00000010
addiupc :: out - ra 40, RSval 0x00000040
addiupc :: out - ra 100, RSval 0x00000100
addiupc :: out - ra 400, RSval 0x00000400
addiupc :: out - ra 1000, RSval 0x00001000
addiupc :: out - ra 4000, RSval 0x00004000
aluipc
aluipc :: out - ra 400000, RSval 0x00000000
aluipc :: out - ra 440000, RSval 0x00000004
aluipc :: out - ra 500000, RSval 0x00000010
aluipc :: out - ra 800000, RSval 0x00000040
aluipc :: out - ra 1400000, RSval 0x00000100
aluipc :: out - ra 4400000, RSval 0x00000400
aluipc :: out - ra 10400000, RSval 0x00001000
aluipc :: out - ra 40400000, RSval 0x00004000
auipc
auipc :: out - ra 0, RSval 0x00000000
auipc :: out - ra 40000, RSval 0x00000004
auipc :: out - ra 100000, RSval 0x00000010
auipc :: out - ra 400000, RSval 0x00000040
auipc :: out - ra 1000000, RSval 0x00000100
auipc :: out - ra 4000000, RSval 0x00000400
auipc :: out - ra 10000000, RSval 0x00001000
auipc :: out - ra 40000000, RSval 0x00004000
lwpc
lwpc :: out: 0x25
lwpc :: out: 0x25
lwpc :: out: 0x25
lwpc :: out: 0x25
lwpc :: out: 0x25
lwpc :: out: 0x25
lwpc :: out: 0x25
lwpc :: out: 0x25

3
none/tests/mips32/pc_instructions_r6.vgtest Normal file
View File

@ -0,0 +1,3 @@
prereq: (../../../tests/mips_features mipsr6)
prog: pc_instructions_r6
vgopts: -q

3
none/tests/mips32/unaligned_load_store.c
View File

@ -14,6 +14,7 @@ void printMem(char* s)
int main ()
{
#if (__mips_isa_rev<6)
printMem("PRE lwl");
__asm__ volatile("move $a0, %0" "\n\t"
"lw $t0, 0($a0)" "\n\t"
@ -62,6 +63,6 @@ int main ()
: "a0", "t0", "t1", "t2", "t3", "cc", "memory"
);
printMem("POST lwr");
#endif
return 0;
}

1
none/tests/mips32/unaligned_load_store.vgtest
View File

@ -1,2 +1,3 @@
prog: unaligned_load_store
prereq: !(../../../tests/mips_features mipsr6)
vgopts: -q

13
none/tests/mips32/vfp.c
View File

@ -247,7 +247,9 @@ float mem1f[] = {
out); \
}
#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_fpr==64 || __mips_fpr==xx)
#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_isa_rev<6) \
&& (__mips_fpr==64 || __mips_fpr==xx)
#define TEST_FPU64 \
__asm__ __volatile__( \
"cvt.l.s $f0, $f0" "\n\t" \
@ -350,7 +352,7 @@ int main()
TESTINSN5LOADw("lwc1 $f0, 64($t1)", 0, 64, f0);
TESTINSN5LOADw("lwc1 $f0, 0($t1)", 0, 0, f0);
#if (__mips==32) && (__mips_isa_rev>=2)
#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_isa_rev<6)
printf("LWXC1\n");
TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 0, f0, a3, v0);
TESTINSN6LOADw("lwxc1 $f0, $a3($v0)", 4, f0, a3, v0);
@ -432,7 +434,7 @@ int main()
TESTINST1(64);
ppMem(mem1, 16);
#if (__mips==32) && (__mips_isa_rev>=2)
#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_isa_rev<6)
printf("SDXC1\n");
TESTINST1a(0);
TESTINST1a(8);
@ -458,7 +460,7 @@ int main()
TESTINST2(64);
ppMemF(mem1f, 16);
#if (__mips==32) && (__mips_isa_rev>=2)
#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_isa_rev<6)
printf("SWXC1\n");
TESTINST2a(0);
TESTINST2a(8);
@ -472,7 +474,8 @@ int main()
ppMemF(mem1f, 16);
#endif
#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_fpr==64 || __mips_fpr==xx)
#if (__mips==32) && (__mips_isa_rev>=2) && (__mips_isa_rev<6) \
&& (__mips_fpr==64 || __mips_fpr==xx)
signal(SIGILL, handler);
/* Test fpu64 mode. */
TEST_FPU64;

1
none/tests/mips64/MIPS64r6int.c Symbolic link
View File

@ -0,0 +1 @@
../mips32/MIPS32r6int.c

1
none/tests/mips64/MIPS64r6int.stderr.exp Symbolic link
View File

@ -0,0 +1 @@
../mips32/MIPS32r6int.stderr.exp

1
none/tests/mips64/MIPS64r6int.stdout.exp Symbolic link
View File

@ -0,0 +1 @@
../mips32/MIPS32r6int.stdout.exp

3
none/tests/mips64/MIPS64r6int.vgtest Normal file
View File

@ -0,0 +1,3 @@
prereq: (../../../tests/mips_features mipsr6)
prog: MIPS64r6int
vgopts: -q

26
none/tests/mips64/Makefile.am
View File

@ -6,10 +6,12 @@ dist_noinst_SCRIPTS = filter_stderr
EXTRA_DIST = \
arithmetic_instruction.stdout.exp-mips64 \
arithmetic_instruction.stdout.exp-mips64r2 arithmetic_instruction.stderr.exp \
arithmetic_instruction.vgtest \
arithmetic_instruction.vgtest arithmetic_instruction.stdout.exp-mips64r6 \
branch_and_jump_instructions.stdout.exp \
branch_and_jump_instructions.stderr.exp branch_and_jump_instructions.vgtest \
branches.stdout.exp branches.stderr.exp branches.vgtest \
branches.stdout.exp branches.stderr.exp branches.vgtest branches.stdout.exp-r6 \
branches_r6.stderr.exp branches_r6.stdout.exp branches_r6.vgtest\
branch_pc.stderr.exp branch_pc.stdout.exp branch_pc.vgtest \
change_fp_mode.stderr.exp change_fp_mode.stdout.exp change_fp_mode.vgtest \
cvm_bbit.stdout.exp cvm_bbit.stdout.exp-non-octeon \
cvm_bbit.stderr.exp cvm_bbit.vgtest \
@ -27,25 +29,32 @@ EXTRA_DIST = \
extract_insert_bit_field.stdout.exp-mips64r2 \
extract_insert_bit_field.stderr.exp extract_insert_bit_field.vgtest \
fpu_arithmetic.stdout.exp fpu_arithmetic.stderr.exp fpu_arithmetic.vgtest \
fpu_arithmetic.stdout.exp-r6 \
fpu_branches.stdout.exp fpu_branches.stderr.exp fpu_branches.vgtest \
fpu_control_word.stdout.exp fpu_control_word.stderr.exp \
fpu_control_word.vgtest \
fpu_load_store.stdout.exp-BE fpu_load_store.stdout.exp-LE \
fpu_load_store.stderr.exp fpu_load_store.vgtest \
fpu_load_store.stdout.exp-BE-r2 fpu_load_store.stdout.exp-LE-r2 \
fpu_load_store.stdout.exp-BE-r6 fpu_load_store.stdout.exp-LE-r6 \
fp_r6.stderr.exp fp_r6.stdout.exp fp_r6.vgtest \
load_indexed_instructions.stdout.exp-BE \
load_indexed_instructions.stdout.exp-LE \
load_indexed_instructions.stdout.exp-non-octeon \
load_indexed_instructions.stderr.exp load_indexed_instructions.vgtest \
load_store.stdout.exp-BE load_store.stdout.exp-LE load_store.stderr.exp \
load_store.vgtest \
load_store.vgtest load_store.stdout.exp-LE-r6 load_store.stdout.exp-BE-r6 \
load_store_multiple.stdout.exp-BE load_store_multiple.stdout.exp-LE \
load_store_multiple.stderr.exp load_store_multiple.vgtest \
load_store_multiple.stdout.exp-LE-r6 load_store_multiple.stdout.exp-BE-r6 \
load_store_unaligned.stdout.exp load_store_unaligned.stderr.exp \
load_store_unaligned.vgtest \
logical_instructions.stdout.exp logical_instructions.stderr.exp \
load_store_unaligned.vgtest \
logical_instructions.vgtest \
move_instructions.stdout.exp-BE move_instructions.stdout.exp-LE \
move_instructions.stderr.exp move_instructions.vgtest \
move_instructions.stdout.exp-r6 \
MIPS64r6int.stderr.exp MIPS64r6int.stdout.exp MIPS64r6int.vgtest \
msa_data_transfer.stdout.exp msa_data_transfer.stderr.exp \
msa_data_transfer.vgtest msa_data_transfer.stdout.exp-BE \
msa_arithmetic.stderr.exp msa_arithmetic.stdout.exp msa_arithmetic.vgtest \
@ -57,6 +66,9 @@ EXTRA_DIST = \
rotate_swap.stdout.exp-mips64 rotate_swap.stdout.exp-mips64r2 \
rotate_swap.stderr.exp rotate_swap.vgtest \
round.stdout.exp round.stderr.exp round.vgtest \
r6_instructions.stdout.exp-LE r6_instructions.stdout.exp-BE r6_instructions.stderr.exp \
r6_instructions.vgtest \
pc_instructions_r6.stderr.exp pc_instructions_r6.stdout.exp pc_instructions_r6.vgtest \
shift_instructions.stdout.exp-mips64 shift_instructions.stdout.exp-mips64r2 \
shift_instructions.stderr.exp shift_instructions.vgtest \
test_block_size.stdout.exp test_block_size.stderr.exp \
@ -76,6 +88,8 @@ check_PROGRAMS = \
arithmetic_instruction \
branch_and_jump_instructions \
branches \
branches_r6 \
branch_pc \
change_fp_mode \
cvm_bbit \
cvm_ins \
@ -87,6 +101,7 @@ check_PROGRAMS = \
fpu_branches \
fpu_control_word \
fpu_load_store \
fp_r6 \
load_indexed_instructions \
load_store \
load_store_multiple \
@ -99,6 +114,9 @@ check_PROGRAMS = \
msa_fpu \
msa_logical_and_shift \
msa_shuffle \
r6_instructions \
MIPS64r6int \
pc_instructions_r6 \
rotate_swap \
round \
shift_instructions \

28
none/tests/mips64/arithmetic_instruction.c
View File

@ -2,6 +2,7 @@
#include "const.h"
#include "macro_int.h"
#if (__mips_isa_rev < 6)
typedef enum {
ADD=0, ADDI, ADDIU, ADDU,
CLO, CLZ, DADD, DADDI,
@ -14,6 +15,17 @@ typedef enum {
SLTI, SLTIU, SLTU, SUB,
SUBU
} arithmetic_op;
#else
typedef enum {
ADD=0, ADDIU, ADDU,
CLO, CLZ, DCLO, DCLZ,
DADD, DADDIU, DADDU,
DSUB, DSUBU, SUB, SUBU,
SEB, SEH,
SLT, SLTI, SLTIU, SLTU
} arithmetic_op;
#endif
int main()
{
@ -32,6 +44,7 @@ int main()
t0, t1, t2);
break;
#if (__mips_isa_rev < 6)
case ADDI:
/* If GPR rs does not contain a sign-extended 32-bit
value (bits 63..31 equal), then the result of the operation
@ -41,7 +54,7 @@ int main()
TEST2("addi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
TEST2("addi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
break;
#endif
case ADDIU:
/* If GPR rs does not contain a sign-extended 32-bit
value (bits 63..31 equal), then the result of the operation
@ -81,7 +94,7 @@ int main()
TEST1("dadd $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
t0, t1, t2);
break;
#if (__mips_isa_rev < 6)
case DADDI:
/* If the addition results in 64-bit 2âs complement arithmetic
overflow, then the destination register is not modified and
@ -95,7 +108,7 @@ int main()
TEST2("daddi $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1);
TEST2("daddi $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1);
break;
#endif
case DADDIU:
/* No Integer Overflow exception occurs under any
circumstances. */
@ -129,7 +142,7 @@ int main()
TEST3("dclz $t0, $t1", reg_val1[i], t0, t1);
TEST3("dclz $v0, $v1", reg_val2[i], v0, v1);
break;
#if (__mips_isa_rev < 6)
case DDIV:
/* If the divisor in GPR rt is zero, the arithmetic result value
is UNPREDICTABLE. */
@ -185,7 +198,7 @@ int main()
TEST4("dmultu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
TEST4("dmultu $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1);
break;
#endif
case DSUB:
/* If the subtraction results in 64-bit 2âs complement
arithmetic overflow, then the destination register is not
@ -202,7 +215,7 @@ int main()
TEST1("dsubu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
s0, s1, s2);
break;
#if (__mips_isa_rev < 6)
case MADD:
/* If GPRs rs or rt do not contain sign-extended 32-bit
values (bits 63..31 equal), then the results of the operation
@ -272,7 +285,7 @@ int main()
TEST1("movz $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
s0, s1, s2);
break;
#endif
case SEB:
#if (__mips==64) && (__mips_isa_rev>=2)
/* If GPR rt does not contain a sign-extended 32-bit
@ -349,7 +362,6 @@ int main()
TEST1("subu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
t0, t1, t2);
break;
default:
printf("Error!\n");
break;

6926
none/tests/mips64/arithmetic_instruction.stdout.exp-mips64r6 Normal file
View File

File diff suppressed because it is too large Load Diff

4
none/tests/mips64/branch_and_jump_instructions.c
View File

@ -1,6 +1,7 @@
#include <stdio.h>
#include "const.h"
#define TEST1(RSval, RD) \
{ \
unsigned long long out = 0; \
@ -179,6 +180,7 @@ int main()
{
int i;
init_reg_val2();
#if (__mips_isa_rev < 6)
printf("B \n");
for (i = 0; i < N; i++)
@ -347,6 +349,6 @@ int main()
printf("J, JALR \n");
for (i = 0; i < N; i++)
TEST2b(reg_val1[i], t1);
#endif
return 0;
}

1
none/tests/mips64/branch_and_jump_instructions.vgtest
View File

@ -1,2 +1,3 @@
prog: branch_and_jump_instructions
vgopts: -q
prereq: !(../../../tests/mips_features mipsr6)

1
none/tests/mips64/branch_pc.c Symbolic link
View File

@ -0,0 +1 @@
../mips32/branch_pc.c

1
none/tests/mips64/branch_pc.stderr.exp Symbolic link
View File

@ -0,0 +1 @@
../mips32/branch_pc.stderr.exp

1
none/tests/mips64/branch_pc.stdout.exp Symbolic link
View File

@ -0,0 +1 @@
../mips32/branch_pc.stdout.exp

1
none/tests/mips64/branch_pc.vgtest Symbolic link
View File

@ -0,0 +1 @@
../mips32/branch_pc.vgtest

65
none/tests/mips64/branches.c
View File

@ -8,9 +8,9 @@
"move $"#RD", %1" "\n\t" \
"b end"#RSval "\n\t" \
"nop" "\n\t" \
"addi $"#RD", $"#RD", 5" "\n\t" \
"addiu $"#RD", $"#RD", 5" "\n\t" \
"end"#RSval":" "\n\t" \
"addi $"#RD", $"#RD", 1" "\n\t" \
"addiu $"#RD", $"#RD", 1" "\n\t" \
"move %0, $"#RD "\n\t" \
".set reorder" "\n\t" \
: "=r" (out) \
@ -28,10 +28,10 @@
".set noreorder" "\n\t" \
"move $"#RD", %1" "\n\t" \
"b end12"#RSval "\n\t" \
"addi $"#RD", $"#RD", 3" "\n\t" \
"addi $"#RD", $"#RD", 5" "\n\t" \
"addiu $"#RD", $"#RD", 3" "\n\t" \
"addiu $"#RD", $"#RD", 5" "\n\t" \
"end12"#RSval":" "\n\t" \
"addi $"#RD", $"#RD", 3" "\n\t" \
"addiu $"#RD", $"#RD", 3" "\n\t" \
"move %0, $"#RD "\n\t" \
".set reorder" "\n\t" \
: "=r" (out) \
@ -50,12 +50,12 @@
"move $"#RD", %1" "\n\t" \
"bal end21"#RSval "\n\t" \
"nop" "\n\t" \
"addi $"#RD", $"#RD", 5" "\n\t" \
"addiu $"#RD", $"#RD", 5" "\n\t" \
"b r_end"#RSval "\n\t" \
"nop" "\n\t" \
"addi $"#RD", $"#RD", 1" "\n\t" \
"addiu $"#RD", $"#RD", 1" "\n\t" \
"end21"#RSval":" "\n\t" \
"addi $"#RD", $"#RD", 1" "\n\t" \
"addiu $"#RD", $"#RD", 1" "\n\t" \
"jr $ra" "\n\t" \
"nop" "\n\t" \
"r_end"#RSval":" "\n\t" \
@ -78,12 +78,12 @@
"dla $t9, end31"#RSval "\n\t" \
"jal $t9" "\n\t" \
"nop" "\n\t" \
"addi $"#RD", $"#RD", 5" "\n\t" \
"addiu $"#RD", $"#RD", 5" "\n\t" \
"dla $t9, r_end11"#RSval "\n\t" \
"j $t9" "\n\t" \
"nop" "\n\t" \
"end31"#RSval":" "\n\t" \
"addi $"#RD", $"#RD", 1" "\n\t" \
"addiu $"#RD", $"#RD", 1" "\n\t" \
"jr $ra" "\n\t" \
"nop" "\n\t" \
"r_end11"#RSval":" "\n\t" \
@ -106,13 +106,13 @@
"dla $t9, end41"#RSval "\n\t" \
"jalr $t0, $t9" "\n\t" \
"nop" "\n\t" \
"addi $"#RD", $"#RD", 5" "\n\t" \
"addiu $"#RD", $"#RD", 5" "\n\t" \
"dla $t9, r_end21"#RSval "\n\t" \
"j $t9" "\n\t" \
"nop" "\n\t" \
"addi $"#RD", $"#RD", 1" "\n\t" \
"addiu $"#RD", $"#RD", 1" "\n\t" \
"end41"#RSval":" "\n\t" \
"addi $"#RD", $"#RD", 1" "\n\t" \
"addiu $"#RD", $"#RD", 1" "\n\t" \
"move $t9, $t0" "\n\t" \
"jr $t9" "\n\t" \
"nop" "\n\t" \
@ -137,9 +137,9 @@
"move $"#RD", %3" "\n\t" \
instruction" $"#RS", $"#RT", end"instruction#RDval "\n\t" \
"nop" "\n\t" \
"addi $"#RD", $"#RD", 5" "\n\t" \
"addiu $"#RD", $"#RD", 5" "\n\t" \
"end"instruction#RDval":" "\n\t" \
"addi $"#RD", $"#RD", 1" "\n\t" \
"addiu $"#RD", $"#RD", 1" "\n\t" \
"move %0, $" #RD "\n\t" \
".set reorder" "\n\t" \
: "=r" (out) \
@ -159,9 +159,9 @@
"move $"#RD", %2" "\n\t" \
instruction" $"#RS", end"instruction#RDval "\n\t" \
"nop" "\n\t" \
"addi $"#RD", $"#RD", 5" "\n\t" \
"addiu $"#RD", $"#RD", 5" "\n\t" \
"end"instruction#RDval":" "\n\t" \
"addi $"#RD", $"#RD", 1" "\n\t" \
"addiu $"#RD", $"#RD", 1" "\n\t" \
"move %0, $"#RD "\n\t" \
".set reorder" "\n\t" \
: "=r" (out) \
@ -181,11 +181,11 @@
"move $"#RS", %1" "\n\t" \
instruction" $"#RS", end21"instruction#RDval "\n\t" \
"nop" "\n\t" \
"addi $"#RD", $"#RD", 5" "\n\t" \
"addiu $"#RD", $"#RD", 5" "\n\t" \
"b r_end"instruction#RDval "\n\t" \
"nop" "\n\t" \
"end21"instruction#RDval":" "\n\t" \
"addi $"#RD", $"#RD", 1" "\n\t" \
"addiu $"#RD", $"#RD", 1" "\n\t" \
"jr $ra" "\n\t" \
"r_end"instruction#RDval":" "\n\t" \
"move %0, $"#RD "\n\t" \
@ -207,10 +207,10 @@
"move $"#RT", %2" "\n\t" \
"move $"#RD", %3" "\n\t" \
instruction" $"#RS", $"#RT", end"instruction#RDval "\n\t" \
"addi $"#RD", $"#RD", 3" "\n\t" \
"addi $"#RD", $"#RD", 5" "\n\t" \
"addiu $"#RD", $"#RD", 3" "\n\t" \
"addiu $"#RD", $"#RD", 5" "\n\t" \
"end"instruction#RDval":" "\n\t" \
"addi $"#RD", $"#RD", 1" "\n\t" \
"addiu $"#RD", $"#RD", 1" "\n\t" \
"move %0, $"#RD "\n\t" \
".set reorder" "\n\t" \
: "=r" (out) \
@ -229,10 +229,10 @@
"move $"#RS", %1" "\n\t" \
"move $"#RD", %2" "\n\t" \
instruction" $"#RS", end"instruction#RDval "\n\t" \
"addi $"#RD", $"#RD", 3" "\n\t" \
"addi $"#RD", $"#RD", 5" "\n\t" \
"addiu $"#RD", $"#RD", 3" "\n\t" \
"addiu $"#RD", $"#RD", 5" "\n\t" \
"end"instruction#RDval":" "\n\t" \
"addi $"#RD", $"#RD", 1" "\n\t" \
"addiu $"#RD", $"#RD", 1" "\n\t" \
"move %0, $"#RD "\n\t" \
".set reorder" "\n\t" \
: "=r" (out) \
@ -251,12 +251,12 @@
"move $"#RD", %2" "\n\t" \
"move $"#RS", %1" "\n\t" \
instruction" $"#RS", end21"instruction#RDval "\n\t" \
"addi $"#RD", $"#RD", 3" "\n\t" \
"addi $"#RD", $"#RD", 5" "\n\t" \
"addiu $"#RD", $"#RD", 3" "\n\t" \
"addiu $"#RD", $"#RD", 5" "\n\t" \
"b r_end"instruction#RDval "\n\t" \
"nop" "\n\t" \
"end21"instruction#RDval":" "\n\t" \
"addi $"#RD", $"#RD", 1" "\n\t" \
"addiu $"#RD", $"#RD", 1" "\n\t" \
"jr $ra" "\n\t" \
"nop" "\n\t" \
"r_end"instruction#RDval":" "\n\t" \
@ -273,6 +273,7 @@
int main()
{
printf("b\n");
TESTINST1(0, 2);
TESTINST1(1, 3);
@ -483,7 +484,7 @@ int main()
TESTINST5("bltz", 13, 0xfff, 16, 17);
TESTINST5("bltz", 14, -1, 2, 25);
TESTINST5("bltz", 15, -1, 25, 24);
#if (__mips_isa_rev < 6)
printf("--- BGEZAL --- if RSval >= 0 then " \
"out = RDval + 6 else out = RDval + 5\n");
TESTINST6("bgezal", 0, 0, 2, 3);
@ -521,7 +522,7 @@ int main()
TESTINST6("bltzal", 13, 0xfff, 16, 17);
TESTINST6("bltzal", 14, -1, 2, 25);
TESTINST6("bltzal", 15, -1, 25, 24);
#endif
printf("--- BNEZ --- if RSval != 0 then " \
"out = RDval + 1 else out = RDval + 6\n");
TESTINST5("bnez", 0, 0, 2, 3);
@ -540,7 +541,7 @@ int main()
TESTINST5("bnez", 13, 0xfff, 16, 17);
TESTINST5("bnez", 14, -1, 2, 25);
TESTINST5("bnez", 15, -1, 25, 24);
#if (__mips_isa_rev < 6)
printf("--- BEQL --- if RSval == RTval then " \
"out = RDval + 4 else out = RDval + 6\n");
TESTINST4l("beql", 0, 0, 1, 2, 3, 4);
@ -711,7 +712,7 @@ int main()
TESTINST4l("bnel", 13, 0xfff, 0xdd, 16, 17, 18);
TESTINST4l("bnel", 14, -1, 0x5, 2, 25, 24);
TESTINST4l("bnel", 15, -1, -1, 25, 24, 7);
#endif
printf("j, jal, jr\n");
TESTINST3j(0, 2);
TESTINST3j(1, 3);

260
none/tests/mips64/branches.stdout.exp-r6 Normal file
View File

@ -0,0 +1,260 @@
b
B :: 1, RSval: 0
B :: 2, RSval: 1
B :: 3, RSval: 2
B :: 4, RSval: 3
B :: 5, RSval: 4
B :: 6, RSval: 5
B :: 7, RSval: 6
B :: 8, RSval: 7
B :: 9, RSval: 8
B :: 10, RSval: 9
B :: 11, RSval: 10
B :: 12, RSval: 11
B :: 13, RSval: 12
B :: 14, RSval: 13
B :: 15, RSval: 14
B :: 16, RSval: 15
B :: 17, RSval: 16
B :: 18, RSval: 17
B :: 19, RSval: 18
B :: 20, RSval: 19
B :: 21, RSval: 20
B :: 22, RSval: 21
B :: 23, RSval: 22
B :: 24, RSval: 23
b
B :: 6, RSval: 0
B :: 7, RSval: 1
B :: 8, RSval: 2
B :: 9, RSval: 3
B :: 10, RSval: 4
B :: 11, RSval: 5
B :: 12, RSval: 6
B :: 13, RSval: 7
B :: 14, RSval: 8
B :: 15, RSval: 9
B :: 16, RSval: 10
B :: 17, RSval: 11
B :: 18, RSval: 12
B :: 19, RSval: 13
B :: 20, RSval: 14
B :: 21, RSval: 15
B :: 22, RSval: 16
B :: 23, RSval: 17
B :: 24, RSval: 18
B :: 25, RSval: 19
B :: 26, RSval: 20
B :: 27, RSval: 21
B :: 28, RSval: 22
B :: 29, RSval: 23
b, bal, jr
B BAL JR :: 6, RSval: 0
B BAL JR :: 7, RSval: 1
B BAL JR :: 8, RSval: 2
B BAL JR :: 9, RSval: 3
B BAL JR :: 10, RSval: 4
B BAL JR :: 11, RSval: 5
B BAL JR :: 12, RSval: 6
B BAL JR :: 13, RSval: 7
B BAL JR :: 14, RSval: 8
B BAL JR :: 15, RSval: 9
B BAL JR :: 16, RSval: 10
B BAL JR :: 17, RSval: 11
B BAL JR :: 18, RSval: 12
B BAL JR :: 19, RSval: 13
B BAL JR :: 20, RSval: 14
B BAL JR :: 21, RSval: 15
B BAL JR :: 22, RSval: 16
B BAL JR :: 23, RSval: 17
B BAL JR :: 24, RSval: 18
B BAL JR :: 25, RSval: 19
B BAL JR :: 26, RSval: 20
B BAL JR :: 27, RSval: 21
B BAL JR :: 28, RSval: 22
B BAL JR :: 29, RSval: 23
--- BEQ --- if RSval == RTval then out = RDval + 1 else out = RDval + 6
beq :: out: 6, RDval: 0, RSval: 0, RTval: 1
beq :: out: 2, RDval: 1, RSval: 1, RTval: 1
beq :: out: 3, RDval: 2, RSval: -1, RTval: -1
beq :: out: 9, RDval: 3, RSval: -1, RTval: -2
beq :: out: 10, RDval: 4, RSval: -2, RTval: -1
beq :: out: 6, RDval: 5, RSval: -1, RTval: -1
beq :: out: 7, RDval: 6, RSval: 5, RTval: 5
beq :: out: 13, RDval: 7, RSval: -3, RTval: -4
beq :: out: 9, RDval: 8, RSval: 125, RTval: 125
beq :: out: 10, RDval: 9, RSval: -2147483648, RTval: -2147483648
beq :: out: 16, RDval: 10, RSval: -1, RTval: -2147483648
beq :: out: 12, RDval: 11, RSval: 598, RTval: 598
beq :: out: 13, RDval: 12, RSval: 85, RTval: 85
beq :: out: 19, RDval: 13, RSval: 4095, RTval: 221
beq :: out: 20, RDval: 14, RSval: -1, RTval: 5
beq :: out: 16, RDval: 15, RSval: -1, RTval: -1
--- BNE --- if RSval != RTval then out = RDval + 1 else out = RDval + 6
bne :: out: 1, RDval: 0, RSval: 0, RTval: 1
bne :: out: 7, RDval: 1, RSval: 1, RTval: 1
bne :: out: 8, RDval: 2, RSval: -1, RTval: -1
bne :: out: 4, RDval: 3, RSval: -1, RTval: -2
bne :: out: 5, RDval: 4, RSval: -2, RTval: -1
bne :: out: 11, RDval: 5, RSval: -1, RTval: -1
bne :: out: 12, RDval: 6, RSval: 5, RTval: 5
bne :: out: 8, RDval: 7, RSval: -3, RTval: -4
bne :: out: 14, RDval: 8, RSval: 125, RTval: 125
bne :: out: 15, RDval: 9, RSval: -2147483648, RTval: -2147483648
bne :: out: 11, RDval: 10, RSval: -1, RTval: -2147483648
bne :: out: 17, RDval: 11, RSval: 598, RTval: 598
bne :: out: 18, RDval: 12, RSval: 85, RTval: 85
bne :: out: 14, RDval: 13, RSval: 4095, RTval: 221
bne :: out: 15, RDval: 14, RSval: -1, RTval: 5
bne :: out: 21, RDval: 15, RSval: -1, RTval: -1
--- BEQZ --- if RSval == 0 then out = RDval + 1 else out = RDval + 6
beqz :: out: 1, RDval: 0, RSval: 0
beqz :: out: 7, RDval: 1, RSval: 1
beqz :: out: 8, RDval: 2, RSval: -1
beqz :: out: 9, RDval: 3, RSval: -1
beqz :: out: 10, RDval: 4, RSval: -2
beqz :: out: 11, RDval: 5, RSval: -1
beqz :: out: 12, RDval: 6, RSval: 5
beqz :: out: 13, RDval: 7, RSval: -3
beqz :: out: 14, RDval: 8, RSval: 125
beqz :: out: 15, RDval: 9, RSval: -2147483648
beqz :: out: 16, RDval: 10, RSval: -1
beqz :: out: 17, RDval: 11, RSval: 598
beqz :: out: 18, RDval: 12, RSval: 85
beqz :: out: 19, RDval: 13, RSval: 4095
beqz :: out: 20, RDval: 14, RSval: -1
beqz :: out: 21, RDval: 15, RSval: -1
--- BGEZ --- if RSval >= 0 then out = RDval + 1 else out = RDval + 6
bgez :: out: 1, RDval: 0, RSval: 0
bgez :: out: 2, RDval: 1, RSval: 1
bgez :: out: 8, RDval: 2, RSval: -1
bgez :: out: 9, RDval: 3, RSval: -1
bgez :: out: 10, RDval: 4, RSval: -2
bgez :: out: 11, RDval: 5, RSval: -1
bgez :: out: 7, RDval: 6, RSval: 5
bgez :: out: 13, RDval: 7, RSval: -3
bgez :: out: 9, RDval: 8, RSval: 125
bgez :: out: 15, RDval: 9, RSval: -2147483648
bgez :: out: 16, RDval: 10, RSval: -1
bgez :: out: 12, RDval: 11, RSval: 598
bgez :: out: 13, RDval: 12, RSval: 85
bgez :: out: 14, RDval: 13, RSval: 4095
bgez :: out: 20, RDval: 14, RSval: -1
bgez :: out: 21, RDval: 15, RSval: -1
--- BGTZ --- if RSval > 0 then out = RDval + 1 else out = RDval + 6
bgtz :: out: 6, RDval: 0, RSval: 0
bgtz :: out: 2, RDval: 1, RSval: 1
bgtz :: out: 8, RDval: 2, RSval: -1
bgtz :: out: 9, RDval: 3, RSval: -1
bgtz :: out: 10, RDval: 4, RSval: -2
bgtz :: out: 11, RDval: 5, RSval: -1
bgtz :: out: 7, RDval: 6, RSval: 5
bgtz :: out: 13, RDval: 7, RSval: -3
bgtz :: out: 9, RDval: 8, RSval: 125
bgtz :: out: 15, RDval: 9, RSval: -2147483648
bgtz :: out: 16, RDval: 10, RSval: -1
bgtz :: out: 12, RDval: 11, RSval: 598
bgtz :: out: 13, RDval: 12, RSval: 85
bgtz :: out: 14, RDval: 13, RSval: 4095
bgtz :: out: 20, RDval: 14, RSval: -1
bgtz :: out: 21, RDval: 15, RSval: -1
--- BLEZ --- if RSval <= 0 then out = RDval + 1 else out = RDval + 6
blez :: out: 1, RDval: 0, RSval: 0
blez :: out: 7, RDval: 1, RSval: 1
blez :: out: 3, RDval: 2, RSval: -1
blez :: out: 4, RDval: 3, RSval: -1
blez :: out: 5, RDval: 4, RSval: -2
blez :: out: 6, RDval: 5, RSval: -1
blez :: out: 12, RDval: 6, RSval: 5
blez :: out: 8, RDval: 7, RSval: -3
blez :: out: 14, RDval: 8, RSval: 125
blez :: out: 10, RDval: 9, RSval: -2147483648
blez :: out: 11, RDval: 10, RSval: -1
blez :: out: 17, RDval: 11, RSval: 598
blez :: out: 18, RDval: 12, RSval: 85
blez :: out: 19, RDval: 13, RSval: 4095
blez :: out: 15, RDval: 14, RSval: -1
blez :: out: 16, RDval: 15, RSval: -1
--- BLTZ --- if RSval < 0 then out = RDval + 1 else out = RDval + 6
bltz :: out: 6, RDval: 0, RSval: 0
bltz :: out: 7, RDval: 1, RSval: 1
bltz :: out: 3, RDval: 2, RSval: -1
bltz :: out: 4, RDval: 3, RSval: -1
bltz :: out: 5, RDval: 4, RSval: -2
bltz :: out: 6, RDval: 5, RSval: -1
bltz :: out: 12, RDval: 6, RSval: 5
bltz :: out: 8, RDval: 7, RSval: -3
bltz :: out: 14, RDval: 8, RSval: 125
bltz :: out: 10, RDval: 9, RSval: -2147483648
bltz :: out: 11, RDval: 10, RSval: -1
bltz :: out: 17, RDval: 11, RSval: 598
bltz :: out: 18, RDval: 12, RSval: 85
bltz :: out: 19, RDval: 13, RSval: 4095
bltz :: out: 15, RDval: 14, RSval: -1
bltz :: out: 16, RDval: 15, RSval: -1
--- BNEZ --- if RSval != 0 then out = RDval + 1 else out = RDval + 6
bnez :: out: 6, RDval: 0, RSval: 0
bnez :: out: 2, RDval: 1, RSval: 1
bnez :: out: 3, RDval: 2, RSval: -1
bnez :: out: 4, RDval: 3, RSval: -1
bnez :: out: 5, RDval: 4, RSval: -2
bnez :: out: 6, RDval: 5, RSval: -1
bnez :: out: 7, RDval: 6, RSval: 5
bnez :: out: 8, RDval: 7, RSval: -3
bnez :: out: 9, RDval: 8, RSval: 125
bnez :: out: 10, RDval: 9, RSval: -2147483648
bnez :: out: 11, RDval: 10, RSval: -1
bnez :: out: 12, RDval: 11, RSval: 598
bnez :: out: 13, RDval: 12, RSval: 85
bnez :: out: 14, RDval: 13, RSval: 4095
bnez :: out: 15, RDval: 14, RSval: -1
bnez :: out: 16, RDval: 15, RSval: -1
j, jal, jr
J JAL JR :: 6, RSval: 0
J JAL JR :: 7, RSval: 1
J JAL JR :: 8, RSval: 2
J JAL JR :: 9, RSval: 3
J JAL JR :: 10, RSval: 4
J JAL JR :: 11, RSval: 5
J JAL JR :: 12, RSval: 6
J JAL JR :: 13, RSval: 7
J JAL JR :: 14, RSval: 8
J JAL JR :: 15, RSval: 9
J JAL JR :: 16, RSval: 10
J JAL JR :: 17, RSval: 11
J JAL JR :: 18, RSval: 12
J JAL JR :: 19, RSval: 13
J JAL JR :: 20, RSval: 14
J JAL JR :: 21, RSval: 15
J JAL JR :: 22, RSval: 16
J JAL JR :: 23, RSval: 17
J JAL JR :: 24, RSval: 18
J JAL JR :: 25, RSval: 19
J JAL JR :: 26, RSval: 20
J JAL JR :: 27, RSval: 21
J JAL JR :: 28, RSval: 22
J JAL JR :: 29, RSval: 23
j, jalr, jr
J JALR JR :: 6, RSval: 0
J JALR JR :: 7, RSval: 1
J JALR JR :: 8, RSval: 2
J JALR JR :: 9, RSval: 3
J JALR JR :: 10, RSval: 4
J JALR JR :: 11, RSval: 5
J JALR JR :: 12, RSval: 6
J JALR JR :: 13, RSval: 7
J JALR JR :: 14, RSval: 8
J JALR JR :: 15, RSval: 9
J JALR JR :: 17, RSval: 11
J JALR JR :: 18, RSval: 12
J JALR JR :: 19, RSval: 13
J JALR JR :: 20, RSval: 14
J JALR JR :: 21, RSval: 15
J JALR JR :: 22, RSval: 16
J JALR JR :: 23, RSval: 17
J JALR JR :: 24, RSval: 18
J JALR JR :: 25, RSval: 19
J JALR JR :: 26, RSval: 20
J JALR JR :: 27, RSval: 21
J JALR JR :: 28, RSval: 22
J JALR JR :: 29, RSval: 23

1
none/tests/mips64/branches_r6.c Symbolic link
View File

@ -0,0 +1 @@
../mips32/branches_r6.c

1
none/tests/mips64/branches_r6.stderr.exp Symbolic link
View File

@ -0,0 +1 @@
../mips32/branches_r6.stderr.exp

1
none/tests/mips64/branches_r6.stdout.exp Symbolic link
View File

@ -0,0 +1 @@
../mips32/branches_r6.stdout.exp

1
none/tests/mips64/branches_r6.vgtest Symbolic link
View File

@ -0,0 +1 @@
../mips32/branches_r6.vgtest

3
none/tests/mips64/change_fp_mode.c
View File

@ -155,7 +155,7 @@ static void fatal_error(const char* msg) {
}
static void test(int* fr_prctl, int* fr_detected) {
#if (__mips_isa_rev<6)
*fr_prctl = prctl(PR_GET_FP_MODE);
*fr_detected = get_fp_mode();
@ -232,6 +232,7 @@ static void test(int* fr_prctl, int* fr_detected) {
TEST_MOVE("movz.d $f0, $f2, $0");
TEST_MOVE("movz.d $f0, $f1, $0");
TEST_MOVE("movz.d $f1, $f2, $0");
#endif
}
int main() {

2
none/tests/mips64/change_fp_mode.vgtest
View File

@ -1,3 +1,3 @@
prog: change_fp_mode
prereq: ../../../tests/mips_features fpu
prereq: ../../../tests/mips_features fpu && !(../../../tests/mips_features mipsr6)
vgopts: -q

1
none/tests/mips64/fp_r6.c Symbolic link
View File

@ -0,0 +1 @@
../mips32/fp_r6.c

1
none/tests/mips64/fp_r6.stderr.exp Symbolic link
View File

@ -0,0 +1 @@
../mips32/fp_r6.stderr.exp

1
none/tests/mips64/fp_r6.stdout.exp Symbolic link
View File

@ -0,0 +1 @@
../mips32/fp_r6.stdout.exp

1
none/tests/mips64/fp_r6.vgtest Symbolic link
View File

@ -0,0 +1 @@
../mips32/fp_r6.vgtest

10
none/tests/mips64/fpu_arithmetic.c
View File

@ -106,6 +106,7 @@ int arithmeticOperations(flt_art_op_t op)
flt_art_op_names[op], round(fd_d), fs_d[i]);
}
break;
#if (__mips_isa_rev < 6)
case MSUBS:
TRIOPf("msub.s");
printf("%s %f %f %f %f\n",flt_art_op_names[op], roundf(fd_f),
@ -147,6 +148,7 @@ int arithmeticOperations(flt_art_op_t op)
round(fd_d), fr_d[i], fs_d[i],
ft_d[i]);
break;
#endif
default:
printf("error\n");
break;
@ -161,10 +163,14 @@ int main()
{
#if defined(__mips_hard_float)
flt_art_op_t op;
#if (__mips_isa_rev < 6)
int end = NMSUBD;
#else
int end = RSQRTD;
#endif
printf("-------------------------- %s --------------------------\n",
"test FPU Arithmetic Operations");
for (op = ABSS; op <= NMSUBD; op++) {
for (op = ABSS; op <= end; op++) {
arithmeticOperations(op);
}
#endif

1729
none/tests/mips64/fpu_arithmetic.stdout.exp-r6 Normal file
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File diff suppressed because it is too large Load Diff

2
none/tests/mips64/fpu_branches.c
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@ -3,7 +3,7 @@
int main()
{
#if defined(__mips_hard_float)
#if defined(__mips_hard_float) && (__mips_isa_rev < 6)
int i = 0;
printf("--- BC1F --- if fs == ft then " \

2
none/tests/mips64/fpu_branches.vgtest
View File

@ -1,3 +1,3 @@
prog: fpu_branches
prereq: ../../../tests/mips_features fpu
prereq: ../../../tests/mips_features fpu && !(../../../tests/mips_features mipsr6)
vgopts: -q

19
none/tests/mips64/fpu_load_store.c
View File

@ -18,12 +18,6 @@ int main()
for (i = 0; i < N*s2; i = i+8)
TEST3("ldc1", i, reg_val2);
printf("--- LDXC1 ---\n");
for (i = 0; i < N*s1; i = i+8)
TEST5("ldxc1", i, reg_val1);
for (i = 0; i < N*s2; i = i+8)
TEST5("ldxc1", i, reg_val2);
printf("--- LWC1 ---\n");
for (i = 0; i < N*s1; i = i+4)
@ -32,13 +26,21 @@ int main()
for (i = 0; i < N*s2; i = i+4)
TEST3w("lwc1", i, reg_val2);
#if (__mips_isa_rev < 6)
printf("--- LDXC1 ---\n");
for (i = 0; i < N*s1; i = i+8)
TEST5("ldxc1", i, reg_val1);
for (i = 0; i < N*s2; i = i+8)
TEST5("ldxc1", i, reg_val2);
printf("--- LWXC1 ---\n");
for (i = 0; i < N*s1; i = i+4)
TEST5w("lwxc1", i, reg_val1);
for (i = 0; i < N*s2; i = i+4)
TEST5w("lwxc1", i, reg_val2);
#endif
/**********************************************************************/
/*-------------------------------STORE--------------------------------*/
/**********************************************************************/
@ -53,7 +55,7 @@ int main()
for (i = 0; i < (N-1)*s1; i = i+4) {
TEST4("swc1", i);
}
#if (__mips_isa_rev < 6)
init_reg_val_zero();
printf("--- SDXC1 ---\n");
for (i = 0; i < N*s1; i = i+8) {
@ -65,6 +67,7 @@ int main()
for (i = 0; i < (N-1)*s1; i = i+4) {
TEST6("swxc1", i);
}
#endif
#endif
return 0;

3078
none/tests/mips64/fpu_load_store.stdout.exp-BE-r2 Normal file
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File diff suppressed because it is too large Load Diff

1539
none/tests/mips64/fpu_load_store.stdout.exp-BE-r6 Normal file
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File diff suppressed because it is too large Load Diff

3078
none/tests/mips64/fpu_load_store.stdout.exp-LE-r2 Normal file
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File diff suppressed because it is too large Load Diff

1539
none/tests/mips64/fpu_load_store.stdout.exp-LE-r6 Normal file
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File diff suppressed because it is too large Load Diff

12
none/tests/mips64/load_store.c
View File

@ -31,6 +31,7 @@ int main()
for (i = 0; i < N*s2; i = i+8)
TEST1("ld", i, reg_val2);
#if (__mips_isa_rev < 6)
/* ldl */
for (i = 0; i < N*s1; i++)
TEST1("ldl", i, reg_val1);
@ -44,6 +45,7 @@ int main()
for (i = 0; i < N*s2; i++)
TEST1("ldr", i, reg_val2);
#endif
/* lh */
for (i = 0; i < N*s1; i = i+2)
@ -66,6 +68,7 @@ int main()
for (i = 0; i < N*s2; i = i+4)
TEST1("lw", i, reg_val2);
#if (__mips_isa_rev < 6)
/* lwl */
for (i = 0; i < N*s1; i++)
TEST1("lwl", i, reg_val1);
@ -79,7 +82,7 @@ int main()
for (i = 0; i < N*s2; i++)
TEST1("lwr", i, reg_val2);
#endif
/* lwu */
for (i = 0; i < N*s1; i = i+4)
TEST1("lwu", i, reg_val1);
@ -100,6 +103,7 @@ int main()
for (i = 0; i < (N-1)*s2; i = i+8)
TEST2("sd", i);
#if (__mips_isa_rev < 6)
init_reg_val_zero();
/* sdl */
for (i = 0; i < (N-1)*s2; i++)
@ -109,7 +113,7 @@ int main()
/* sdr */
for (i = 8; i < (N-1)*s2; i++)
TEST2("sdr", i);
#endif
init_reg_val_zero();
/* sh */
for (i = 0; i < (N-1)*s2; i = i+2)
@ -121,6 +125,8 @@ int main()
TEST2("sw", i);
init_reg_val_zero();
#if (__mips_isa_rev < 6)
/* swl */
for (i = 4; i < (N-1)*s2; i++)
TEST2("swl", i);
@ -129,6 +135,6 @@ int main()
/* swr */
for (i = 4; i < (N-1)*s2; i++)
TEST2("swr", i);
#endif
return 0;
}

14961
none/tests/mips64/load_store.stdout.exp-BE-r6 Normal file
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File diff suppressed because it is too large Load Diff

14961
none/tests/mips64/load_store.stdout.exp-LE-r6 Normal file
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File diff suppressed because it is too large Load Diff

4
none/tests/mips64/load_store_multiple.c
View File

@ -50,6 +50,7 @@ unsigned int mem2[] = {
/* swl $t0, 3($t1)
swr $t0, 0($t1) */
#if (__mips_isa_rev < 6)
#define TESTINSTsw(RTval, offset, RT, RS) \
{ \
unsigned int out; \
@ -67,6 +68,7 @@ unsigned int mem2[] = {
printf("swl $t0, 3($t1)\nswr $t0, 0($t1)\n :: RTval: 0x%x, out: 0x%x\n", \
RTval, out); \
}
#endif
void ppMem(unsigned int* m, int len)
{
@ -217,6 +219,7 @@ int main()
ppMem(mem1, 16);
ppMem1(mem, 16);
#if (__mips_isa_rev < 6)
printf("swl\n");
TESTINST1("swl $t0, 1($t1)", 0, 1, t0, t1);
TESTINST1("swl $t0, 3($t1)", 0x31415927, 3, t0, t1);
@ -344,6 +347,7 @@ int main()
ppMem2(mem2, 12);
TESTINSTsw(0x2aaee700, 32, t0, t1);
ppMem2(mem2, 12);
#endif
return 0;
}

171
none/tests/mips64/load_store_multiple.stdout.exp-BE-r6 Normal file
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@ -0,0 +1,171 @@
sb
sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27000000
sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27000000
sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff000000
sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff000000
sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x1e0000
sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27
sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27
sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xff000000
sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff
sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27000000
sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f000000
sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f000000
sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71000000
sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71000000
sb $t0, 0($t1) :: RTval: 0xf, out: 0xf000000
sb $t0, 0($t1) :: RTval: 0xf, out: 0xf000000
sb $t0, 0($t1) :: RTval: 0x1, out: 0x1000000
sb $t0, 0($t1) :: RTval: 0x1, out: 0x1000000
sb $t0, 0($t1) :: RTval: 0x35, out: 0x35000000
sb $t0, 0($t1) :: RTval: 0x35, out: 0x35000000
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff000027
sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0xff3f343f
sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff000000
sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff3e353d
sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x27000000
sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x273c3b3b
sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0xff000000
sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0xff3b3b37
sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x3b3a45
sb $t0, 51($t1) :: RTval: 0x28f, out: 0x8f000000
sb $t0, 51($t1) :: RTval: 0x28f, out: 0x8f4e464d
MEM1:
0x3500ff00, 0x27ffff, 0xff0000ff, 0x0
0x0, 0x0, 0x0, 0xff
0xffffffff, 0x0, 0x27ff00, 0x0
0x8f, 0x0, 0x0, 0x0
MEM:
0x3500ff00, 0x27ffff, 0xff0000ff, 0xffffffff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2dff
0x3f343fff, 0x3e353d3c, 0x3627ff3b, 0x3b003b3a
0x454f4e8f, 0x4e464d46, 0x474d474c, 0x4a484a4c
sh
sh $t0, 1($t1) :: RTval: 0x0, out: 0x0
sh $t0, 1($t1) :: RTval: 0x0, out: 0x1f00
sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x59270000
sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x59270000
sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 9($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 9($t1) :: RTval: 0x80000000, out: 0x3ff
sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffff00ff
sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffff00ff
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270059
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x59270059
sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x59
sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x59
sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0059
sh $t0, 0($t1) :: RTval: 0x28f, out: 0x28f0059
sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710059
sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfd710059
sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0059
sh $t0, 0($t1) :: RTval: 0xf, out: 0xf0059
sh $t0, 0($t1) :: RTval: 0x1, out: 0x10059
sh $t0, 0($t1) :: RTval: 0x1, out: 0x10059
sh $t0, 0($t1) :: RTval: 0x35, out: 0x350059
sh $t0, 0($t1) :: RTval: 0x35, out: 0x350059
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffff27ff
sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffff0000
sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffff343f
sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0xffff0000
sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0xffff353d
sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x59270000
sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x59273b3b
sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xffff0000
sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xffff4f4e
sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x454e
sh $t0, 51($t1) :: RTval: 0x28f, out: 0x28f0000
sh $t0, 51($t1) :: RTval: 0x28f, out: 0x28f464d
MEM1:
0x35ffff, 0x27ffffff, 0xffff00ff, 0xff000000
0x0, 0x0, 0x0, 0xff
0xff0000ff, 0xff000000, 0x592700, 0xff
0xff000002, 0x8f000000, 0x0, 0x0
MEM:
0x35ffff, 0x27ffffff, 0xffff00ff, 0xffffffff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0x262d2dff
0xff343fff, 0xff353d3c, 0x3659273b, 0x3b373bff
0xff000002, 0x8f464d46, 0x474d474c, 0x4a484a4c
sw
sw $t0, 1($t1) :: RTval: 0x0, out: 0x0
sw $t0, 1($t1) :: RTval: 0x0, out: 0x0
sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0x0
sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0xffff
sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
MEM1:
0xffff, 0xffff7fff, 0xffffffff, 0x7f
0xffffff00, 0x0, 0x0, 0xff
0xffffff00, 0xffffff, 0xff7fff80, 0x0
0x314100, 0x28f00, 0x0, 0x0
MEM:
0xffff, 0xffff7fff, 0xffffffff, 0xffff7f
0xffffff2f, 0x242c2b2b, 0x252a2e2b, 0x262d2dff
0xffffff3e, 0x3effffff, 0xff7fff80, 0x3a
0x45314100, 0x28f46, 0x474d474c, 0x4a484a4c

171
none/tests/mips64/load_store_multiple.stdout.exp-LE-r6 Normal file
View File

@ -0,0 +1,171 @@
sb
sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
sb $t0, 3($t1) :: RTval: 0x0, out: 0x0
sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x27
sb $t0, 5($t1) :: RTval: 0x31415927, out: 0x3000027
sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0xff
sb $t0, 7($t1) :: RTval: 0x7fffffff, out: 0x3ff
sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 1($t1) :: RTval: 0x80000000, out: 0x1f00
sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27000000
sb $t0, 2($t1) :: RTval: 0x80000000, out: 0x27000000
sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff
sb $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x3ffff
sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xff
sb $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff
sb $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff0000ff
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27
sb $t0, 0($t1) :: RTval: 0x31415927, out: 0x27
sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sb $t0, 0($t1) :: RTval: 0xdd00000, out: 0x0
sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f
sb $t0, 0($t1) :: RTval: 0x28f, out: 0x8f
sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71
sb $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x71
sb $t0, 0($t1) :: RTval: 0xf, out: 0xf
sb $t0, 0($t1) :: RTval: 0xf, out: 0xf
sb $t0, 0($t1) :: RTval: 0x1, out: 0x1
sb $t0, 0($t1) :: RTval: 0x1, out: 0x1
sb $t0, 0($t1) :: RTval: 0x35, out: 0x35
sb $t0, 0($t1) :: RTval: 0x35, out: 0x35
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff
sb $t0, 2($t1) :: RTval: 0xffffffff, out: 0x270000ff
sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
sb $t0, 31($t1) :: RTval: 0xffffffff, out: 0x343f3eff
sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0xff
sb $t0, 35($t1) :: RTval: 0xffffffff, out: 0x353d3cff
sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x27
sb $t0, 41($t1) :: RTval: 0x31415927, out: 0x3a363a27
sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0xff
sb $t0, 42($t1) :: RTval: 0x7fffffff, out: 0x3b3a36ff
sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x0
sb $t0, 45($t1) :: RTval: 0x80000000, out: 0x453b3700
sb $t0, 51($t1) :: RTval: 0x28f, out: 0x8f
sb $t0, 51($t1) :: RTval: 0x28f, out: 0x464d468f
MEM1:
0xff0035, 0xffff2700, 0xff0000ff, 0x0
0x0, 0x0, 0x0, 0xff000000
0xffffffff, 0x0, 0xff2700, 0x0
0x8f000000, 0x0, 0x0, 0x0
MEM:
0xff0035, 0xffff2700, 0xff0000ff, 0xffffffff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0xff2d2d2a
0xff343f3e, 0x3e353d3c, 0x36ff273b, 0x3b37003a
0x8f4f4e45, 0x4e464d46, 0x474d474c, 0x4a484a4c
sh
sh $t0, 1($t1) :: RTval: 0x0, out: 0x0
sh $t0, 1($t1) :: RTval: 0x0, out: 0x120000
sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x5927
sh $t0, 3($t1) :: RTval: 0x31415927, out: 0x5927
sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x300ffff
sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 7($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 9($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 9($t1) :: RTval: 0x80000000, out: 0xff000000
sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 6($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 11($t1) :: RTval: 0x7fffffff, out: 0xffffffff
sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ffff
sh $t0, 8($t1) :: RTval: 0xffffffff, out: 0xff00ffff
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x27005927
sh $t0, 0($t1) :: RTval: 0x31415927, out: 0x27005927
sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x27000000
sh $t0, 0($t1) :: RTval: 0xdd00000, out: 0x27000000
sh $t0, 0($t1) :: RTval: 0x28f, out: 0x2700028f
sh $t0, 0($t1) :: RTval: 0x28f, out: 0x2700028f
sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x2700fd71
sh $t0, 0($t1) :: RTval: 0xfffffd71, out: 0x2700fd71
sh $t0, 0($t1) :: RTval: 0xf, out: 0x2700000f
sh $t0, 0($t1) :: RTval: 0xf, out: 0x2700000f
sh $t0, 0($t1) :: RTval: 0x1, out: 0x27000001
sh $t0, 0($t1) :: RTval: 0x1, out: 0x27000001
sh $t0, 0($t1) :: RTval: 0x35, out: 0x27000035
sh $t0, 0($t1) :: RTval: 0x35, out: 0x27000035
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff
sh $t0, 2($t1) :: RTval: 0xffffffff, out: 0xff59ffff
sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffff
sh $t0, 31($t1) :: RTval: 0xffffffff, out: 0x343fffff
sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0xffff
sh $t0, 35($t1) :: RTval: 0xffffffff, out: 0x353dffff
sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x5927
sh $t0, 41($t1) :: RTval: 0x31415927, out: 0x3a365927
sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0xffff
sh $t0, 47($t1) :: RTval: 0x7fffffff, out: 0x4f4effff
sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x0
sh $t0, 49($t1) :: RTval: 0x80000000, out: 0x46450000
sh $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
sh $t0, 51($t1) :: RTval: 0x28f, out: 0x464d028f
MEM1:
0xffff0035, 0xffffff59, 0xff00ffff, 0xff
0x0, 0x0, 0x0, 0xff000000
0xff0000ff, 0xff, 0x592700, 0xff000000
0x8f0000ff, 0x2, 0x0, 0x0
MEM:
0xffff0035, 0xffffff59, 0xff00ffff, 0xffffffff
0x232f2e2f, 0x242c2b2b, 0x252a2e2b, 0xff2d2d2a
0xff343fff, 0x3e353dff, 0x3659273b, 0xff373b3a
0x8f0000ff, 0x4e464d02, 0x474d474c, 0x4a484a4c
sw
sw $t0, 1($t1) :: RTval: 0x0, out: 0x0
sw $t0, 1($t1) :: RTval: 0x0, out: 0x0
sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 3($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 5($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 7($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 9($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 6($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0x8000
sw $t0, 15($t1) :: RTval: 0x7fffffff, out: 0xffff8000
sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 8($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
sw $t0, 0($t1) :: RTval: 0xdd00000, out: 0xdd00000
sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 0($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
sw $t0, 0($t1) :: RTval: 0xfffffd71, out: 0xfffffd71
sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
sw $t0, 0($t1) :: RTval: 0xf, out: 0xf
sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
sw $t0, 0($t1) :: RTval: 0x1, out: 0x1
sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
sw $t0, 0($t1) :: RTval: 0x35, out: 0x35
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 2($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 31($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 37($t1) :: RTval: 0xffffffff, out: 0xffffffff
sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 49($t1) :: RTval: 0x31415927, out: 0x31415927
sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 41($t1) :: RTval: 0x7fffffff, out: 0x7fffffff
sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 43($t1) :: RTval: 0x80000000, out: 0x80000000
sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
sw $t0, 51($t1) :: RTval: 0x28f, out: 0x28f
MEM1:
0xffff0035, 0xffffffff, 0xffffffff, 0xff000080
0x7fffff, 0x0, 0x0, 0xff000000
0xffffff, 0xffffff00, 0xffffff, 0x800000
0x8f592700, 0x2, 0x0, 0x0
MEM:
0xffff0035, 0xffffffff, 0xffffffff, 0xffffff80
0x237fffff, 0x242c2b2b, 0x252a2e2b, 0xff2d2d2a
0x3fffffff, 0xffffff3c, 0xffffff, 0x3b800000
0x8f592745, 0x4e000002, 0x474d474c, 0x4a484a4c

2
none/tests/mips64/load_store_unaligned.c
View File

@ -26,6 +26,7 @@ int main()
#if defined(__mips_hard_float)
int i, index;
unsigned long long outLoad;
#if (__mips_isa_rev < 6)
for (i = 0; i < N * SOLL; i++) {
outLoad = 0;
__asm__ __volatile__(
@ -43,6 +44,7 @@ int main()
printf("i: %d, memSrc[%d]: 0x%llx, memDst[%d]: 0x%llx, outLoad: 0x%llx\n",
i, index, memSrc[index], index, memDst[index], outLoad);
}
#endif
#endif
return 0;
}

2
none/tests/mips64/load_store_unaligned.vgtest
View File

@ -1,3 +1,3 @@
prog: load_store_unaligned
prereq: ../../../tests/mips_features fpu
prereq: ../../../tests/mips_features fpu && !(../../../tests/mips_features mipsr6)
vgopts: -q

8
none/tests/mips64/macro_fpu.h
View File

@ -5,9 +5,11 @@ typedef enum {
DIVS, DIVD, MULS, MULD,
NEGS, NEGD, SQRTS, SQRTD,
SUBS, SUBD, RECIPS, RECIPD,
RSQRTS, RSQRTD, MSUBS, MSUBD,
MADDS, MADDD, NMADDS, NMADDD,
NMSUBS, NMSUBD
RSQRTS, RSQRTD,
#if (__mips_isa_rev < 6)
MSUBS, MSUBD, MADDS, MADDD,
NMADDS, NMADDD, NMSUBS, NMSUBD
#endif
} flt_art_op_t;
typedef enum {

7
none/tests/mips64/move_instructions.c
View File

@ -88,7 +88,7 @@ const double fs2_f[] = {
printf("dmtc1, mov.d, dmfc1 :: mem: 0x%llx out: 0x%llx\n", \
(long long)mem, out); \
}
#if (__mips_isa_rev < 6)
/* movX.s fd, fs */
#define TEST3(instruction, FD, FS, cc, offset) \
{ \
@ -135,6 +135,7 @@ const double fs2_f[] = {
printf("%s :: out: 0x%llx, cc: %d\n", \
instruction, out, cc); \
}
#endif
/* movX.s fd, fs, rt */
#define TEST4(instruction, offset, RTval, FD, FS, RT) \
@ -174,6 +175,7 @@ const double fs2_f[] = {
printf("%s :: out: 0x%llx\n", instruction, out); \
}
#if (__mips_isa_rev < 6)
/* movf, movt */
#define TEST5(instruction, RDval, RSval, RD, RS) \
{ \
@ -192,6 +194,7 @@ const double fs2_f[] = {
instruction, RDval, RSval, out); \
}
#endif
#endif
int main()
{
@ -206,6 +209,7 @@ int main()
TEST2(reg_val2[i]);
}
#if (__mips_isa_rev < 6)
printf("--- MOVF.S ---\n");
TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 0);
TEST3("movf.s $f4, $f6, $fcc0", f4, f6, 1, 8);
@ -369,6 +373,7 @@ int main()
TEST5("movt", 0x5555ffff, 0xffffffff, t3, t1);
TEST5("movt", 0xeeeeeeee, 0xffffeeee, t3, t0);
}
#endif
#endif
return 0;
}

1024
none/tests/mips64/move_instructions.stdout.exp-r6 Normal file
View File

File diff suppressed because it is too large Load Diff

1
none/tests/mips64/pc_instructions_r6.c Symbolic link
View File

@ -0,0 +1 @@
../mips32/pc_instructions_r6.c

1
none/tests/mips64/pc_instructions_r6.stderr.exp Symbolic link
View File

@ -0,0 +1 @@
../mips32/pc_instructions_r6.stderr.exp

39
none/tests/mips64/pc_instructions_r6.stdout.exp Normal file
View File

@ -0,0 +1,39 @@
addiupc
addiupc :: out - ra 0, RSval 0x00000000
addiupc :: out - ra 4, RSval 0x00000004
addiupc :: out - ra 10, RSval 0x00000010
addiupc :: out - ra 40, RSval 0x00000040
addiupc :: out - ra 100, RSval 0x00000100
addiupc :: out - ra 400, RSval 0x00000400
addiupc :: out - ra 1000, RSval 0x00001000
addiupc :: out - ra 4000, RSval 0x00004000
aluipc
aluipc :: out - ra 20000000, RSval 0x00000000
aluipc :: out - ra 20040000, RSval 0x00000004
aluipc :: out - ra 20100000, RSval 0x00000010
aluipc :: out - ra 20400000, RSval 0x00000040
aluipc :: out - ra 21000000, RSval 0x00000100
aluipc :: out - ra 24000000, RSval 0x00000400
aluipc :: out - ra 30000000, RSval 0x00001000
aluipc :: out - ra 60000000, RSval 0x00004000
auipc
auipc :: out - ra 0, RSval 0x00000000
auipc :: out - ra 40000, RSval 0x00000004
auipc :: out - ra 100000, RSval 0x00000010
auipc :: out - ra 400000, RSval 0x00000040
auipc :: out - ra 1000000, RSval 0x00000100
auipc :: out - ra 4000000, RSval 0x00000400
auipc :: out - ra 10000000, RSval 0x00001000
auipc :: out - ra 40000000, RSval 0x00004000
lwpc
lwpc :: out: 0x25
lwpc :: out: 0x25
lwpc :: out: 0x25
lwpc :: out: 0x25
lwpc :: out: 0x25
lwpc :: out: 0x25
lwpc :: out: 0x25
lwpc :: out: 0x25

1
none/tests/mips64/pc_instructions_r6.vgtest Symbolic link
View File

@ -0,0 +1 @@
../mips32/pc_instructions_r6.vgtest

355
none/tests/mips64/r6_instructions.c Normal file
View File

@ -0,0 +1,355 @@
#include <stdio.h>
unsigned long long mem[] = { 0x3FF0000000000001ULL, 0x3FF0000000000000ULL,
0x00000000ffffffffULL, 0x1234563388994400ULL,
0x0000004412369801ULL, 0x111111eeeeeee220ULL,
0xAAAAABBBBBCCCDDDULL, 0xaa55cc2266dd2200ULL,
0x3FF0045698720001ULL, 0x3FF0000000000000ULL,
0x00000000ffffffffULL, 0x0007200059762458ULL,
0xaa55c200abcdefabULL, 0x852369741afedbc6ULL };
#define TEST1(instruction, RD, RS, RT, RSval, RTval) \
{ \
unsigned long long result; \
__asm__ volatile ( \
"move $"#RS", %1\n\t" \
"move $"#RT", %2\n\t" \
instruction" $"#RD", $"#RS", $"#RT", 1\n\t" \
"move %0, $"#RD"\n\t" \
: "=&r"(result) \
: "r"(RSval), "r"(RTval) \
: #RD, #RS, #RT, "memory" \
); \
printf(instruction":: %llx\n", result); \
}
#define TEST2(instruction, RS, RT, RSval, RTval) \
{ \
unsigned long long result; \
__asm__ volatile ( \
"move $"#RS", %1\n\t" \
"move $"#RT", %2\n\t" \
instruction" $"#RS", $"#RT", 1\n\t" \
"move %0, $"#RS"\n\t" \
: "=&r"(result) \
: "r"(RSval), "r"(RTval) \
: #RS, #RT, "memory" \
); \
printf(instruction":: %llx\n", result); \
}
#define TEST3(instruction, RS, RSval) \
{ \
unsigned long long result; \
__asm__ volatile ( \
"move $"#RS", %1\n\t" \
instruction" $"#RS", $"#RS", 1\n\t" \
"move %0, $"#RS"\n\t" \
: "=&r"(result) \
: "r"(RSval) \
: #RS, "memory" \
); \
printf(instruction":: %llx\n", result); \
}
#define TEST4(instruction, RS, RT, RSval, RTval) \
{ \
unsigned long long result; \
__asm__ volatile ( \
"move $"#RS", %1\n\t" \
"move $"#RT", %2\n\t" \
instruction" $"#RS", $"#RT" \n\t" \
"move %0, $"#RS"\n\t" \
: "=&r"(result) \
: "r"(RSval), "r"(RTval) \
: #RS, #RT, "memory" \
); \
printf(instruction":: %llx\n", result); \
}
#define TEST5(instruction, RD, RS, RT, RSval, RTval) \
{ \
unsigned long long result; \
__asm__ volatile ( \
"move $"#RS", %1\n\t" \
"move $"#RT", %2\n\t" \
instruction" $"#RD", $"#RS", $"#RT" \n\t" \
"move %0, $"#RD"\n\t" \
: "=&r"(result) \
: "r"(RSval), "r"(RTval) \
: #RD, #RS, #RT, "memory" \
); \
printf(instruction":: %llx\n", result); \
}
#define TEST6(instruction, RSval, RD) \
{ \
unsigned long long out = 0; \
__asm__ __volatile__( \
".set push \n\t" \
".set noreorder \n\t" \
"lbl"instruction#RSval ": \n\t" \
"or $0, $0, $0 \n\t" \
"and $0, $0, $0 \n\t" \
instruction" $"#RD ", lbl"instruction#RSval "\n\t" \
"move %0, $"#RD "\n\t" \
".set pop \n\t" \
: "=r" (out) \
: \
: "t0", "t1" \
); \
printf("%s :: out: 0x%llx\n", instruction, out); \
}
int main() {
#if (__mips_isa_rev>=6)
printf("dalign\n");
TEST1("dalign" , t0, t1, t2, mem[0], 0);
TEST1("dalign" , t1, t2, t3, mem[1], 1);
TEST1("dalign" , t2, t3, v0, mem[2], 2);
TEST1("dalign" , t3, v0, v1, mem[3], 3);
TEST1("dalign" , v0, v1, a0, mem[4], 4);
TEST1("dalign" , v1, a0, a1, mem[5], 5);
TEST1("dalign" , a0, a1, a2, mem[6], 6);
TEST1("dalign" , a1, a2, a3, mem[7], 7);
TEST1("dalign" , s0, s1, s2, mem[8], 8);
TEST1("dalign" , s1, s2, s3, mem[9], 9);
TEST1("dalign" , s2, s3, s4, mem[10], 10);
TEST1("dalign" , s3, s4, s5, mem[11], 11);
TEST1("dalign" , s4, s5, s6, mem[12], 12);
TEST1("dalign" , s5, s6, s7, mem[13], 13);
printf("\ndaui\n");
TEST2("daui" , t0, t1, mem[0], 0);
TEST2("daui" , t1, t2, mem[1], 1);
TEST2("daui" , t2, t3, mem[2], 2);
TEST2("daui" , t3, v0, mem[3], 3);
TEST2("daui" , v0, v1, mem[4], 4);
TEST2("daui" , v1, a0, mem[5], 5);
TEST2("daui" , a0, a1, mem[6], 6);
TEST2("daui" , a1, a2, mem[7], 7);
TEST2("daui" , a2, a3, mem[8], 8);
TEST2("daui" , s0, s1, mem[9], 9);
TEST2("daui" , s2, s3, mem[10], 10);
TEST2("daui" , s3, s4, mem[11], 11);
TEST2("daui" , s4, s5, mem[12], 12);
TEST2("daui" , s5, s6, mem[13], 13);
printf("\ndahi\n");
TEST3("dahi" , t0, mem[0]);
TEST3("dahi" , t1, mem[1]);
TEST3("dahi" , t2, mem[2]);
TEST3("dahi" , t3, mem[3]);
TEST3("dahi" , v0, mem[4]);
TEST3("dahi" , v1, mem[5]);
TEST3("dahi" , a0, mem[6]);
TEST3("dahi" , a1, mem[7]);
TEST3("dahi" , a2, mem[8]);
TEST3("dahi" , a3, mem[9]);
TEST3("dahi" , s0, mem[10]);
TEST3("dahi" , s1, mem[11]);
TEST3("dahi" , s2, mem[12]);
TEST3("dahi" , s3, mem[13]);
printf("\ndati\n");
TEST3("dati" , t0, mem[0]);
TEST3("dati" , t1, mem[1]);
TEST3("dati" , t2, mem[2]);
TEST3("dati" , t3, mem[3]);
TEST3("dati" , v0, mem[4]);
TEST3("dati" , v1, mem[5]);
TEST3("dati" , a0, mem[6]);
TEST3("dati" , a1, mem[7]);
TEST3("dati" , a2, mem[8]);
TEST3("dati" , a3, mem[9]);
TEST3("dati" , s0, mem[10]);
TEST3("dati" , s1, mem[11]);
TEST3("dati" , s2, mem[12]);
TEST3("dati" , s3, mem[13]);
printf("\ndbitswap\n");
TEST4("dbitswap" , t0, t1, mem[0], 0);
TEST4("dbitswap" , t1, t2, mem[1], 1);
TEST4("dbitswap" , t2, t3, mem[2], 2);
TEST4("dbitswap" , t3, v0, mem[3], 3);
TEST4("dbitswap" , v0, v1, mem[4], 4);
TEST4("dbitswap" , v1, a0, mem[5], 5);
TEST4("dbitswap" , a0, a1, mem[6], 6);
TEST4("dbitswap" , a1, a2, mem[7], 7);
TEST4("dbitswap" , a2, a3, mem[8], 8);
TEST4("dbitswap" , a3, s0, mem[9], 9);
TEST4("dbitswap" , s0, s1, mem[10], 10);
TEST4("dbitswap" , s1, s2, mem[11], 11);
TEST4("dbitswap" , s2, s3, mem[12], 12);
TEST4("dbitswap" , s3, s4, mem[13], 13);
printf("\nddiv\n");
TEST5("ddiv" , t0, t1, t2, mem[0], mem[1]);
TEST5("ddiv" , t1, t2, t3, mem[1], mem[2]);
TEST5("ddiv" , t2, t3, v0, mem[2], mem[3]);
TEST5("ddiv" , t3, v0, v1, mem[3], mem[4]);
TEST5("ddiv" , v0, v1, a0, mem[4], mem[5]);
TEST5("ddiv" , v1, a0, a1, mem[5], mem[6]);
TEST5("ddiv" , a0, a1, a2, mem[6], mem[7]);
TEST5("ddiv" , a1, a2, a3, mem[7], mem[8]);
TEST5("ddiv" , a2, a3, s0, mem[8], mem[9]);
TEST5("ddiv" , a3, s0, s1, mem[9], mem[10]);
TEST5("ddiv" , s0, s1, s2, mem[10], mem[11]);
TEST5("ddiv" , s2, s3, s4, mem[11], mem[12]);
TEST5("ddiv" , s3, s4, s5, mem[12], mem[13]);
TEST5("ddiv" , s4, s5, s6, mem[13], mem[0]);
printf("\ndmod\n");
TEST5("dmod" , t0, t1, t2, mem[0], mem[1]);
TEST5("dmod" , t1, t2, t3, mem[1], mem[2]);
TEST5("dmod" , t2, t3, v0, mem[2], mem[3]);
TEST5("dmod" , t3, v0, v1, mem[3], mem[4]);
TEST5("dmod" , v0, v1, a0, mem[4], mem[5]);
TEST5("dmod" , v1, a0, a1, mem[5], mem[6]);
TEST5("dmod" , a0, a1, a2, mem[6], mem[7]);
TEST5("dmod" , a1, a2, a3, mem[7], mem[8]);
TEST5("dmod" , a2, a3, s0, mem[8], mem[9]);
TEST5("dmod" , a3, s0, s1, mem[9], mem[10]);
TEST5("dmod" , s0, s1, s2, mem[10], mem[11]);
TEST5("dmod" , s2, s3, s4, mem[11], mem[12]);
TEST5("dmod" , s3, s4, s5, mem[12], mem[13]);
TEST5("dmod" , s4, s5, s6, mem[13], mem[0]);
printf("\nddivu\n");
TEST5("ddivu" , t0, t1, t2, mem[0], mem[1]);
TEST5("ddivu" , t1, t2, t3, mem[1], mem[2]);
TEST5("ddivu" , t2, t3, v0, mem[2], mem[3]);
TEST5("ddivu" , t3, v0, v1, mem[3], mem[4]);
TEST5("ddivu" , v0, v1, a0, mem[4], mem[5]);
TEST5("ddivu" , v1, a0, a1, mem[5], mem[6]);
TEST5("ddivu" , a0, a1, a2, mem[6], mem[7]);
TEST5("ddivu" , a1, a2, a3, mem[7], mem[8]);
TEST5("ddivu" , a2, a3, s0, mem[8], mem[9]);
TEST5("ddivu" , a3, s0, s1, mem[9], mem[10]);
TEST5("ddivu" , s0, s1, s2, mem[10], mem[11]);
TEST5("ddivu" , s2, s3, s4, mem[11], mem[12]);
TEST5("ddivu" , s3, s4, s5, mem[12], mem[13]);
TEST5("ddivu" , s4, s5, s6, mem[13], mem[0]);
printf("\ndmodu\n");
TEST5("dmodu" , t0, t1, t2, mem[0], mem[1]);
TEST5("dmodu" , t1, t2, t3, mem[1], mem[2]);
TEST5("dmodu" , t2, t3, v0, mem[2], mem[3]);
TEST5("dmodu" , t3, v0, v1, mem[3], mem[4]);
TEST5("dmodu" , v0, v1, a0, mem[4], mem[5]);
TEST5("dmodu" , v1, a0, a1, mem[5], mem[6]);
TEST5("dmodu" , a0, a1, a2, mem[6], mem[7]);
TEST5("dmodu" , a1, a2, a3, mem[7], mem[8]);
TEST5("dmodu" , a2, a3, s0, mem[8], mem[9]);
TEST5("dmodu" , a3, s0, s1, mem[9], mem[10]);
TEST5("dmodu" , s0, s1, s2, mem[10], mem[11]);
TEST5("dmodu" , s2, s3, s4, mem[11], mem[12]);
TEST5("dmodu" , s3, s4, s5, mem[12], mem[13]);
TEST5("dmodu" , s4, s5, s6, mem[13], mem[0]);
printf("\ndlsa\n");
TEST1("dlsa" , t0, t1, t2, mem[0], 0);
TEST1("dlsa" , t1, t2, t3, mem[1], 1);
TEST1("dlsa" , t2, t3, v0, mem[2], 2);
TEST1("dlsa" , t3, v0, v1, mem[3], 3);
TEST1("dlsa" , v0, v1, a0, mem[4], 4);
TEST1("dlsa" , v1, a0, a1, mem[5], 5);
TEST1("dlsa" , a0, a1, a2, mem[6], 6);
TEST1("dlsa" , a1, a2, a3, mem[7], 7);
TEST1("dlsa" , s0, s1, s2, mem[8], 8);
TEST1("dlsa" , s1, s2, s3, mem[9], 9);
TEST1("dlsa" , s2, s3, s4, mem[10], 10);
TEST1("dlsa" , s3, s4, s5, mem[11], 11);
TEST1("dlsa" , s4, s5, s6, mem[12], 12);
TEST1("dlsa" , s5, s6, s7, mem[13], 13);
printf("\ndmul\n");
TEST5("dmul" , t0, t1, t2, mem[0], mem[1]);
TEST5("dmul" , t1, t2, t3, mem[1], mem[2]);
TEST5("dmul" , t2, t3, v0, mem[2], mem[3]);
TEST5("dmul" , t3, v0, v1, mem[3], mem[4]);
TEST5("dmul" , v0, v1, a0, mem[4], mem[5]);
TEST5("dmul" , v1, a0, a1, mem[5], mem[6]);
TEST5("dmul" , a0, a1, a2, mem[6], mem[7]);
TEST5("dmul" , a1, a2, a3, mem[7], mem[8]);
TEST5("dmul" , a2, a3, s0, mem[8], mem[9]);
TEST5("dmul" , a3, s0, s1, mem[9], mem[10]);
TEST5("dmul" , s0, s1, s2, mem[10], mem[11]);
TEST5("dmul" , s2, s3, s4, mem[11], mem[12]);
TEST5("dmul" , s3, s4, s5, mem[12], mem[13]);
TEST5("dmul" , s4, s5, s6, mem[13], mem[0]);
printf("\ndmuh\n");
TEST5("dmuh" , t0, t1, t2, mem[0], mem[1]);
TEST5("dmuh" , t1, t2, t3, mem[1], mem[2]);
TEST5("dmuh" , t2, t3, v0, mem[2], mem[3]);
TEST5("dmuh" , t3, v0, v1, mem[3], mem[4]);
TEST5("dmuh" , v0, v1, a0, mem[4], mem[5]);
TEST5("dmuh" , v1, a0, a1, mem[5], mem[6]);
TEST5("dmuh" , a0, a1, a2, mem[6], mem[7]);
TEST5("dmuh" , a1, a2, a3, mem[7], mem[8]);
TEST5("dmuh" , a2, a3, s0, mem[8], mem[9]);
TEST5("dmuh" , a3, s0, s1, mem[9], mem[10]);
TEST5("dmuh" , s0, s1, s2, mem[10], mem[11]);
TEST5("dmuh" , s2, s3, s4, mem[11], mem[12]);
TEST5("dmuh" , s3, s4, s5, mem[12], mem[13]);
TEST5("dmuh" , s4, s5, s6, mem[13], mem[0]);
printf("\ndmulu\n");
TEST5("dmulu" , t0, t1, t2, mem[0], mem[1]);
TEST5("dmulu" , t1, t2, t3, mem[1], mem[2]);
TEST5("dmulu" , t2, t3, v0, mem[2], mem[3]);
TEST5("dmulu" , t3, v0, v1, mem[3], mem[4]);
TEST5("dmulu" , v0, v1, a0, mem[4], mem[5]);
TEST5("dmulu" , v1, a0, a1, mem[5], mem[6]);
TEST5("dmulu" , a0, a1, a2, mem[6], mem[7]);
TEST5("dmulu" , a1, a2, a3, mem[7], mem[8]);
TEST5("dmulu" , a2, a3, s0, mem[8], mem[9]);
TEST5("dmulu" , a3, s0, s1, mem[9], mem[10]);
TEST5("dmulu" , s0, s1, s2, mem[10], mem[11]);
TEST5("dmulu" , s2, s3, s4, mem[11], mem[12]);
TEST5("dmulu" , s3, s4, s5, mem[12], mem[13]);
TEST5("dmulu" , s4, s5, s6, mem[13], mem[0]);
printf("\ndmuhu\n");
TEST5("dmuhu" , t0, t1, t2, mem[0], mem[1]);
TEST5("dmuhu" , t1, t2, t3, mem[1], mem[2]);
TEST5("dmuhu" , t2, t3, v0, mem[2], mem[3]);
TEST5("dmuhu" , t3, v0, v1, mem[3], mem[4]);
TEST5("dmuhu" , v0, v1, a0, mem[4], mem[5]);
TEST5("dmuhu" , v1, a0, a1, mem[5], mem[6]);
TEST5("dmuhu" , a0, a1, a2, mem[6], mem[7]);
TEST5("dmuhu" , a1, a2, a3, mem[7], mem[8]);
TEST5("dmuhu" , a2, a3, s0, mem[8], mem[9]);
TEST5("dmuhu" , a3, s0, s1, mem[9], mem[10]);
TEST5("dmuhu" , s0, s1, s2, mem[10], mem[11]);
TEST5("dmuhu" , s2, s3, s4, mem[11], mem[12]);
TEST5("dmuhu" , s3, s4, s5, mem[12], mem[13]);
TEST5("dmuhu" , s4, s5, s6, mem[13], mem[0]);
printf("\nldpc\n");
TEST6("ldpc", 0, v0);
TEST6("ldpc", 4, v1);
TEST6("ldpc", 16, a0);
TEST6("ldpc", 64, a1);
TEST6("ldpc", 256, a3);
TEST6("ldpc", 1024, t0);
TEST6("ldpc", 4096, t1);
TEST6("ldpc", 16384, t2);
printf("\nlwupc\n");
TEST6("lwupc", 0, v0);
TEST6("lwupc", 4, v1);
TEST6("lwupc", 16, a0);
TEST6("lwupc", 64, a1);
TEST6("lwupc", 256, a3);
TEST6("lwupc", 1024, t0);
TEST6("lwupc", 4096, t1);
TEST6("lwupc", 16384, t2);
#endif
}

0
none/tests/mips64/r6_instructions.stderr.exp Normal file
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243
none/tests/mips64/r6_instructions.stdout.exp-BE Normal file
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@ -0,0 +1,243 @@
dalign
dalign:: 3f
dalign:: 13f
dalign:: 200
dalign:: 312
dalign:: 400
dalign:: 511
dalign:: 6aa
dalign:: 7aa
dalign:: 83f
dalign:: 93f
dalign:: a00
dalign:: b00
dalign:: caa
dalign:: d85
daui
daui:: 10000
daui:: 10001
daui:: 10002
daui:: 10003
daui:: 10004
daui:: 10005
daui:: 10006
daui:: 10007
daui:: 10008
daui:: 10009
daui:: 1000a
daui:: 1000b
daui:: 1000c
daui:: 1000d
dahi
dahi:: 3ff0000100000001
dahi:: 3ff0000100000000
dahi:: 1ffffffff
dahi:: 1234563488994400
dahi:: 4512369801
dahi:: 111111efeeeee220
dahi:: aaaaabbcbbcccddd
dahi:: aa55cc2366dd2200
dahi:: 3ff0045798720001
dahi:: 3ff0000100000000
dahi:: 1ffffffff
dahi:: 7200159762458
dahi:: aa55c201abcdefab
dahi:: 852369751afedbc6
dati
dati:: 3ff1000000000001
dati:: 3ff1000000000000
dati:: 10000ffffffff
dati:: 1235563388994400
dati:: 1004412369801
dati:: 111211eeeeeee220
dati:: aaababbbbbcccddd
dati:: aa56cc2266dd2200
dati:: 3ff1045698720001
dati:: 3ff1000000000000
dati:: 10000ffffffff
dati:: 8200059762458
dati:: aa56c200abcdefab
dati:: 852469741afedbc6
dbitswap
dbitswap:: 0
dbitswap:: 80
dbitswap:: 40
dbitswap:: c0
dbitswap:: 20
dbitswap:: a0
dbitswap:: 60
dbitswap:: e0
dbitswap:: 10
dbitswap:: 90
dbitswap:: 50
dbitswap:: d0
dbitswap:: 30
dbitswap:: b0
ddiv
ddiv:: 1
ddiv:: 3ff00000
ddiv:: 0
ddiv:: 447675
ddiv:: 0
ddiv:: 0
ddiv:: 0
ddiv:: ffffffffffffffff
ddiv:: 1
ddiv:: 3ff00000
ddiv:: 0
ddiv:: 0
ddiv:: 0
ddiv:: ffffffffffffffff
dmod
dmod:: 1
dmod:: 3ff00000
dmod:: ffffffff
dmod:: 31ab51558b
dmod:: 4412369801
dmod:: 111111eeeeeee220
dmod:: aaaaabbbbbcccddd
dmod:: ea45d078ff4f2201
dmod:: 45698720001
dmod:: 3ff00000
dmod:: ffffffff
dmod:: 7200059762458
dmod:: aa55c200abcdefab
dmod:: c51369741afedbc7
ddivu
ddivu:: 1
ddivu:: 3ff00000
ddivu:: 0
ddivu:: 447675
ddivu:: 0
ddivu:: 0
ddivu:: 1
ddivu:: 2
ddivu:: 1
ddivu:: 3ff00000
ddivu:: 0
ddivu:: 0
ddivu:: 1
ddivu:: 2
dmodu
dmodu:: 1
dmodu:: 3ff00000
dmodu:: ffffffff
dmodu:: 31ab51558b
dmodu:: 4412369801
dmodu:: 111111eeeeeee220
dmodu:: 54df9954efabdd
dmodu:: 2a75c37535f921fe
dmodu:: 45698720001
dmodu:: 3ff00000
dmodu:: ffffffff
dmodu:: 7200059762458
dmodu:: 2532588c90cf13e5
dmodu:: 54369741afedbc4
dlsa
dlsa:: 7fe0000000000002
dlsa:: 7fe0000000000001
dlsa:: 200000000
dlsa:: 2468ac6711328803
dlsa:: 88246d3006
dlsa:: 222223ddddddc445
dlsa:: 5555577777999bc0
dlsa:: 54ab9844cdba4407
dlsa:: 7fe008ad30e4000a
dlsa:: 7fe0000000000009
dlsa:: 200000008
dlsa:: e4000b2ec48bb
dlsa:: 54ab8401579bdf62
dlsa:: a46d2e835fdb799
dmul
dmul:: 3ff0000000000000
dmul:: c010000000000000
dmul:: 7664edcc7766bc00
dmul:: 3c92966ae0f94400
dmul:: 405e3296b7f1e220
dmul:: bcd2438320ccd5a0
dmul:: fa541c1ef9205a00
dmul:: e18c52cb8add2200
dmul:: 3ff0000000000000
dmul:: c010000000000000
dmul:: 596f0457a689dba8
dmul:: 906ef1a2f0506ec8
dmul:: 9566bca536f8a742
dmul:: 48c369741afedbc6
dmuh
dmuh:: ff8010000000000
dmuh:: 3fefffff
dmuh:: 12345633
dmuh:: 4d7327599
dmuh:: 489bf9a76
dmuh:: fa4fa4c28f5e3d3a
dmuh:: 1c8e10ee7d7940db
dmuh:: ea9acc383490c340
dmuh:: ff8021560b2f8e0
dmuh:: 3fefffff
dmuh:: 72000
dmuh:: fffd9da2e8550feb
dmuh:: 291cf23985f12705
dmuh:: e15088266f7e0703
dmulu
dmulu:: 3ff0000000000000
dmulu:: c010000000000000
dmulu:: 7664edcc7766bc00
dmulu:: 3c92966ae0f94400
dmulu:: 405e3296b7f1e220
dmulu:: bcd2438320ccd5a0
dmulu:: fa541c1ef9205a00
dmulu:: e18c52cb8add2200
dmulu:: 3ff0000000000000
dmulu:: c010000000000000
dmulu:: 596f0457a689dba8
dmulu:: 906ef1a2f0506ec8
dmulu:: 9566bca536f8a742
dmulu:: 48c369741afedbc6
dmuhu
dmuhu:: ff8010000000000
dmuhu:: 3fefffff
dmuhu:: 12345633
dmuhu:: 4d7327599
dmuhu:: 489bf9a76
dmuhu:: b60b6b17e4d1f5a
dmuhu:: 718e88cca02330b8
dmuhu:: 2a8ad08ecd02c341
dmuhu:: ff8021560b2f8e0
dmuhu:: 3fefffff
dmuhu:: 72000
dmuhu:: 4bda341cb3443
dmuhu:: 58961dae4cbdf276
dmuhu:: 214088266f7e0704
ldpc
ldpc :: out: 0x2500000024
ldpc :: out: 0x2500000024
ldpc :: out: 0x2500000024
ldpc :: out: 0x2500000024
ldpc :: out: 0x2500000024
ldpc :: out: 0x2500000024
ldpc :: out: 0x2500000024
ldpc :: out: 0x2500000024
lwupc
lwupc :: out: 0x25
lwupc :: out: 0x25
lwupc :: out: 0x25
lwupc :: out: 0x25
lwupc :: out: 0x25
lwupc :: out: 0x25
lwupc :: out: 0x25
lwupc :: out: 0x25

243
none/tests/mips64/r6_instructions.stdout.exp-LE Normal file
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@ -0,0 +1,243 @@
dalign
dalign:: 3f
dalign:: 13f
dalign:: 200
dalign:: 312
dalign:: 400
dalign:: 511
dalign:: 6aa
dalign:: 7aa
dalign:: 83f
dalign:: 93f
dalign:: a00
dalign:: b00
dalign:: caa
dalign:: d85
daui
daui:: 10000
daui:: 10001
daui:: 10002
daui:: 10003
daui:: 10004
daui:: 10005
daui:: 10006
daui:: 10007
daui:: 10008
daui:: 10009
daui:: 1000a
daui:: 1000b
daui:: 1000c
daui:: 1000d
dahi
dahi:: 3ff0000100000001
dahi:: 3ff0000100000000
dahi:: 1ffffffff
dahi:: 1234563488994400
dahi:: 4512369801
dahi:: 111111efeeeee220
dahi:: aaaaabbcbbcccddd
dahi:: aa55cc2366dd2200
dahi:: 3ff0045798720001
dahi:: 3ff0000100000000
dahi:: 1ffffffff
dahi:: 7200159762458
dahi:: aa55c201abcdefab
dahi:: 852369751afedbc6
dati
dati:: 3ff1000000000001
dati:: 3ff1000000000000
dati:: 10000ffffffff
dati:: 1235563388994400
dati:: 1004412369801
dati:: 111211eeeeeee220
dati:: aaababbbbbcccddd
dati:: aa56cc2266dd2200
dati:: 3ff1045698720001
dati:: 3ff1000000000000
dati:: 10000ffffffff
dati:: 8200059762458
dati:: aa56c200abcdefab
dati:: 852469741afedbc6
dbitswap
dbitswap:: 0
dbitswap:: 80
dbitswap:: 40
dbitswap:: c0
dbitswap:: 20
dbitswap:: a0
dbitswap:: 60
dbitswap:: e0
dbitswap:: 10
dbitswap:: 90
dbitswap:: 50
dbitswap:: d0
dbitswap:: 30
dbitswap:: b0
ddiv
ddiv:: 1
ddiv:: 3ff00000
ddiv:: 0
ddiv:: 447675
ddiv:: 0
ddiv:: 0
ddiv:: 0
ddiv:: ffffffffffffffff
ddiv:: 1
ddiv:: 3ff00000
ddiv:: 0
ddiv:: 0
ddiv:: 0
ddiv:: ffffffffffffffff
dmod
dmod:: 1
dmod:: 3ff00000
dmod:: ffffffff
dmod:: 31ab51558b
dmod:: 4412369801
dmod:: 111111eeeeeee220
dmod:: aaaaabbbbbcccddd
dmod:: ea45d078ff4f2201
dmod:: 45698720001
dmod:: 3ff00000
dmod:: ffffffff
dmod:: 7200059762458
dmod:: aa55c200abcdefab
dmod:: c51369741afedbc7
ddivu
ddivu:: 1
ddivu:: 3ff00000
ddivu:: 0
ddivu:: 447675
ddivu:: 0
ddivu:: 0
ddivu:: 1
ddivu:: 2
ddivu:: 1
ddivu:: 3ff00000
ddivu:: 0
ddivu:: 0
ddivu:: 1
ddivu:: 2
dmodu
dmodu:: 1
dmodu:: 3ff00000
dmodu:: ffffffff
dmodu:: 31ab51558b
dmodu:: 4412369801
dmodu:: 111111eeeeeee220
dmodu:: 54df9954efabdd
dmodu:: 2a75c37535f921fe
dmodu:: 45698720001
dmodu:: 3ff00000
dmodu:: ffffffff
dmodu:: 7200059762458
dmodu:: 2532588c90cf13e5
dmodu:: 54369741afedbc4
dlsa
dlsa:: 7fe0000000000002
dlsa:: 7fe0000000000001
dlsa:: 200000000
dlsa:: 2468ac6711328803
dlsa:: 88246d3006
dlsa:: 222223ddddddc445
dlsa:: 5555577777999bc0
dlsa:: 54ab9844cdba4407
dlsa:: 7fe008ad30e4000a
dlsa:: 7fe0000000000009
dlsa:: 200000008
dlsa:: e4000b2ec48bb
dlsa:: 54ab8401579bdf62
dlsa:: a46d2e835fdb799
dmul
dmul:: 3ff0000000000000
dmul:: c010000000000000
dmul:: 7664edcc7766bc00
dmul:: 3c92966ae0f94400
dmul:: 405e3296b7f1e220
dmul:: bcd2438320ccd5a0
dmul:: fa541c1ef9205a00
dmul:: e18c52cb8add2200
dmul:: 3ff0000000000000
dmul:: c010000000000000
dmul:: 596f0457a689dba8
dmul:: 906ef1a2f0506ec8
dmul:: 9566bca536f8a742
dmul:: 48c369741afedbc6
dmuh
dmuh:: ff8010000000000
dmuh:: 3fefffff
dmuh:: 12345633
dmuh:: 4d7327599
dmuh:: 489bf9a76
dmuh:: fa4fa4c28f5e3d3a
dmuh:: 1c8e10ee7d7940db
dmuh:: ea9acc383490c340
dmuh:: ff8021560b2f8e0
dmuh:: 3fefffff
dmuh:: 72000
dmuh:: fffd9da2e8550feb
dmuh:: 291cf23985f12705
dmuh:: e15088266f7e0703
dmulu
dmulu:: 3ff0000000000000
dmulu:: c010000000000000
dmulu:: 7664edcc7766bc00
dmulu:: 3c92966ae0f94400
dmulu:: 405e3296b7f1e220
dmulu:: bcd2438320ccd5a0
dmulu:: fa541c1ef9205a00
dmulu:: e18c52cb8add2200
dmulu:: 3ff0000000000000
dmulu:: c010000000000000
dmulu:: 596f0457a689dba8
dmulu:: 906ef1a2f0506ec8
dmulu:: 9566bca536f8a742
dmulu:: 48c369741afedbc6
dmuhu
dmuhu:: ff8010000000000
dmuhu:: 3fefffff
dmuhu:: 12345633
dmuhu:: 4d7327599
dmuhu:: 489bf9a76
dmuhu:: b60b6b17e4d1f5a
dmuhu:: 718e88cca02330b8
dmuhu:: 2a8ad08ecd02c341
dmuhu:: ff8021560b2f8e0
dmuhu:: 3fefffff
dmuhu:: 72000
dmuhu:: 4bda341cb3443
dmuhu:: 58961dae4cbdf276
dmuhu:: 214088266f7e0704
ldpc
ldpc :: out: 0x2400000025
ldpc :: out: 0x2400000025
ldpc :: out: 0x2400000025
ldpc :: out: 0x2400000025
ldpc :: out: 0x2400000025
ldpc :: out: 0x2400000025
ldpc :: out: 0x2400000025
ldpc :: out: 0x2400000025
lwupc
lwupc :: out: 0x25
lwupc :: out: 0x25
lwupc :: out: 0x25
lwupc :: out: 0x25
lwupc :: out: 0x25
lwupc :: out: 0x25
lwupc :: out: 0x25
lwupc :: out: 0x25

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