On various systems none/tests/amd64-linux/map_32bits.vgtest fails with:
first mmap: Cannot allocate memory.
The problem is that the --aspace-minaddr is too tight. Newer glibc seem
to mmap some memory and so even our first mmap with MMAP_32BIT will fail.
The solution is to make a bit more memory < 2GB available.
If there is 16MB available the test always seems to succeed without
needing too many tries. The original 256K is too low.
https://bugs.kde.org/show_bug.cgi?id=406422
Valgrind ppc64 test_isa_3_0_other test will attempt to display
all of the bits of the XER as part of the test case results.
The tests have no existing logic to clear those bits, so this can
pick up straggling values that cascade into a testcase failure.
This adds some code to correct this in two directions;
- Print only the bits that are expected by the tests. This
is currently just the OV and OV32 bits.
- print all of the bits when run under higher verbosity levels.
Bugzilla 406198 - none/tests/ppc64/test_isa_3_0_other test sporadically
including CA bit in output
Patch submitted by Will Schmidt <will_schmidt@vnet.ibm.com>
Patch reviewed, committed by: Carl Love <cel@us.ibm.com>
This corrects a valgrind instruction emulation issue revealed by
a GCC change.
The xscvdpsp,xscvdpspn,xscvdpuxws instructions each convert
double precision values to single precision values, and write
the results into bits 0-32 of the 128 bit target register.
To get the value into the normal position for a scalar register
the result needed to be right-shifted 32 bits, so gcc always
did that.
It was determined that hardware also always did that, so the (redundant)
gcc shift was removed.
This exposed an issue because valgrind was only writing the result to
bits 0-31 of the target register.
This patch updates the emulation to write the result to both of the involved
32-bit fields.
VEX/priv/guest_ppc_toIR.c:
- rearrange ops in dis_vx_conv to update more portions of the target
register with copies of the result. xscvdpsp,xscvdpspn,xscvdpuxws
none/tests/ppc64/test_isa_2_06_part1.c
- update res32 checking to explicitly include fcfids and fcfidus in the
32-bit result grouping.
none/tests/ppc64/test_isa_2_07_part2.c
- correct NULL initializer for logic_tests definition
[*1] - GCC change referenced:
2017-09-26 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (movsi_from_sf): Adjust code to
eliminate doing a 32-bit shift right or vector extract after
doing XSCVDPSPN.
patch submitted by: Will Schmidt <will_schmidt@vnet.ibm.com>
reviewed, committed by: Carl Love <cel@us.ibm.com>
Bug 398870 - Please add support for instruction vcvtps2ph
Bug 353370 - RDRAND amd64->IR: unhandled instruction bytes: 0x48 0xF 0xC7 0xF0
This commit implements:
* amd64 RDRAND instruction, on hosts that have it.
* amd64 VCVTPH2PS and VCVTPS2PH, on hosts that have it.
The presence/absence of these on the host is now reflected in the CPUID
results returned to the guest. So code that tests for these features in
CPUID and acts accordingly should "just work".
* New test cases, none/tests/amd64/rdrand and none/tests/amd64/f16c. These
are built if the host's assembler can handle them, in the usual way.
The libvexmultiarch_test failed on s390, since VEX was configured for MIPS64
with 32bit FPUs. Modify arch_hwcaps() to a realist case with 64bit FPUs.
This fixes KDE #402351.
addex uses OV as carry in and carry out. For all other instructions
OV is the signed overflow flag. And instructions like adde use CA
as carry.
Replace set_XER_OV_OV32 with set_XER_OV_OV32_ADDEX, which will
call calculate_XER_CA_64 and calculate_XER_CA_32, but with OV
as input, and sets OV and OV32.
Enable test_addex in none/tests/ppc64/test_isa_3_0.c and update
the expected output. test_addex would fail to match the expected
output before this patch.
The mfvscr and vor instructions in jm-insns.c had a "=vr" constraint.
This should have been an "=v" constraint. This resolved assembler
warnings and the testcase failing on ppc64le with gcc 8.2 and
binutils 2.30.
Add test cases for the z13 vector FP support. Bring s390-opcodes.csv
up-to-date, reflecting that the z13 vector instructions are now supported.
Also remove the non-support disclaimer for the vector facility from
README.s390.
The patch was contributed by Vadim Barkov, with some clean-up and minor
adjustments by Andreas Arnez.
Author: Nicholas Nethercote <nnethercote@mozilla.com>
Use inlined frames in Massif XTree output.
This makes Massif's output much easier to follow.
The commit also removes a -1 used on all Massif stack frame addresses.
There was a big comment questioning the presence of that -1, and with it
gone the addresses now match those produced by DHAT.
This adds test cases and some internal stuff to the z/Architecture vector
integer and string instruction support.
Contributed by Vadim Barkov <vbrkov@gmail.com>.
This implements various z/Architecture instructions that conditionally
yield a data exception ("trap"). The condition is either based on a
comparison being true ("compare and trap") or on a loaded value being
zero ("load and trap"). These instructions haven't been widely used in
the past, but may now be emitted by newer compilers. Note that the
resulting signal for a data exception is SIGFPE, not SIGTRAP. Thus this
patch also adds a new jump kind Ijk_SigFPE.
Adds test cases, that check both the 10h and 11h decodings. For some reason
the expected output diff is huge. I don't know why. It is the same as what
the hardware produces, though.
Apart from instructions with vector operands, Valgrind does not implement the
additional z/Architecture instructions introduced with z13.
These are:
- load and zero rightmost byte (LZRF, LZRG);
- load logical and zero rightmost byte (LLZRGF);
- load halfword high immediate on condition (LOCHHI);
- load halfword immediate on condition (LOCHI, LOCGHI);
- load high on condition (LOCFHR, LOCFH);
- store high on condition (STOCFH);
- perform pseudorandom number operation (PPNO), with the functions
PPNO-Query and PPNO-SHA-512-DRNG;
- load count to block boundary (LCBB).
Patches from Vadim Barkov (vbrkov@gmail.com), with coordination, testing
and format cleanups from Andreas Arnez (arnez@linux.ibm.com).
This test fails sporadically (eg, on Fedora 27 with gcc (GCC) 7.3.1 20180303 (Red Hat 7.3.1-5))
because the tested instruction uses RAX and RDX as input, but the test framework doesn't
set them :-/, so the outcome basically depends on whatever junk the compiler left in those
registers beforehand. As a result of this, all previous uses of RAX in the test have
been changed to use RSI instead. n-i-bz.
The ppc32 results were not updated when the xvnegsp instruction support
was added. Add the xvnegsp 32-bit results to
ppc/test_isa_2_06_part3.stdout.exp.
Signed-off-by: Carl Love <carll@us.ibm.com>
Missed the update to none/tests/ppc64/Makefile.am to remove the
expected output files test_isa_3_0_altivec.stdout.exp and
test_isa_3_0_other.stdout.exp.
Add support for instruction xsmaxcdp in VEX/priv/guest_ppc_toIR.c.
Fixes in file VEX/priv/guest_ppc_toIR.c for xsmaxcdp, xsmincdp, lxssp,
stxssp and stxvl instructions.
Fix compiler issues with optimization option -O2 for test
none/tests/ppc64/test_isa_3_0.c.
Add test case test_xsmaxcdpi to test file none/tests/ppc64/test_isa_3_0.c.
Fixes to test none/tests/ppc64/test_isa_3_0.c for compiling inline functions
with optimization -O0. Assembly instruction fixes, test argument array size
fixes, max loop index fixes. Condition code register fixes to fix control
flow issues when compiled with optimization.
Update expected results for test_isa_3_0_altivec.stdout.exp-LE and
test_isa_3_0_other.stdout.exp-LE.
The modified test none/tests/sem crashes with a SEGV when valgrind is compiled
with lto on various amd64 platforms (debian/gcc 6.3, RHEL7/gcc 6.4,
Ubuntu/gcc 7.2)
The problem is that the vki_semid_ds buf is not what is expected by the kernel:
the kernel expects a bigger structure vki_semid64_ds (at least on
these platforms).
Getting the sem_nsems seems to work by chance, as sem_nsems is at
the same offset in both vki_semid_ds and vki_semid64_ds.
However, e.g. the ctime was not set properly after syscall return,
and 2 words after sem_nsems were set to 0 by the kernel, causing
the SEGV, as a spilled register became 0.
Fix consists in using the 64 bit version for __NR_semctl.
Tested on debian/amd64 and s390x.
Fix the register constraints for the vtvsrwa and mtfprd instructions
in test_isa_2_07_part2.c. Update the expected output in
none/tests/jm_vec_isa_2_07.stdout.exp.
Fix destination register constraint in assembly code in function
test_mtfprwa in file none/tests/ppc64/test_isa_2_07_part1.c. Constraint
changed from "=ws" to "=d".
This set of tests covers MIPS r6 specific instructions:
none/tests/mips32/MIPS32r6int
none/tests/mips32/branch_pc
none/tests/mips32/branches_r6
none/tests/mips32/fp_r6
none/tests/mips32/pc_instructions_r6
none/tests/mips64/MIPS64r6int
none/tests/mips64/branch_pc
none/tests/mips64/branches_r6
none/tests/mips64/fp_r6
none/tests/mips64/pc_instructions_r6
none/tests/mips64/r6_instructions
The following tests had to be changed to be applicaple for Rev6:
none/tests/libvex_test.c
none/tests/mips32/LoadStore
none/tests/mips32/LoadStore1
none/tests/mips32/MIPS32int
none/tests/mips32/MoveIns
none/tests/mips32/branches
none/tests/mips32/change_fp_mode
none/tests/mips32/mips32_dsp
none/tests/mips32/vfp
none/tests/mips64/arithmetic_instruction
none/tests/mips64/branches
none/tests/mips64/fpu_arithmetic
none/tests/mips64/fpu_load_store
none/tests/mips64/load_store
none/tests/mips64/load_store_multiple
none/tests/mips64/move_instructions
The following tests are not applicable for Rev6:
none/tests/mips32/fpu_branches
none/tests/mips32/unaligned_load_store
none/tests/mips64/branch_and_jump_instructions
none/tests/mips64/change_fp_mode
none/tests/mips64/fpu_branches
none/tests/mips64/load_store_unaligned
none/tests/mips64/unaligned_load
none/tests/mips64/unaligned_load_store.
Contributed by:
Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic.
Related BZ issue - #387410.
(from bug 385408 comment 0):
Valgrind currently lacks support for the z/Architecture vector "support"
instructions introduced with z13. These are documented in the
z/Architecture Principles of Operation, Eleventh Edition (March, 2015),
chapter 21: "Vector Overview and Support Instructions".
Bits 18 (NAN2008) and 19 (ABS2008) in FCSR are preset by hardware and can
differ between platforms. Hence, we should clear these bits before printing
FCSR value in order to have the same output on different platforms.
This fixes several failures (tests modified by this change) that occur on
MIPS P5600 board. The P5600 is a core that implements MIPS32 Release 5 arch.
This set of tests covers the whole MSA instruction set:
none/tests/mips32/msa_arithmetic
none/tests/mips32/msa_comparison
none/tests/mips32/msa_data_transfer
none/tests/mips32/msa_fpu
none/tests/mips32/msa_logical_and_shift
none/tests/mips32/msa_shuffle
none/tests/mips64/msa_arithmetic (symlink to mips32)
none/tests/mips64/msa_comparison (symlink to mips32)
none/tests/mips64/msa_data_transfer
none/tests/mips64/msa_fpu (symlink to mips32)
none/tests/mips64/msa_logical_and_shift (symlink to mips32)
none/tests/mips64/msa_shuffle (symlink to mips32)
Contributed by:
Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic.
Related BZ issue - #382563.
glibc doesn't guarantee anything about setrlimit with a NULL limit argument.
It could just crash (if it needs to adjust the limit) or might silently
succeed (as newer glibc do). Just remove the extra check.
See also the "setrlimit change to prlimit change in behavior" thread:
https://sourceware.org/ml/libc-alpha/2017-10/threads.html#00830
Compiler may optimize out call to cbrt. Change test to prevent that.
Otherwise, the test does not exercise a desired codepath for cbrt, and it
prints precalculated value.
In 64 bit mode there's no way to just save eflags so we save the
whole of rflags but we were doing so to a 32 bit variable!
Replace that with proper rflags support that knows it is dealing
with the full 64 bit flags word in 64 bit mode.
Implements a new version of VEX register allocator which
keeps the main state per virtual registers, as opposed
to real registers in v2. This results in a simpler and
cleaner design and much simpler implementation.
It has been observed that the new allocator executes 20-30%
faster than the previous one but could produce slightly worse
spilling decisions. Overall performance improvement when running
the Valgrind performance regression test suite has been observed
in terms of a few percent.
The new register allocator (v3) is now the default one.
The old register allocator (v2) is still kept around and can be
activated with command line option '--vex-regalloc-version=2'.
Fixes BZ#381553.
This patch removes two compiler warnings from the test:
vfp.c: In function 'handler':
vfp.c:260:4: warning: implicit declaration of function 'exit'
[-Wimplicit-function-declaration]
exit(0);
^
vfp.c:260:4: warning: incompatible implicit declaration of built-in
function 'exit'
vfp.c: At top level:
vfp.c:258:13: warning: 'handler' defined but not used [-Wunused-function]
static void handler(int sig)
^
The #ifdef HAS_VSX guard is wrongly placed. It makes the standard
include headers not be used. Causing a build failure. Fix by moving
the #ifdef HAS_VSX after the standard includes.
https://bugs.kde.org/show_bug.cgi?id=381272
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@16450
