Carl Love 82e94fff80 PPC64, patch to test case issues reported in bugzilla 401827 and 401828.
This corrects a valgrind instruction emulation issue revealed by
a GCC change.
The xscvdpsp,xscvdpspn,xscvdpuxws instructions each convert
double precision values to single precision values, and write
the results into bits 0-32 of the 128 bit target register.
To get the value into the normal position for a scalar register
the result needed to be right-shifted 32 bits, so gcc always
did that.
It was determined that hardware also always did that, so the (redundant)
gcc shift was removed.
This exposed an issue because valgrind was only writing the result to
bits 0-31 of the target register.

This patch updates the emulation to write the result to both of the involved
32-bit fields.

VEX/priv/guest_ppc_toIR.c:
  - rearrange ops in dis_vx_conv to update more portions of the target
    register with copies of the result.   xscvdpsp,xscvdpspn,xscvdpuxws

none/tests/ppc64/test_isa_2_06_part1.c
  - update res32 checking to explicitly include fcfids and fcfidus in the
    32-bit result grouping.

none/tests/ppc64/test_isa_2_07_part2.c
  - correct NULL initializer for logic_tests definition

[*1] - GCC change referenced:
    2017-09-26  Michael Meissner  <meissner@linux.vnet.ibm.com>
            * config/rs6000/rs6000.md (movsi_from_sf): Adjust code to
              eliminate doing a 32-bit shift right or vector extract after
              doing  XSCVDPSPN.

patch submitted by:   Will Schmidt <will_schmidt@vnet.ibm.com>
reviewed, committed by:  Carl Love <cel@us.ibm.com>
2019-04-04 12:31:05 -05:00
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