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Petar Jovanovic
4ef3d807e1 mips: MSA support for mips32/mips64. 
Full support of MIPS SIMD Architecture Module (MSA) instruction set.

Following IOPs have been implemented using generation of MSA instructions:

  Iop_GetElem8x16, Iop_GetElem16x8, Iop_GetElem32x4, Iop_GetElem64x2,
  Iop_V128to32, Iop_V128HIto64, Iop_V128to64, Iop_F32toF16x4, Iop_Abs64x2,
  Iop_Abs32x4, Iop_Abs16x8, Iop_Abs8x16, Iop_Cnt8x16, Iop_NotV128,
  Iop_Reverse8sIn16_x8, Iop_Reverse8sIn32_x4, Iop_Reverse8sIn64_x2,
  Iop_Cls8x16, Iop_Cls16x8, Iop_Cls32x4, Iop_Clz8x16, Iop_Clz16x8,
  Iop_Clz32x4, Iop_Clz64x2, Iop_Abs32Fx4, Iop_Abs64Fx2, Iop_RecipEst32Fx4,
  Iop_RecipEst64Fx2, Iop_RSqrtEst32Fx4, Iop_RSqrtEst64Fx2, Iop_F16toF32x4,
  Iop_I32UtoFx4, Iop_FtoI32Sx4_RZ, Iop_FtoI32Ux4_RZ, Iop_Add8x16,
  Iop_Add16x8, Iop_Add32x4, Iop_Add64x2, Iop_Sub8x16, Iop_Sub16x8,
  Iop_Sub32x4, Iop_Sub64x2, Iop_QAdd8Sx16, Iop_QAdd16Sx8, Iop_QAdd32Sx4,
  Iop_QAdd64Sx2, Iop_QAdd8Ux16, Iop_QAdd16Ux8, Iop_QAdd32Ux4,
  Iop_QAdd64Ux2, Iop_QSub8Sx16, Iop_QSub16Sx8, Iop_QSub32Sx4,
  Iop_QSub64Sx2, Iop_QSub8Ux16, Iop_QSub16Ux8, Iop_QSub32Ux4,
  Iop_QSub64Ux2, Iop_QDMulHi32Sx4, Iop_QDMulHi16Sx8, Iop_QRDMulHi32Sx4,
  Iop_QRDMulHi16Sx8, Iop_Max8Sx16, Iop_Max16Sx8, Iop_Max32Sx4, Iop_Max64Sx2,
  Iop_Max8Ux16, Iop_Max16Ux8, Iop_Max32Ux4, Iop_Max64Ux2, Iop_Min8Sx16,
  Iop_Min16Sx8, Iop_Min32Sx4, Iop_Min64Sx2, Iop_Min8Ux16, Iop_Min16Ux8,
  Iop_Min32Ux4, Iop_Min64Ux2, Iop_Shl8x16, Iop_Shl16x8, Iop_Shl32x4,
  Iop_Shl64x2, Iop_Shr8x16, Iop_Shr16x8, Iop_Shr32x4, Iop_Shr64x2,
  Iop_Sar8x16, Iop_Sar16x8, Iop_Sar32x4, Iop_Sar64x2, Iop_InterleaveHI8x16,
  Iop_InterleaveHI16x8, Iop_InterleaveHI32x4, Iop_InterleaveHI64x2,
  Iop_InterleaveLO8x16, Iop_InterleaveLO16x8, Iop_InterleaveLO32x4,
  Iop_InterleaveLO64x2, Iop_InterleaveEvenLanes8x16,
  Iop_InterleaveEvenLanes16x8, Iop_InterleaveEvenLanes32x4,
  Iop_InterleaveOddLanes8x16, Iop_InterleaveOddLanes16x8,
  Iop_InterleaveOddLanes32x4, Iop_CmpEQ8x16, Iop_CmpEQ16x8, Iop_CmpEQ32x4,
  Iop_CmpEQ64x2, Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4,
  Iop_CmpGT64Sx2, Iop_CmpGT8Ux16, Iop_CmpGT16Ux8, Iop_CmpGT32Ux4,
  Iop_CmpGT64Ux2, Iop_Avg8Sx16, Iop_Avg16Sx8, Iop_Avg32Sx4, Iop_Avg8Ux16,
  Iop_Avg16Ux8, Iop_Avg32Ux4, Iop_Mul8x16, Iop_Mul16x8, Iop_Mul32x4,
  Iop_AndV128, Iop_OrV128, Iop_XorV128, Iop_ShrV128, Iop_ShlV128,
  Iop_ShlN8x16, Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2, Iop_SarN8x16,
  Iop_SarN16x8, Iop_SarN32x4, Iop_SarN64x2, Iop_ShrN8x16, Iop_ShrN16x8,
  Iop_ShrN32x4, Iop_ShrN64x2, Iop_QandQSarNnarrow64Sto32Sx2,
  Iop_QandQSarNnarrow32Sto16Sx4, Iop_QandQRSarNnarrow64Sto32Sx2,
  Iop_QandQRSarNnarrow32Sto16Sx4, Iop_CmpEQ32Fx4, Iop_CmpEQ64Fx2,
  Iop_CmpLT32Fx4, Iop_CmpLT64Fx2, Iop_CmpLE32Fx4, Iop_CmpLE64Fx2,
  Iop_CmpUN32Fx4, Iop_CmpUN64Fx2, Iop_64HLtoV128, Iop_Min32Fx4,
  Iop_Min64Fx2, Iop_Max32Fx4, Iop_Max64Fx2, Iop_Sqrt32Fx4,
  Iop_Sqrt64Fx2, Iop_Add32Fx4, Iop_Add64Fx2, Iop_Sub32Fx4,
  Iop_Sub64Fx2, Iop_Mul32Fx4, Iop_Mul64Fx2, Iop_Div32Fx4,
  Iop_Div64Fx2, Iop_F32x4_2toQ16x8, Iop_F64x2_2toQ32x4,
  Iop_ScaleF64, Scale2_64Fx2, Scale2_32Fx4, Iop_Log2_32Fx4, Iop_Log2_64Fx2,
  Iop_PackOddLanes8x16, Iop_PackEvenLanes8x16, Iop_PackOddLanes16x8,
  Iop_PackEvenLanes16x8, Iop_PackOddLanes32x4, Iop_PackEvenLanes32x4.

Folowing IOPs have been implemented without generating MSA instructions:

  Iop_CmpEQ8, Iop_MullU8, Iop_MullS8, Iop_MullU16, Iop_MullS16, Iop_DivS32,
  Iop_DivU32, Iop_DivS64, Iop_DivU64, Iop_F32toI32U, Iop_F64toI64U,
  Iop_I64UtoF64

Imlementation of the following IOPs has been changed in order to use MSA
when it is possible:

  Iop_MAddF64, Iop_MSubF32, Iop_MSubF64.

Contributed by:
  Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic.

Related BZ issue - #382563.
 2017-10-27 16:27:24 +02:00
Petar Jovanovic
91373819a3 mips: new Iops added to support MSA 
New Iops are defined:
  Iop_Scale2_32Fx4, Iop_Scale2_64Fx2,
  Iop_Log2_32Fx4, Iop_Log2_64Fx2,
  Iop_F32x4_2toQ16x8, Iop_F64x2_2toQ32x4,
  Iop_PackOddLanes8x16, Iop_PackEvenLanes8x16,
  Iop_PackOddLanes16x8, Iop_PackEvenLanes16x8,
  Iop_PackOddLanes32x4, Iop_PackEvenLanes32x4.

Contributed by:
  Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic.

Related BZ issue - #382563.
 2017-10-27 16:27:24 +02:00
Philippe Waroquiers
c1eace647c Fix n-i-bz fix bug in strspn replacement 
Mix-up between UChar and HChar in strspn.
Also grouped together the n-i-bz announded fixes in NEWS
 2017-10-26 20:53:15 +02:00
Mark Wielaard
476b52d62d Bug #385912. Remove explicit NULL check from none/tests/rlimit_nofile. 
glibc doesn't guarantee anything about setrlimit with a NULL limit argument.
It could just crash (if it needs to adjust the limit) or might silently
succeed (as newer glibc do). Just remove the extra check.

See also the "setrlimit change to prlimit change in behavior" thread:
https://sourceware.org/ml/libc-alpha/2017-10/threads.html#00830
 2017-10-20 14:55:06 +02:00
Mark Wielaard
f844689f85 Suppress _dl_runtime_resolve_avx_slow for memcheck conditional. 
glibc ld.so has an optimization when resolving a symbol that checks
whether or not the upper 128 bits of the ymm registers are zero. If
so it uses "cheaper" instructions to save/restore them using the xmm
registers. If those upper 128 bits contain undefined values memcheck
will issue an Conditional jump or move depends on uninitialised value(s)
warning whenever trying to resolve a symbol.

This triggers in our sh-mem-vecxxx test cases. Suppress the warning
by default.

https://bugs.kde.org/show_bug.cgi?id=385868
 2017-10-20 14:17:04 +02:00
Petar Jovanovic
cd1d7eb00c mips: simplify handling of Iop_Max32U 
Use MIPSRH_Reg to get MIPSRH for Iop_Max32U. Without it, under specific
circumstances, the code may explode and exceed Valgrind instruction buffer
due to multiple calls to iselWordExpr_R through iselWordExpr_RH.

Issue discovered while testing Valgrind on Android.

Patch by Tamara Vlahovic.
 2017-10-17 15:40:47 +02:00
Petar Jovanovic
2cf115e657 mips: fix handling of Iex_ITE 
While handling Iex_ITE, do not use the same virtual register for the
input and output.

Issue discovered while testing Valgrind on Android.

Patch by Tamara Vlahovic.
 2017-10-17 15:31:06 +02:00
Ivo Raisr
074de238d4 VEX register allocator: allocate caller-save registers for short lived vregs. 
Allocate caller-saved registers for short lived vregs and callee-save registers
for vregs which span accross helper calls.
Fixes BZ#384987.
 2017-10-11 20:56:49 +02:00
Ivo Raisr
83cabd3249 Refactor tracking of MOV coalescing. 
Reg<->Reg MOV coalescing status is now a part of the HRegUsage.
This allows register allocation to query it two times without incurring
a performance penalty. This in turn allows to better keep track of
vreg<->vreg MOV coalescing so that all vregs in the coalesce chain
get the effective |dead_before| of the last vreg.

A small performance improvement has been observed because this allows
to coalesce even spilled vregs (previously only assigned ones).
 2017-10-11 20:56:48 +02:00
Petar Jovanovic
c069589178 mips: add support for bi-arch build on mips64 
If native compiler can build Valgrind for mips32 o32 on native mips64
system, it should do it.
This change adds a second architecture for MIPS in a similar way how it has
been previously done for amd64 and ppc64.
 2017-10-10 18:06:14 +02:00
Carl Love
856d45eb7e PPC64, vpermr, xxperm, xxpermr fix Iop_Perm8x16 selector field 
The implementation of the vpermr, xxperm, xxpermr violate this by
using a mask of 0x1F.  Fix the code and the corresponding comments
to met the definition for Iop_Perm8x16.  Use Iop_Dup8x16 to generate
vector value for subtraction.

Bugzilla 385334.
 2017-10-05 12:19:59 -05:00
Carl Love
c618e707d3 PPC64, revert the change to vperm instruction. 
The patch was in my git tree with the patch I intended to apply.
I didn't realize the patch was in the tree.  Git applied both
patches.  Still investigating the vperm change to see if it is
really needed.
 2017-10-04 10:54:07 -05:00
Carl Love
5398a9f9cb PPC64, Add support for xscmpeqdp, xscmpgtdp, xscmpgedp, xsmincdp instructions. 
These are Power 9 instructions.

Add test cases for the new instructions to test_isa_3_0.c

Bugzilla 385183.
 2017-10-04 10:24:36 -05:00
Carl Love
f0c4da68ca PPC64, Fix bug in vperm instruction. 
The ISA says:

Let the source vector be the concatenation of the
contents of VR[VRA] followed by the contents of
VR[VRB].

For each integer value i from 0 to 15, do the following.
  Let index be the value specified by bits 3:7 of byte
  element i of VR[VRC].

So, the index value is 5-bits wide ([3:7]), not 4-bits wide.
 2017-10-03 15:19:53 -05:00
Carl Love
b0aef250a7 PPC64, Re-implement the vpermr instruction using the Iop_Perm8x16. 
The current implementation will generate a lot of Iops.  The number
of generated Iops can lead to Valgrind running out of temporary space.
See bugzilla https://bugs.kde.org/show_bug.cgi?id=385208 as an example
of the issue.  Using Iop_Perm8x16 reduces the number of Iops significantly.

bugzilla 385210
 2017-10-03 15:18:09 -05:00
Carl Love
a1d03d0d11 PPC64, Use the vperm code to implement the xxperm inst. 
The current xxperm instruction implementation generates a huge
number of Iops to explicitly do the permutation.  The code
was changed to use the Iop_Perm8x16 which is much more efficient
so temporary memory doesn't get exhausted.

Bugzilla 385208
 2017-10-03 15:09:22 -05:00
Carl Love
acdeb75d2a PPC64, Replace body of generate_store_FPRF with C helper function. 
The function calculates the floating point condition code values
and stores them into the floating point condition code register.
The function is used by a number of instructions. The calculation
generates a lot of Iops as it much check the operatds for NaN, SNaN,
zero, dnorm, norm and infinity. The large number of Iops exhausts
temporary memory.
 2017-10-03 12:08:09 -05:00
Carl Love
7fce2c5269 PPC64, Add support for the Data Stream Control Register (DSCR) 2017-10-03 12:03:22 -05:00
Petar Jovanovic
da3987aa18 mips32: add BE-exp files for several tests 
This fixes several tests on mips32 BE platforms:

memcheck/tests/mips32/fadvise64
drd/tests/tc19_shadowmem
helgrind/tests/tc19_shadowmem
 2017-10-02 14:54:20 +02:00
Petar Jovanovic
f3637a0853 mips: make sure configure script checks for correct ABIs 
For mips64, we currently build for n64.
For mips32, we currently build for o32.

Pass these flags explicitly in configure checks.
 2017-10-02 13:28:50 +02:00
Rhys Kidd
7221d28cad gitignore: Fix up false directory-level .gitignore settings 
So we never intended to ignore all changes from the top-level down in /include
or /cachegrind. Instead allow the filetype-specific .gitignore patterns match
to the contents of these two folders.

Also, don't ignore changes to include/valgrind.h as it exists in the repository
and should be tracked for any changes developers might make.

Changes tested by running a git clean force and then full rebuild. No stray
build artifacts were being tracked erroneously by git after these changes.
 2017-10-01 20:57:04 -04:00
Rhys Kidd
1ce04c35c2 Preliminary support for Darwin 17.x (macOS 10.13) 2017-10-01 19:45:10 -04:00
Rhys Kidd
ed6ad13bc8 Fix missing workq_ops operations (macOS) 
Related to discussion in bz#383723. Patch based upon one provided by
Andy Maloney.
 2017-10-01 19:05:48 -04:00
Petar Jovanovic
711d3a53c3 mips64: set mips64r2 as default for 64-builds 
Set mips64r2 as default. Major 64-bit platforms are Rev2.
This also fixes small issue when -march=octeon is in conflict with -mips64.
 2017-09-29 19:16:37 +02:00
Petar Jovanovic
eb18bd1b44 mips: optimize multiplication Iops 
Optimize and refactor some of mul* Iop code in VEX/priv/host_mips_.

Patch from Aleksandar Rikalo.
 2017-09-28 19:29:51 +02:00
Ivo Raisr
8cdeee4ebb Minor refactoring for VEX register allocator v3. No functional change. 2017-09-28 07:39:12 +02:00
Philippe Waroquiers
4adbae3559 Add a .exp file for the dash version in Debian 9 
Add shell.stderr.exp-dash3, which differs from shell.stderr.exp-dash2 with:

6c6
< ./shell_binaryfile: 4: ./shell_binaryfile: Syntax error: ")" unexpected
---
> ./shell: 19: ./shell: ./shell_binaryfile: Exec format error

(so the newer dash gives a clearer msg)
 2017-09-27 18:29:58 +02:00
Petar Jovanovic
9fa2d21857 mips: fix typos for the recently added test 
Correct name of the recently added test in Makefile.am.
 2017-09-27 16:52:05 +02:00
Petar Jovanovic
c96148a2a1 mips: fix VKI_SIOCATMARK, VKI_SIOCSPGRP and VKI_SIOCGPGRP macros 
Set correct values from Linux kernel.
See ./arch/mips/include/uapi/asm/sockios.h

This issue is covered by newly introduced memcheck test mips32/bad_sioc.
 2017-09-27 16:04:31 +02:00
Petar Jovanovic
8227e4a763 mips: new Memcheck test, bad_sioc 
Check if Memcheck is able to recognize errors related to uninitialized
parameters in ioctl(SIOCSPGRP / SIOCATMARK) calls.

Test by Aleksandar Rikalo.
 2017-09-27 15:55:16 +02:00
Ivo Raisr
07e286ea30 Reorder allocatable registers for s390x so that the callee saved are listed first. 
Helper calls always trash all caller saved registers. By listing the callee saved
first then VEX register allocator (both v2 and v3) is more likely to pick them
and does not need to spill that much before helper calls.
 2017-09-26 21:15:58 +02:00
Rhys Kidd
27e1503bc7 Support all Apple clang/LLVM 5.1+ 
clang has been reasonably good at standards compliance for a while now, and
the Apple-shipped clang-variant in Xcode remains fairly close to upstream.

Let's assume that the Apple-shipped clang-variant is sufficient for
building valgrind, provided it is above a minimum version of 5.1.
 2017-09-24 17:51:11 -04:00
Philippe Waroquiers
fdc75efce6 Follow up to 'On ppc, add generic_start_main.isra.0 as a below main function' 
massif/tests/mmapunmap on ppc now indicates a below main function.

Note: this ppc53 specific file is needed because the valgrind stack unwinder
does not properly unwind in main.
At the mmap syscall, gdb backtrace gives:
Breakpoint 3, 0x00000000041dbae0 in .__GI_mmap () from /lib64/libc.so.6
(gdb) bt

while the valgrind stack trace gives:
Thread 1: status = VgTs_Runnable (lwpid 64207)
==64207==    at 0x41DBAE0: mmap (in /usr/lib64/libc-2.17.so)
==64207==    by 0x10000833: f (mmapunmap.c:9)
==64207==    by 0x40E6BEB: (below main) (in /usr/lib64/libc-2.17.so)
client stack range: [0x1FFEFF0000 0x1FFF00FFFF] client SP: 0x1FFF00ECE0
valgrind stack top usage: 15632 of 1048576
 2017-09-23 16:41:18 +02:00
Philippe Waroquiers
8259193f1c On ppc, add generic_start_main.isra.0 as a below main function 
We can have stacktraces such as:
==41840==    by 0x10000927: a1 (deep.c:27)
==41840==    by 0x1000096F: main (deep.c:35)
==41840==    by 0x4126BEB: generic_start_main.isra.0 (in /usr/lib64/libc-2.17.so)
==41840==    by 0x4126E13: __libc_start_main (in /usr/lib64/libc-2.17.so)

So, add generic_start_main.isra.0 as a below main function.
This fixes the test  massif/tests/deep-D
 2017-09-23 13:49:05 +02:00
Philippe Waroquiers
d1232dd32a massif: match --ignore-fn with the first IP that has a fnname 
Currently, --ignore-fn is only matched with the top IP entries that
have a fnname. With this change, we first search for the first IP that
has a fnname.
This e.g. allows to ignore the allocation for a stacktrace such as:
   0x1 0x2 0x3 fn_to_ignore otherfn

This is then used in massif c++ tests new-cpp and overloaded-new to ignore
the c++ libstdc++ allocation similar to:
==10754== 72,704 bytes in 1 blocks are still reachable in loss record 10 of 10
==10754==    at 0x4C2BBCD: malloc (vg_replace_malloc.c:299)
==10754==    by 0x4EC39BF: ??? (in /usr/lib/x86_64-linux-gnu/libstdc++.so.6.0.22)
==10754==    by 0x400F8A9: call_init.part.0 (dl-init.c:72)
==10754==    by 0x400F9BA: call_init (dl-init.c:30)
==10754==    by 0x400F9BA: _dl_init (dl-init.c:120)
==10754==    by 0x4000C59: ??? (in /lib/x86_64-linux-gnu/ld-2.24.so)
 2017-09-23 13:30:42 +02:00
Philippe Waroquiers
f053756e28 Follow up to 345307 - Warning about "still reachable" memory when using libstdc++ from gcc 5 
The bug itself was solved in 3.12 by the addition of __gnu_cxx::__freeres
in the libstdc++ and have valgrind calling it before exit.

However, depending on the version of the libstdc++, the test leak_cpp_interior
was giving different results.

This commit adds some filtering specific to the test, so as to not depend
anymore of the absolute number of bytes leaked, and adds a suppression entry to
ignore the memory allocated by libstdc++.

This allows to have only 2 .exp files, instead of 4 (or worse, if
we would have to handle yet other .exp files depending on the libstdc++
version).
 2017-09-22 23:50:35 +02:00
Philippe Waroquiers
f1ff8597ef Implement static TLS code for more platforms 
gdbserver_tests/hgtls is failing on a number of platforms
as it looks like static tls handling is now needed.
So, omplement static tls for a few more platforms.
The formulas that are platform dependent are somewhat wild guesses
obtained with trial and errors.
Note that arm/arm64/ppc32 are not (yet) done
 2017-09-19 23:17:48 +02:00
Philippe Waroquiers
92ec6d08bb Fix assert on ppc32 due to typo for GPR28 
The below commit introduced a regression on ppc32
ommit 00d4667295a821fef9eb198abcb0c942dffb6045
Author: Ivo Raisr <ivosh@ivosh.net>
Date:   Wed Sep 6 08:10:36 2017 +0200

    Reorder allocatable registers for AMD64, X86, and PPC so that the callee saved are listed first.

    Helper calls always trash all caller saved registers. By listing the callee saved
    first then VEX register allocator (both v2 and v3) is more likely to pick them
    and does not need to spill that much before helper calls.

Investigation/fix done by Ivo.
 2017-09-19 23:12:35 +02:00
Ivo Raisr
b9df4c8dec Fix a typo bug in VEX register allocator v3. 
Also scanning a few more instructions ahead helps producing
better code.
 2017-09-16 18:49:56 +02:00
Petar Jovanovic
e4f2fdfa4b mips: finetune none/tests/(mips32|64)/test_math test 
Compiler may optimize out call to cbrt. Change test to prevent that.
Otherwise, the test does not exercise a desired codepath for cbrt, and it
prints precalculated value.
 2017-09-15 18:29:29 +02:00
Petar Jovanovic
211b0c303a mips: add clearing $ra to CLEAR_CALLER_SAVED_REGS macro 
Return address register belongs to caller saved registers, and compiler can
use it to store temporary values. Clear it.
 2017-09-15 16:04:18 +02:00
Ivo Raisr
00d4667295 Reorder allocatable registers for AMD64, X86, and PPC so that the callee saved are listed first. 
Helper calls always trash all caller saved registers. By listing the callee saved
first then VEX register allocator (both v2 and v3) is more likely to pick them
and does not need to spill that much before helper calls.
 2017-09-14 14:43:53 +02:00
Philippe Waroquiers
621cde90f7 Fix Bug 255603 - exp-sgcheck Assertion '!already_present' failed 
The code handling array bounds is not ready to accept a reference
to something else (not very clear what this reference could be) :
the code only expects directly the value of a bound.
So, it was using the reference (i.e. an offset somewehere in the debug
info) as the value of the bound.
This then gave huge bounds for some arrays, causing an overlap
in the stack variable handling code in exp-sgcheck.

Such references seems to be used sometimes for arrays with variable
size stack allocated.

Fix (or rather bypass) the problem by not considering that we have
a usable array bound when a reference is given.
 2017-09-13 22:47:11 +02:00
Rhys Kidd
2e5843802d Update AUTHORS 2017-09-10 11:08:20 -04:00
Rhys Kidd
128fd6e6a5 Fix syscall param msg->desc.port.name on macOS 10.12. bz#379373 
Based upon patch from Louis Brunner.
 2017-09-10 10:50:06 -04:00
Ivo Raisr
3117cd9637 Reduce number of spill instructions generated by VEX register allocator v3. 
Keeps track whether the bound real register has been reloaded from a virtual
register recently and if this real reg is still equal to that spill slot.
Avoids unnecessary spilling that vreg later, when this rreg needs
to be reserved, usually as a caller save register for a helper call.

Fixes BZ#384526.
 2017-09-10 09:14:26 +02:00
Ivo Raisr
1639d6c783 Small performance enhancement to VEX register allocator v2. 
Iterate only over real registers of the target hreg class.
 2017-09-04 09:22:15 +02:00
Rhys Kidd
55fe390c7a Fix missing pselect syscall (OS X 10.11). bz#379748 
Based upon patch from Louis Brunner.
 2017-09-03 12:55:52 -04:00
Ivo Raisr
82b3f16a18 Small fixes to notes about Inner/Outer setup. 2017-09-01 17:27:08 +02:00
Julian Seward
5cc18ff30b Improve the implementation of expensiveCmpEQorNE. 
.. so that the code it creates runs in approximately half the time it did
before.  This is in support of making the cost of expensive (exactly)
integer EQ/NE as low as possible, since the day will soon come when we'll
need to enable this by default.
 2017-08-31 11:11:25 +02:00