There will be a lot more to come.
On amd64 Linux
In faultstatus was seeing the division by zero and emitting a ud2 opcode.
In wrap3 a pair of mutually recursive functions were being inlined.
When forced not to be inlined GCC merged them into a single function.
It cannot see that the client requests have diffeent behaviour.
This is unfortunately a big and complex patch, to implement LD{,A}XP and
ST{,L}XP. These were omitted from the original AArch64 v8.0 implementation
for unknown reasons.
(Background) the patch is made significantly more complex because for AArch64
we actually have two implementations of the underlying
Load-Linked/Store-Conditional (LL/SC) machinery: a "primary" implementation,
which translates LL/SC more or less directly into IR and re-emits them at the
back end, and a "fallback" implementation that implements LL/SC "manually", by
taking advantage of the fact that V serialises thread execution, so we can
"implement" LL/SC by simulating a reservation using fields LLSC_* in the guest
state, and invalidating the reservation at every thread switch.
(Background) the fallback scheme is needed because the primary scheme is in
violation of the ARMv8 semantics in that it can (easily) introduce extra
memory references between the LL and SC, hence on some hardware causing the
reservation to always fail and so the simulated program to wind up looping
forever.
For these instructions, big picture:
* for the primary implementation, we take advantage of the fact that
IRStmt_LLSC allows I128 bit transactions to be represented. Hence we bundle
up the two 64-bit data elements into an I128 (or vice versa) and present a
single I128-typed IRStmt_LLSC in the IR. In the backend, those are
re-emitted as LDXP/STXP respectively. For LL/SC on 32-bit register pairs,
that bundling produces a single 64-bit item, and so the existing LL/SC
backend machinery handles it. The effect is that a doubleword 32-bit LL/SC
in the front end translates into a single 64-bit LL/SC in the back end.
Overall, though, the implementation is straightforward.
* for the fallback implementation, it is necessary to extend the guest state
field `guest_LLSC_DATA` to represent a 128-bit transaction, by splitting it
into _DATA_LO64 and DATA_HI64. Then, the implementation is an exact
analogue of the fallback implementation for single-word LL/SC. It takes
advantage of the fact that the backend already supports 128-bit CAS, as
fixed in bug 445354. As with the primary implementation, doubleword 32-bit
LL/SC is bundled into a single 64-bit transaction.
Detailed changes:
* new arm64 guest state fields LLSC_DATA_LO64/LLSC_DATA_LO64 to replace
guest_LLSC_DATA
* (ridealong fix) arm64 front end: a fix to a minor and harmless decoding bug
for the single-word LDX/STX case.
* arm64 front end: IR generation for LD{,A}XP/ST{,L}XP: tedious and
longwinded, but per comments above, an exact(ish) analogue of the singleword
case
* arm64 backend: new insns ARM64Instr_LdrEXP / ARM64Instr_StrEXP to wrap up 2
x 64 exclusive loads/stores. Per comments above, there's no need to handle
the 2 x 32 case.
* arm64 isel: translate I128-typed IRStmt_LLSC into the above two insns
* arm64 isel: some auxiliary bits and pieces needed to handle I128 values;
this is standard doubleword isel stuff
* arm64 isel: (ridealong fix): Ist_CAS: check for endianness of the CAS!
* arm64 isel: (ridealong) a couple of formatting fixes
* IR infrastructure: add support for I128 constants, done the same as V128
constants
* memcheck: handle shadow loads and stores for I128 values
* testcase: memcheck/tests/atomic_incs.c: on arm64, also test 128-bit atomic
addition, to check we really have atomicity right
* testcase: new test none/tests/arm64/ldxp_stxp.c, tests operation but not
atomicity. (Smoke test).
Contributed by Will Schmidt <will_schmidt@vnet.ibm.com>
This includes updates and adjustments as suggested by Carl.
Add tests that exercise PCRelative instructions.
These instructions are encoded with R==1, which indicate that
the memory accessed by the instruction is at a location
relative to the currently executing instruction.
These tests are built using -Wl,-text and -Wl,-bss
options to ensure the location of the target array is at a
location with a specific offset from the currently
executing instruction.
The write instructions are aimed at a large buffer in
the bss section; which is checked for updates at the
completion of each test.
In order to ensure consistent output across assorted
systems, the tests have been padded with ori, nop instructions
and align directives.
Detailed changes:
* Makefile.am: Add test_isa_3_1_R1_RT and test_isa_3_1_R1_XT tests.
* isa_3_1_helpers.h: Add identify_instruction_by_func_name() helper function
to indicate if the test is for R==1.
Add helpers to initialize and print changes to the pcrelative_write_target
array.
Add #define to help pad code with a series of eyecatcher ORI instructions.
* test_isa_3_1_R1_RT.c: New test.
* test_isa_3_1_R1_XT.c: New test.
* test_isa_3_1_R1_XT.stdout.exp: New expected output.
* test_isa_3_1_R1_XT.stdout.exp: New expected output.
* test_isa_3_1_R1_RT.stderr.exp: New expected output.
* test_isa_3_1_R1_RT.stderr.exp: New expected output.
* test_isa_3_1_R1_RT.vgtest: New test handler.
* test_isa_3_1_R1_XT.vgtest: New test handler.
* test_isa_3_1_common.c: Add indicators (updates_byte,updates_halfword,
updates_word) indicators to control the output from the R==1 tests.
Add helper check for "_R1" to indicate if instruction is coded with R==1.
Add init and print helpers for the pcrelative_write_target array.
In s390_irgen_EXRL, the offset is zero-extended instead of sign-extended,
typically causing Valgrind to crash when a negative offset occurs.
Fix this with a new helper function that calculates a "relative long"
address from a 32-bit offset. Replace other calculations of "relative
long" addresses by invocations of this function as well. And for
consistency, do the same with "relative" (short) addresses.
There's one remaining
memalign2.c:29:9: warning: unused variable 'piece' [-Wunused-variable]
because of a block of #if FreeBSD for memalign that looks unnecessary
Otherwise all that is left is a few like
warning: unknown warning option '-Wno-alloc-size-larger-than'; did you mean '-Wno-frame-larger-than='? [-Wunknown-warning-option]
because there is no standard for compiler arguments.
Various tests do things which we want to detect at runtime, like
ignoring the result of malloc or doing a deliberate impossibly large
allocation or operations that would result in overflowing or
truncated strings, that generate a warning from gcc.
In once case, mq_setattr called with new and old attrs overlapping,
this was explicitly fixed, in others -Wno-foobar was added to silence
the warning. This is safe even for older gcc, since a compiler will
ignore any -Wno-foobar they don't know about - since they do know they
won't warn for foobar.
cachegrind callgrind dhat exp-bbv gdbserver_tests massif none mpi shared
Mostly these are just updates (and new testcases) under new/tests
The other directories have just #ifdef changes
Some files for the freebsd port have not yet committed, but were
already referenced in the Makefiles. Remove those references for
now to make distcheck happy.
* coregrind/Makefile.am (valgrind_SOURCES): Remove
launcher-freebsd.c
* drd/tests/Makefile.am (check_PROGRAMS): Remove
thread_name_freebsd.
* none/tests/Makefile.am (SUBDIRS): Remove freebsd.
(DIST_SUBDIRS): Likewise.
* none/tests/freebsd/filter_stderr: Removed.
Files in the root directory
Several Makefile.am files that have dependencies on FreeBSD autoconf
variables. Included a few new filter files to act as placeholders
to create new freebsd subdirectories.
Updated NEWS with the FreeBSD bugzilla items plus a couple of other
items fixed indirectly.
Some inline assemblies in various s390x test cases miss specifying the
condition code "cc" in the clobber list. Although this has not actually
been seen to cause wrong code generation, it certainly might, so fix this.
Some GCC versions emit the following warnings for some s390x-specific test
cases:
warning: listing the stack pointer register '15' in a clobber list is
deprecated
warning: this 'else' clause does not
guard... [-Wmisleading-indentation] ...this statement, but...
Fix these.
Most of inline assemblies declaring r15 as clobbered do not actually
change its value. Only in stmg_wrap() it becomes necessary to save and
restore r15.
dash 0.5.11 produces slightly different error messagess.
The new exp file is similar to shell.stderr.exp-dash3 but
with the extra (second) "shell: " output removed.
The lxvx and stxvx tests are moved into their own separate
tests. Add the expec files for the new test.
Update the expected results for the altivec test.
Split out the mfspr tests into a separate test using command line option
"-M". The value in the LR and CTR registers changed. It appears the
changes are due to changes in the test program jm-insns.c. Splinting
these instructions out will help to minimize the size of future updates
when the test program changes.
For ISA 3.0 and beyond, the instructions also write the XER register.
Split the instructions out to a new command line option so we can create
an ISA 2.07 expect file, ISA 3.0 LE and ISA 3.0 BE expect file. The new
command line option is "-s" to just run just these four instructions.
Due to changes between the compiler and linker, we need to add .machine
arguments to configure file to properly detect the availability of the
dfp instructions.
Add print statement if HAS_DFP is not enabled to make it
easier to determine when HAS_DFP is not enabled.
GCC is no longer passing the "-many" flag to the assembler. So, the
inline assembly instructions statements need to use the .machine directives
for the specific platform.
(gcc commit e154242724b084380e3221df7c08fcdbd8460674 ; "[RS6000] Don't
pass -many to the assembler".
Hardware sync instruction (hwsync) added after the copy, paste and cpabort
instructions to improve the reliability of the test.
The mftgpr and mffgpr instructions are deprecated. Added comments in
VEX/priv/guest_ppc_toIR.c for the instructions stating the instructions
are deprecated. Valgrind support can be removed if the opcodes get reused
in the future. For now, leaving the functional support in Valgrind
for the instructions.
Removed the regression test power6_mf_gpr.c, expect files and vgtest file
from none/tests/ppc64.
The inputs into the vinsdlx,vinsdrx instructions changed as a result of
the impossible constraint issue fix. This patch updates the expected
results.
https://bugs.kde.org/show_bug.cgi?id=441534
This reworks the modulo operation as seen in
valgrind/none/tests/ppc64/test_isa_3_1_common.c:
initialize_source_registers().
Due to a GCC issue (PR101882), we will try to avoid a modulo operation with
both input and outputs set to a hard register. In this case, we can apply
the modulo operation to the args[] array value used to initialize the ra
value.
https://bugs.kde.org/show_bug.cgi?id=440906
Add test cases for verifying the new/enhanced instructions in the
vector-enhancements facility 2. For "vector string search" VSTRS add a
memcheck test case.
Make --track-fds=yes not report on file descriptors 0, 1, and 2 (stdin,
stdout, and stderr) by default. Add a new option --track-fds=all that does
report on the std file descriptors still being open. Update testsuite and
documentation.
Original patch by Peter Kelly <pmk@cs.adelaide.edu.au>
Updated by Daniel Fahlgren <daniel@fahlgren.se>
https://bugs.kde.org/show_bug.cgi?id=140939
