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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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Bug 436873 Added arm64 v8.2 vector FABD, FACGE, FACGT and FADD
This patch adds FP half-precision support for the following: FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> FABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> FACGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> FACGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> Fixes https://bugs.kde.org/show_bug.cgi?id=436873
This commit is contained in:
Assad Hashmi
parent
3ac8615140
commit
f048559cb0
@ -12863,6 +12863,50 @@ Bool dis_AdvSIMD_three_same_fp16(/*MB_OUT*/DisResult* dres, UInt insn,
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return True;
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}
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if (bitU == 1 && size == X11 && opcode == BITS5(0,0,0,1,0)) {
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/* -------- 1,11,00010 FABD 4h_4h_4h, 8h_8h_8h -------- */
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IRTemp rm = mk_get_IR_rounding_mode();
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IRTemp t1 = newTempV128();
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IRTemp t2 = newTempV128();
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assign(t1, triop(Iop_Sub16Fx8, mkexpr(rm), getQReg128(nn), getQReg128(mm)));
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assign(t2, unop(Iop_Abs16Fx8, mkexpr(t1)));
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putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t2));
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const HChar* arr = bitQ == 0 ? "4h" : "8h";
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DIP("%s %s.%s, %s.%s, %s.%s\n", "fabd",
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nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
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return True;
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}
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if (bitU == 1 && opcode == BITS5(0,0,1,0,1)) {
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/* -------- 1,01,00101 FACGE 4h_4h_4h 8h_8h_8h -------- */
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/* -------- 1,11,00101 FACGT 4h_4h_4h 8h_8h_8h -------- */
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Bool isGT = (size & 3) == 3;
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IROp opCMP = isGT ? Iop_CmpLT16Fx8 : Iop_CmpLE16Fx8;
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IROp opABS = Iop_Abs16Fx8;
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IRTemp t1 = newTempV128();
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assign(t1, binop(opCMP, unop(opABS, getQReg128(mm)),
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unop(opABS, getQReg128(nn))));
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putQReg128(dd, math_MAYBE_ZERO_HI64(bitQ, t1));
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const HChar* arr = bitQ == 0 ? "4h" : "8h";
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DIP("%s %s.%s, %s.%s, %s.%s\n", isGT ? "facgt" : "facge",
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nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
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return True;
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}
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if (bitU == 0 && size == X01 && opcode == BITS5(0,0,0,1,0)) {
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/* -------- 0,01,00010 FADD 4h_4h_4h, 8h_8h_8h -------- */
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IRTemp rm = mk_get_IR_rounding_mode();
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IRTemp t1 = newTempV128();
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IRTemp t2 = newTempV128();
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assign(t1, triop(Iop_Add16Fx8, mkexpr(rm), getQReg128(nn), getQReg128(mm)));
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assign(t2, math_MAYBE_ZERO_HI64(bitQ, t1));
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putQReg128(dd, mkexpr(t2));
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const HChar* arr = bitQ == 0 ? "4h" : "8h";
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DIP("%s %s.%s, %s.%s, %s.%s\n", "fadd",
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nameQReg128(dd), arr, nameQReg128(nn), arr, nameQReg128(mm), arr);
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return True;
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}
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return False;
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# undef INSN
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}
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@ -602,6 +602,7 @@ static void showARM64VecBinOp(/*OUT*/const HChar** nm,
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case ARM64vecb_FADD32x4: *nm = "fadd "; *ar = "4s"; return;
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case ARM64vecb_FADD16x8: *nm = "fadd "; *ar = "8h"; return;
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case ARM64vecb_FSUB32x4: *nm = "fsub "; *ar = "4s"; return;
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case ARM64vecb_FSUB16x8: *nm = "fsub "; *ar = "8h"; return;
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case ARM64vecb_FMUL32x4: *nm = "fmul "; *ar = "4s"; return;
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case ARM64vecb_FDIV32x4: *nm = "fdiv "; *ar = "4s"; return;
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case ARM64vecb_FMAX64x2: *nm = "fmax "; *ar = "2d"; return;
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@ -4946,6 +4947,9 @@ Int emit_ARM64Instr ( /*MB_MOD*/Bool* is_profInc,
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case ARM64vecb_FSUB32x4:
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*p++ = X_3_8_5_6_5_5(X010, X01110101, vM, X110101, vN, vD);
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break;
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case ARM64vecb_FSUB16x8:
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*p++ = X_3_8_5_6_5_5(X010, X01110110, vM, X000101, vN, vD);
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break;
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case ARM64vecb_FMUL64x2:
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*p++ = X_3_8_5_6_5_5(X011, X01110011, vM, X110111, vN, vD);
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break;
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@ -337,6 +337,7 @@ typedef
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ARM64vecb_FADD64x2, ARM64vecb_FADD32x4,
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ARM64vecb_FADD16x8,
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ARM64vecb_FSUB64x2, ARM64vecb_FSUB32x4,
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ARM64vecb_FSUB16x8,
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ARM64vecb_FMUL64x2, ARM64vecb_FMUL32x4,
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ARM64vecb_FDIV64x2, ARM64vecb_FDIV32x4,
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ARM64vecb_FMAX64x2, ARM64vecb_FMAX32x4,
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@ -3173,6 +3173,7 @@ static HReg iselV128Expr_wrk ( ISelEnv* env, IRExpr* e )
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case Iop_Mul32Fx4: vecbop = ARM64vecb_FMUL32x4; break;
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case Iop_Div32Fx4: vecbop = ARM64vecb_FDIV32x4; break;
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case Iop_Add16Fx8: vecbop = ARM64vecb_FADD16x8; break;
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case Iop_Sub16Fx8: vecbop = ARM64vecb_FSUB16x8; break;
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default: break;
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}
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if (vecbop != ARM64vecb_INVALID) {
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@ -656,6 +656,7 @@ void ppIROp ( IROp op )
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case Iop_CmpNEZ8x8: vex_printf("CmpNEZ8x8"); return;
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case Iop_Add16Fx8: vex_printf("Add16Fx8"); return;
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case Iop_Sub16Fx8: vex_printf("Sub16Fx8"); return;
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case Iop_Add32Fx4: vex_printf("Add32Fx4"); return;
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case Iop_Add32Fx2: vex_printf("Add32Fx2"); return;
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case Iop_Add32F0x4: vex_printf("Add32F0x4"); return;
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@ -1586,7 +1587,7 @@ Bool primopMightTrap ( IROp op )
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case Iop_DPBtoBCD: case Iop_BCDtoDPB: case Iop_BCDAdd: case Iop_BCDSub:
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case Iop_I128StoBCD128: case Iop_BCD128toI128S: case Iop_ReinterpI64asD64:
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case Iop_ReinterpD64asI64:
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case Iop_Add16Fx8:
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case Iop_Add16Fx8: case Iop_Sub16Fx8:
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case Iop_Add32Fx4: case Iop_Sub32Fx4: case Iop_Mul32Fx4: case Iop_Div32Fx4:
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case Iop_Max32Fx4: case Iop_Min32Fx4:
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case Iop_Add32Fx2: case Iop_Sub32Fx2:
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@ -3831,7 +3832,7 @@ void typeOfPrimop ( IROp op,
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case Iop_Mul64Fx2: case Iop_Div64Fx2:
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case Iop_Add32Fx4: case Iop_Sub32Fx4:
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case Iop_Mul32Fx4: case Iop_Div32Fx4:
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case Iop_Add16Fx8:
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case Iop_Add16Fx8: case Iop_Sub16Fx8:
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case Iop_F64x2_2toQ32x4: case Iop_F32x4_2toQ16x8:
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TERNARY(ity_RMode,Ity_V128,Ity_V128, Ity_V128);
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@ -1380,7 +1380,7 @@ typedef
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Iop_Sqrt16Fx8,
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/* ternary :: IRRoundingMode(I32) x V128 x V128 -> V128 */
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Iop_Add16Fx8,
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Iop_Add16Fx8, Iop_Sub16Fx8,
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/* binary */
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Iop_CmpLT16Fx8, Iop_CmpLE16Fx8,
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@ -3473,6 +3473,7 @@ IRAtom* expr2vbits_Triop ( MCEnv* mce,
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IR is implemented.
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*/
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case Iop_Add16Fx8:
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case Iop_Sub16Fx8:
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return binary16Fx8_w_rm(mce, vatom1, vatom2, vatom3);
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case Iop_Add32Fx8:
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@ -619,6 +619,7 @@ static irop_t irops[] = {
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{ DEFOP(Iop_ReinterpD64asI64, UNDEF_SAME), .s390x = 1, .ppc64 = 1, .ppc32 = 1 },
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/* ------------------ 128-bit SIMD FP. ------------------ */
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{ DEFOP(Iop_Add16Fx8, UNDEF_UNKNOWN), },
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{ DEFOP(Iop_Sub16Fx8, UNDEF_UNKNOWN), },
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{ DEFOP(Iop_Add32Fx4, UNDEF_UNKNOWN), },
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{ DEFOP(Iop_Sub32Fx4, UNDEF_UNKNOWN), },
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{ DEFOP(Iop_Mul32Fx4, UNDEF_UNKNOWN), },
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@ -2163,6 +2163,70 @@ GEN_THREEVEC_TEST(fadd_h_27_28_29, "fadd h27, h28, h29", 27, 28, 29)
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GEN_THREEVEC_TEST(fadd_h_28_29_30, "fadd h28, h29, h30", 28, 29, 30)
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GEN_THREEVEC_TEST(fadd_h_29_30_31, "fadd h29, h30, h31", 29, 30, 31)
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// FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
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GEN_THREEVEC_TEST(fadd_8h_00_01_02, "fadd v0.8h, v1.8h, v2.8h", 0, 1, 2)
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GEN_THREEVEC_TEST(fadd_8h_01_02_03, "fadd v1.8h, v2.8h, v3.8h", 1, 2, 3)
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GEN_THREEVEC_TEST(fadd_8h_02_03_04, "fadd v2.8h, v3.8h, v4.8h", 2, 3, 4)
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GEN_THREEVEC_TEST(fadd_8h_03_04_05, "fadd v3.8h, v4.8h, v5.8h", 3, 4, 5)
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GEN_THREEVEC_TEST(fadd_8h_04_05_06, "fadd v4.8h, v5.8h, v6.8h", 4, 5, 6)
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GEN_THREEVEC_TEST(fadd_8h_05_06_07, "fadd v5.8h, v6.8h, v7.8h", 5, 6, 7)
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GEN_THREEVEC_TEST(fadd_8h_06_07_08, "fadd v6.8h, v7.8h, v8.8h", 6, 7, 8)
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GEN_THREEVEC_TEST(fadd_8h_07_08_09, "fadd v7.8h, v8.8h, v9.8h", 7, 8, 9)
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GEN_THREEVEC_TEST(fadd_8h_08_09_10, "fadd v8.8h, v9.8h, v10.8h", 8, 9, 10)
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GEN_THREEVEC_TEST(fadd_8h_09_10_11, "fadd v9.8h, v10.8h, v11.8h", 9, 10, 11)
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GEN_THREEVEC_TEST(fadd_8h_10_11_12, "fadd v10.8h, v11.8h, v12.8h", 10, 11, 12)
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GEN_THREEVEC_TEST(fadd_8h_11_12_13, "fadd v11.8h, v12.8h, v13.8h", 11, 12, 13)
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GEN_THREEVEC_TEST(fadd_8h_12_13_14, "fadd v12.8h, v13.8h, v14.8h", 12, 13, 14)
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GEN_THREEVEC_TEST(fadd_8h_13_14_15, "fadd v13.8h, v14.8h, v15.8h", 13, 14, 15)
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GEN_THREEVEC_TEST(fadd_8h_14_15_16, "fadd v14.8h, v15.8h, v16.8h", 14, 15, 16)
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GEN_THREEVEC_TEST(fadd_8h_15_16_17, "fadd v15.8h, v16.8h, v17.8h", 15, 16, 17)
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GEN_THREEVEC_TEST(fadd_8h_16_17_18, "fadd v16.8h, v17.8h, v18.8h", 16, 17, 18)
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GEN_THREEVEC_TEST(fadd_8h_17_18_19, "fadd v17.8h, v18.8h, v19.8h", 17, 18, 19)
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GEN_THREEVEC_TEST(fadd_8h_18_19_20, "fadd v18.8h, v19.8h, v20.8h", 18, 19, 20)
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GEN_THREEVEC_TEST(fadd_8h_19_20_21, "fadd v19.8h, v20.8h, v21.8h", 19, 20, 21)
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GEN_THREEVEC_TEST(fadd_8h_20_21_22, "fadd v20.8h, v21.8h, v22.8h", 20, 21, 22)
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GEN_THREEVEC_TEST(fadd_8h_21_22_23, "fadd v21.8h, v22.8h, v23.8h", 21, 22, 23)
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GEN_THREEVEC_TEST(fadd_8h_22_23_24, "fadd v22.8h, v23.8h, v24.8h", 22, 23, 24)
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GEN_THREEVEC_TEST(fadd_8h_23_24_25, "fadd v23.8h, v24.8h, v25.8h", 23, 24, 25)
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GEN_THREEVEC_TEST(fadd_8h_24_25_26, "fadd v24.8h, v25.8h, v26.8h", 24, 25, 26)
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GEN_THREEVEC_TEST(fadd_8h_25_26_27, "fadd v25.8h, v26.8h, v27.8h", 25, 26, 27)
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GEN_THREEVEC_TEST(fadd_8h_26_27_28, "fadd v26.8h, v27.8h, v28.8h", 26, 27, 28)
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GEN_THREEVEC_TEST(fadd_8h_27_28_29, "fadd v27.8h, v28.8h, v29.8h", 27, 28, 29)
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GEN_THREEVEC_TEST(fadd_8h_28_29_30, "fadd v28.8h, v29.8h, v30.8h", 28, 29, 30)
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GEN_THREEVEC_TEST(fadd_8h_29_30_31, "fadd v29.8h, v30.8h, v31.8h", 29, 30, 31)
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GEN_THREEVEC_TEST(fadd_4h_00_01_02, "fadd v0.4h, v1.4h, v2.4h", 0, 1, 2)
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GEN_THREEVEC_TEST(fadd_4h_01_02_03, "fadd v1.4h, v2.4h, v3.4h", 1, 2, 3)
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GEN_THREEVEC_TEST(fadd_4h_02_03_04, "fadd v2.4h, v3.4h, v4.4h", 2, 3, 4)
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GEN_THREEVEC_TEST(fadd_4h_03_04_05, "fadd v3.4h, v4.4h, v5.4h", 3, 4, 5)
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GEN_THREEVEC_TEST(fadd_4h_04_05_06, "fadd v4.4h, v5.4h, v6.4h", 4, 5, 6)
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GEN_THREEVEC_TEST(fadd_4h_05_06_07, "fadd v5.4h, v6.4h, v7.4h", 5, 6, 7)
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GEN_THREEVEC_TEST(fadd_4h_06_07_08, "fadd v6.4h, v7.4h, v8.4h", 6, 7, 8)
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GEN_THREEVEC_TEST(fadd_4h_07_08_09, "fadd v7.4h, v8.4h, v9.4h", 7, 8, 9)
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GEN_THREEVEC_TEST(fadd_4h_08_09_10, "fadd v8.4h, v9.4h, v10.4h", 8, 9, 10)
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GEN_THREEVEC_TEST(fadd_4h_09_10_11, "fadd v9.4h, v10.4h, v11.4h", 9, 10, 11)
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GEN_THREEVEC_TEST(fadd_4h_10_11_12, "fadd v10.4h, v11.4h, v12.4h", 10, 11, 12)
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GEN_THREEVEC_TEST(fadd_4h_11_12_13, "fadd v11.4h, v12.4h, v13.4h", 11, 12, 13)
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GEN_THREEVEC_TEST(fadd_4h_12_13_14, "fadd v12.4h, v13.4h, v14.4h", 12, 13, 14)
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GEN_THREEVEC_TEST(fadd_4h_13_14_15, "fadd v13.4h, v14.4h, v15.4h", 13, 14, 15)
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GEN_THREEVEC_TEST(fadd_4h_14_15_16, "fadd v14.4h, v15.4h, v16.4h", 14, 15, 16)
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GEN_THREEVEC_TEST(fadd_4h_15_16_17, "fadd v15.4h, v16.4h, v17.4h", 15, 16, 17)
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GEN_THREEVEC_TEST(fadd_4h_16_17_18, "fadd v16.4h, v17.4h, v18.4h", 16, 17, 18)
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GEN_THREEVEC_TEST(fadd_4h_17_18_19, "fadd v17.4h, v18.4h, v19.4h", 17, 18, 19)
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GEN_THREEVEC_TEST(fadd_4h_18_19_20, "fadd v18.4h, v19.4h, v20.4h", 18, 19, 20)
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GEN_THREEVEC_TEST(fadd_4h_19_20_21, "fadd v19.4h, v20.4h, v21.4h", 19, 20, 21)
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GEN_THREEVEC_TEST(fadd_4h_20_21_22, "fadd v20.4h, v21.4h, v22.4h", 20, 21, 22)
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GEN_THREEVEC_TEST(fadd_4h_21_22_23, "fadd v21.4h, v22.4h, v23.4h", 21, 22, 23)
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GEN_THREEVEC_TEST(fadd_4h_22_23_24, "fadd v22.4h, v23.4h, v24.4h", 22, 23, 24)
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GEN_THREEVEC_TEST(fadd_4h_23_24_25, "fadd v23.4h, v24.4h, v25.4h", 23, 24, 25)
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GEN_THREEVEC_TEST(fadd_4h_24_25_26, "fadd v24.4h, v25.4h, v26.4h", 24, 25, 26)
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GEN_THREEVEC_TEST(fadd_4h_25_26_27, "fadd v25.4h, v26.4h, v27.4h", 25, 26, 27)
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GEN_THREEVEC_TEST(fadd_4h_26_27_28, "fadd v26.4h, v27.4h, v28.4h", 26, 27, 28)
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GEN_THREEVEC_TEST(fadd_4h_27_28_29, "fadd v27.4h, v28.4h, v29.4h", 27, 28, 29)
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GEN_THREEVEC_TEST(fadd_4h_28_29_30, "fadd v28.4h, v29.4h, v30.4h", 28, 29, 30)
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GEN_THREEVEC_TEST(fadd_4h_29_30_31, "fadd v29.4h, v30.4h, v31.4h", 29, 30, 31)
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// FADDP <V><d>, <Vn>.<T>
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GEN_TWOVEC_TEST(faddp_h_2h_00_01, "faddp h0, v1.2h", 0, 1)
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@ -2594,6 +2658,70 @@ GEN_THREEVEC_TEST(fabd_h_27_28_29, "fabd h27, h28, h29", 27, 28, 29)
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GEN_THREEVEC_TEST(fabd_h_28_29_30, "fabd h28, h29, h30", 28, 29, 30)
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GEN_THREEVEC_TEST(fabd_h_29_30_31, "fabd h29, h30, h31", 29, 30, 31)
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// FABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
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GEN_THREEVEC_TEST(fabd_8h_00_01_02, "fabd v0.8h, v1.8h, v2.8h", 0, 1, 2)
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GEN_THREEVEC_TEST(fabd_8h_01_02_03, "fabd v1.8h, v2.8h, v3.8h", 1, 2, 3)
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GEN_THREEVEC_TEST(fabd_8h_02_03_04, "fabd v2.8h, v3.8h, v4.8h", 2, 3, 4)
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GEN_THREEVEC_TEST(fabd_8h_03_04_05, "fabd v3.8h, v4.8h, v5.8h", 3, 4, 5)
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||||
GEN_THREEVEC_TEST(fabd_8h_04_05_06, "fabd v4.8h, v5.8h, v6.8h", 4, 5, 6)
|
||||
GEN_THREEVEC_TEST(fabd_8h_05_06_07, "fabd v5.8h, v6.8h, v7.8h", 5, 6, 7)
|
||||
GEN_THREEVEC_TEST(fabd_8h_06_07_08, "fabd v6.8h, v7.8h, v8.8h", 6, 7, 8)
|
||||
GEN_THREEVEC_TEST(fabd_8h_07_08_09, "fabd v7.8h, v8.8h, v9.8h", 7, 8, 9)
|
||||
GEN_THREEVEC_TEST(fabd_8h_08_09_10, "fabd v8.8h, v9.8h, v10.8h", 8, 9, 10)
|
||||
GEN_THREEVEC_TEST(fabd_8h_09_10_11, "fabd v9.8h, v10.8h, v11.8h", 9, 10, 11)
|
||||
GEN_THREEVEC_TEST(fabd_8h_10_11_12, "fabd v10.8h, v11.8h, v12.8h", 10, 11, 12)
|
||||
GEN_THREEVEC_TEST(fabd_8h_11_12_13, "fabd v11.8h, v12.8h, v13.8h", 11, 12, 13)
|
||||
GEN_THREEVEC_TEST(fabd_8h_12_13_14, "fabd v12.8h, v13.8h, v14.8h", 12, 13, 14)
|
||||
GEN_THREEVEC_TEST(fabd_8h_13_14_15, "fabd v13.8h, v14.8h, v15.8h", 13, 14, 15)
|
||||
GEN_THREEVEC_TEST(fabd_8h_14_15_16, "fabd v14.8h, v15.8h, v16.8h", 14, 15, 16)
|
||||
GEN_THREEVEC_TEST(fabd_8h_15_16_17, "fabd v15.8h, v16.8h, v17.8h", 15, 16, 17)
|
||||
GEN_THREEVEC_TEST(fabd_8h_16_17_18, "fabd v16.8h, v17.8h, v18.8h", 16, 17, 18)
|
||||
GEN_THREEVEC_TEST(fabd_8h_17_18_19, "fabd v17.8h, v18.8h, v19.8h", 17, 18, 19)
|
||||
GEN_THREEVEC_TEST(fabd_8h_18_19_20, "fabd v18.8h, v19.8h, v20.8h", 18, 19, 20)
|
||||
GEN_THREEVEC_TEST(fabd_8h_19_20_21, "fabd v19.8h, v20.8h, v21.8h", 19, 20, 21)
|
||||
GEN_THREEVEC_TEST(fabd_8h_20_21_22, "fabd v20.8h, v21.8h, v22.8h", 20, 21, 22)
|
||||
GEN_THREEVEC_TEST(fabd_8h_21_22_23, "fabd v21.8h, v22.8h, v23.8h", 21, 22, 23)
|
||||
GEN_THREEVEC_TEST(fabd_8h_22_23_24, "fabd v22.8h, v23.8h, v24.8h", 22, 23, 24)
|
||||
GEN_THREEVEC_TEST(fabd_8h_23_24_25, "fabd v23.8h, v24.8h, v25.8h", 23, 24, 25)
|
||||
GEN_THREEVEC_TEST(fabd_8h_24_25_26, "fabd v24.8h, v25.8h, v26.8h", 24, 25, 26)
|
||||
GEN_THREEVEC_TEST(fabd_8h_25_26_27, "fabd v25.8h, v26.8h, v27.8h", 25, 26, 27)
|
||||
GEN_THREEVEC_TEST(fabd_8h_26_27_28, "fabd v26.8h, v27.8h, v28.8h", 26, 27, 28)
|
||||
GEN_THREEVEC_TEST(fabd_8h_27_28_29, "fabd v27.8h, v28.8h, v29.8h", 27, 28, 29)
|
||||
GEN_THREEVEC_TEST(fabd_8h_28_29_30, "fabd v28.8h, v29.8h, v30.8h", 28, 29, 30)
|
||||
GEN_THREEVEC_TEST(fabd_8h_29_30_31, "fabd v29.8h, v30.8h, v31.8h", 29, 30, 31)
|
||||
|
||||
GEN_THREEVEC_TEST(fabd_4h_00_01_02, "fabd v0.4h, v1.4h, v2.4h", 0, 1, 2)
|
||||
GEN_THREEVEC_TEST(fabd_4h_01_02_03, "fabd v1.4h, v2.4h, v3.4h", 1, 2, 3)
|
||||
GEN_THREEVEC_TEST(fabd_4h_02_03_04, "fabd v2.4h, v3.4h, v4.4h", 2, 3, 4)
|
||||
GEN_THREEVEC_TEST(fabd_4h_03_04_05, "fabd v3.4h, v4.4h, v5.4h", 3, 4, 5)
|
||||
GEN_THREEVEC_TEST(fabd_4h_04_05_06, "fabd v4.4h, v5.4h, v6.4h", 4, 5, 6)
|
||||
GEN_THREEVEC_TEST(fabd_4h_05_06_07, "fabd v5.4h, v6.4h, v7.4h", 5, 6, 7)
|
||||
GEN_THREEVEC_TEST(fabd_4h_06_07_08, "fabd v6.4h, v7.4h, v8.4h", 6, 7, 8)
|
||||
GEN_THREEVEC_TEST(fabd_4h_07_08_09, "fabd v7.4h, v8.4h, v9.4h", 7, 8, 9)
|
||||
GEN_THREEVEC_TEST(fabd_4h_08_09_10, "fabd v8.4h, v9.4h, v10.4h", 8, 9, 10)
|
||||
GEN_THREEVEC_TEST(fabd_4h_09_10_11, "fabd v9.4h, v10.4h, v11.4h", 9, 10, 11)
|
||||
GEN_THREEVEC_TEST(fabd_4h_10_11_12, "fabd v10.4h, v11.4h, v12.4h", 10, 11, 12)
|
||||
GEN_THREEVEC_TEST(fabd_4h_11_12_13, "fabd v11.4h, v12.4h, v13.4h", 11, 12, 13)
|
||||
GEN_THREEVEC_TEST(fabd_4h_12_13_14, "fabd v12.4h, v13.4h, v14.4h", 12, 13, 14)
|
||||
GEN_THREEVEC_TEST(fabd_4h_13_14_15, "fabd v13.4h, v14.4h, v15.4h", 13, 14, 15)
|
||||
GEN_THREEVEC_TEST(fabd_4h_14_15_16, "fabd v14.4h, v15.4h, v16.4h", 14, 15, 16)
|
||||
GEN_THREEVEC_TEST(fabd_4h_15_16_17, "fabd v15.4h, v16.4h, v17.4h", 15, 16, 17)
|
||||
GEN_THREEVEC_TEST(fabd_4h_16_17_18, "fabd v16.4h, v17.4h, v18.4h", 16, 17, 18)
|
||||
GEN_THREEVEC_TEST(fabd_4h_17_18_19, "fabd v17.4h, v18.4h, v19.4h", 17, 18, 19)
|
||||
GEN_THREEVEC_TEST(fabd_4h_18_19_20, "fabd v18.4h, v19.4h, v20.4h", 18, 19, 20)
|
||||
GEN_THREEVEC_TEST(fabd_4h_19_20_21, "fabd v19.4h, v20.4h, v21.4h", 19, 20, 21)
|
||||
GEN_THREEVEC_TEST(fabd_4h_20_21_22, "fabd v20.4h, v21.4h, v22.4h", 20, 21, 22)
|
||||
GEN_THREEVEC_TEST(fabd_4h_21_22_23, "fabd v21.4h, v22.4h, v23.4h", 21, 22, 23)
|
||||
GEN_THREEVEC_TEST(fabd_4h_22_23_24, "fabd v22.4h, v23.4h, v24.4h", 22, 23, 24)
|
||||
GEN_THREEVEC_TEST(fabd_4h_23_24_25, "fabd v23.4h, v24.4h, v25.4h", 23, 24, 25)
|
||||
GEN_THREEVEC_TEST(fabd_4h_24_25_26, "fabd v24.4h, v25.4h, v26.4h", 24, 25, 26)
|
||||
GEN_THREEVEC_TEST(fabd_4h_25_26_27, "fabd v25.4h, v26.4h, v27.4h", 25, 26, 27)
|
||||
GEN_THREEVEC_TEST(fabd_4h_26_27_28, "fabd v26.4h, v27.4h, v28.4h", 26, 27, 28)
|
||||
GEN_THREEVEC_TEST(fabd_4h_27_28_29, "fabd v27.4h, v28.4h, v29.4h", 27, 28, 29)
|
||||
GEN_THREEVEC_TEST(fabd_4h_28_29_30, "fabd v28.4h, v29.4h, v30.4h", 28, 29, 30)
|
||||
GEN_THREEVEC_TEST(fabd_4h_29_30_31, "fabd v29.4h, v30.4h, v31.4h", 29, 30, 31)
|
||||
|
||||
// FACGT <Hd>, <Hn>, <Hm>
|
||||
|
||||
GEN_THREEVEC_TEST(facgt_h_00_01_02, "facgt h0, h1, h2", 0, 1, 2)
|
||||
@ -2627,6 +2755,70 @@ GEN_THREEVEC_TEST(facgt_h_27_28_29, "facgt h27, h28, h29", 27, 28, 29)
|
||||
GEN_THREEVEC_TEST(facgt_h_28_29_30, "facgt h28, h29, h30", 28, 29, 30)
|
||||
GEN_THREEVEC_TEST(facgt_h_29_30_31, "facgt h29, h30, h31", 29, 30, 31)
|
||||
|
||||
// FACGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
|
||||
|
||||
GEN_THREEVEC_TEST(facgt_8h_00_01_02, "facgt v0.8h, v1.8h, v2.8h", 0, 1, 2)
|
||||
GEN_THREEVEC_TEST(facgt_8h_01_02_03, "facgt v1.8h, v2.8h, v3.8h", 1, 2, 3)
|
||||
GEN_THREEVEC_TEST(facgt_8h_02_03_04, "facgt v2.8h, v3.8h, v4.8h", 2, 3, 4)
|
||||
GEN_THREEVEC_TEST(facgt_8h_03_04_05, "facgt v3.8h, v4.8h, v5.8h", 3, 4, 5)
|
||||
GEN_THREEVEC_TEST(facgt_8h_04_05_06, "facgt v4.8h, v5.8h, v6.8h", 4, 5, 6)
|
||||
GEN_THREEVEC_TEST(facgt_8h_05_06_07, "facgt v5.8h, v6.8h, v7.8h", 5, 6, 7)
|
||||
GEN_THREEVEC_TEST(facgt_8h_06_07_08, "facgt v6.8h, v7.8h, v8.8h", 6, 7, 8)
|
||||
GEN_THREEVEC_TEST(facgt_8h_07_08_09, "facgt v7.8h, v8.8h, v9.8h", 7, 8, 9)
|
||||
GEN_THREEVEC_TEST(facgt_8h_08_09_10, "facgt v8.8h, v9.8h, v10.8h", 8, 9, 10)
|
||||
GEN_THREEVEC_TEST(facgt_8h_09_10_11, "facgt v9.8h, v10.8h, v11.8h", 9, 10, 11)
|
||||
GEN_THREEVEC_TEST(facgt_8h_10_11_12, "facgt v10.8h, v11.8h, v12.8h", 10, 11, 12)
|
||||
GEN_THREEVEC_TEST(facgt_8h_11_12_13, "facgt v11.8h, v12.8h, v13.8h", 11, 12, 13)
|
||||
GEN_THREEVEC_TEST(facgt_8h_12_13_14, "facgt v12.8h, v13.8h, v14.8h", 12, 13, 14)
|
||||
GEN_THREEVEC_TEST(facgt_8h_13_14_15, "facgt v13.8h, v14.8h, v15.8h", 13, 14, 15)
|
||||
GEN_THREEVEC_TEST(facgt_8h_14_15_16, "facgt v14.8h, v15.8h, v16.8h", 14, 15, 16)
|
||||
GEN_THREEVEC_TEST(facgt_8h_15_16_17, "facgt v15.8h, v16.8h, v17.8h", 15, 16, 17)
|
||||
GEN_THREEVEC_TEST(facgt_8h_16_17_18, "facgt v16.8h, v17.8h, v18.8h", 16, 17, 18)
|
||||
GEN_THREEVEC_TEST(facgt_8h_17_18_19, "facgt v17.8h, v18.8h, v19.8h", 17, 18, 19)
|
||||
GEN_THREEVEC_TEST(facgt_8h_18_19_20, "facgt v18.8h, v19.8h, v20.8h", 18, 19, 20)
|
||||
GEN_THREEVEC_TEST(facgt_8h_19_20_21, "facgt v19.8h, v20.8h, v21.8h", 19, 20, 21)
|
||||
GEN_THREEVEC_TEST(facgt_8h_20_21_22, "facgt v20.8h, v21.8h, v22.8h", 20, 21, 22)
|
||||
GEN_THREEVEC_TEST(facgt_8h_21_22_23, "facgt v21.8h, v22.8h, v23.8h", 21, 22, 23)
|
||||
GEN_THREEVEC_TEST(facgt_8h_22_23_24, "facgt v22.8h, v23.8h, v24.8h", 22, 23, 24)
|
||||
GEN_THREEVEC_TEST(facgt_8h_23_24_25, "facgt v23.8h, v24.8h, v25.8h", 23, 24, 25)
|
||||
GEN_THREEVEC_TEST(facgt_8h_24_25_26, "facgt v24.8h, v25.8h, v26.8h", 24, 25, 26)
|
||||
GEN_THREEVEC_TEST(facgt_8h_25_26_27, "facgt v25.8h, v26.8h, v27.8h", 25, 26, 27)
|
||||
GEN_THREEVEC_TEST(facgt_8h_26_27_28, "facgt v26.8h, v27.8h, v28.8h", 26, 27, 28)
|
||||
GEN_THREEVEC_TEST(facgt_8h_27_28_29, "facgt v27.8h, v28.8h, v29.8h", 27, 28, 29)
|
||||
GEN_THREEVEC_TEST(facgt_8h_28_29_30, "facgt v28.8h, v29.8h, v30.8h", 28, 29, 30)
|
||||
GEN_THREEVEC_TEST(facgt_8h_29_30_31, "facgt v29.8h, v30.8h, v31.8h", 29, 30, 31)
|
||||
|
||||
GEN_THREEVEC_TEST(facgt_4h_00_01_02, "facgt v0.4h, v1.4h, v2.4h", 0, 1, 2)
|
||||
GEN_THREEVEC_TEST(facgt_4h_01_02_03, "facgt v1.4h, v2.4h, v3.4h", 1, 2, 3)
|
||||
GEN_THREEVEC_TEST(facgt_4h_02_03_04, "facgt v2.4h, v3.4h, v4.4h", 2, 3, 4)
|
||||
GEN_THREEVEC_TEST(facgt_4h_03_04_05, "facgt v3.4h, v4.4h, v5.4h", 3, 4, 5)
|
||||
GEN_THREEVEC_TEST(facgt_4h_04_05_06, "facgt v4.4h, v5.4h, v6.4h", 4, 5, 6)
|
||||
GEN_THREEVEC_TEST(facgt_4h_05_06_07, "facgt v5.4h, v6.4h, v7.4h", 5, 6, 7)
|
||||
GEN_THREEVEC_TEST(facgt_4h_06_07_08, "facgt v6.4h, v7.4h, v8.4h", 6, 7, 8)
|
||||
GEN_THREEVEC_TEST(facgt_4h_07_08_09, "facgt v7.4h, v8.4h, v9.4h", 7, 8, 9)
|
||||
GEN_THREEVEC_TEST(facgt_4h_08_09_10, "facgt v8.4h, v9.4h, v10.4h", 8, 9, 10)
|
||||
GEN_THREEVEC_TEST(facgt_4h_09_10_11, "facgt v9.4h, v10.4h, v11.4h", 9, 10, 11)
|
||||
GEN_THREEVEC_TEST(facgt_4h_10_11_12, "facgt v10.4h, v11.4h, v12.4h", 10, 11, 12)
|
||||
GEN_THREEVEC_TEST(facgt_4h_11_12_13, "facgt v11.4h, v12.4h, v13.4h", 11, 12, 13)
|
||||
GEN_THREEVEC_TEST(facgt_4h_12_13_14, "facgt v12.4h, v13.4h, v14.4h", 12, 13, 14)
|
||||
GEN_THREEVEC_TEST(facgt_4h_13_14_15, "facgt v13.4h, v14.4h, v15.4h", 13, 14, 15)
|
||||
GEN_THREEVEC_TEST(facgt_4h_14_15_16, "facgt v14.4h, v15.4h, v16.4h", 14, 15, 16)
|
||||
GEN_THREEVEC_TEST(facgt_4h_15_16_17, "facgt v15.4h, v16.4h, v17.4h", 15, 16, 17)
|
||||
GEN_THREEVEC_TEST(facgt_4h_16_17_18, "facgt v16.4h, v17.4h, v18.4h", 16, 17, 18)
|
||||
GEN_THREEVEC_TEST(facgt_4h_17_18_19, "facgt v17.4h, v18.4h, v19.4h", 17, 18, 19)
|
||||
GEN_THREEVEC_TEST(facgt_4h_18_19_20, "facgt v18.4h, v19.4h, v20.4h", 18, 19, 20)
|
||||
GEN_THREEVEC_TEST(facgt_4h_19_20_21, "facgt v19.4h, v20.4h, v21.4h", 19, 20, 21)
|
||||
GEN_THREEVEC_TEST(facgt_4h_20_21_22, "facgt v20.4h, v21.4h, v22.4h", 20, 21, 22)
|
||||
GEN_THREEVEC_TEST(facgt_4h_21_22_23, "facgt v21.4h, v22.4h, v23.4h", 21, 22, 23)
|
||||
GEN_THREEVEC_TEST(facgt_4h_22_23_24, "facgt v22.4h, v23.4h, v24.4h", 22, 23, 24)
|
||||
GEN_THREEVEC_TEST(facgt_4h_23_24_25, "facgt v23.4h, v24.4h, v25.4h", 23, 24, 25)
|
||||
GEN_THREEVEC_TEST(facgt_4h_24_25_26, "facgt v24.4h, v25.4h, v26.4h", 24, 25, 26)
|
||||
GEN_THREEVEC_TEST(facgt_4h_25_26_27, "facgt v25.4h, v26.4h, v27.4h", 25, 26, 27)
|
||||
GEN_THREEVEC_TEST(facgt_4h_26_27_28, "facgt v26.4h, v27.4h, v28.4h", 26, 27, 28)
|
||||
GEN_THREEVEC_TEST(facgt_4h_27_28_29, "facgt v27.4h, v28.4h, v29.4h", 27, 28, 29)
|
||||
GEN_THREEVEC_TEST(facgt_4h_28_29_30, "facgt v28.4h, v29.4h, v30.4h", 28, 29, 30)
|
||||
GEN_THREEVEC_TEST(facgt_4h_29_30_31, "facgt v29.4h, v30.4h, v31.4h", 29, 30, 31)
|
||||
|
||||
// FACGE <Hd>, <Hn>, <Hm>
|
||||
|
||||
GEN_THREEVEC_TEST(facge_h_00_01_02, "facge h0, h1, h2", 0, 1, 2)
|
||||
@ -2660,6 +2852,70 @@ GEN_THREEVEC_TEST(facge_h_27_28_29, "facge h27, h28, h29", 27, 28, 29)
|
||||
GEN_THREEVEC_TEST(facge_h_28_29_30, "facge h28, h29, h30", 28, 29, 30)
|
||||
GEN_THREEVEC_TEST(facge_h_29_30_31, "facge h29, h30, h31", 29, 30, 31)
|
||||
|
||||
// FACGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
|
||||
|
||||
GEN_THREEVEC_TEST(facge_8h_00_01_02, "facge v0.8h, v1.8h, v2.8h", 0, 1, 2)
|
||||
GEN_THREEVEC_TEST(facge_8h_01_02_03, "facge v1.8h, v2.8h, v3.8h", 1, 2, 3)
|
||||
GEN_THREEVEC_TEST(facge_8h_02_03_04, "facge v2.8h, v3.8h, v4.8h", 2, 3, 4)
|
||||
GEN_THREEVEC_TEST(facge_8h_03_04_05, "facge v3.8h, v4.8h, v5.8h", 3, 4, 5)
|
||||
GEN_THREEVEC_TEST(facge_8h_04_05_06, "facge v4.8h, v5.8h, v6.8h", 4, 5, 6)
|
||||
GEN_THREEVEC_TEST(facge_8h_05_06_07, "facge v5.8h, v6.8h, v7.8h", 5, 6, 7)
|
||||
GEN_THREEVEC_TEST(facge_8h_06_07_08, "facge v6.8h, v7.8h, v8.8h", 6, 7, 8)
|
||||
GEN_THREEVEC_TEST(facge_8h_07_08_09, "facge v7.8h, v8.8h, v9.8h", 7, 8, 9)
|
||||
GEN_THREEVEC_TEST(facge_8h_08_09_10, "facge v8.8h, v9.8h, v10.8h", 8, 9, 10)
|
||||
GEN_THREEVEC_TEST(facge_8h_09_10_11, "facge v9.8h, v10.8h, v11.8h", 9, 10, 11)
|
||||
GEN_THREEVEC_TEST(facge_8h_10_11_12, "facge v10.8h, v11.8h, v12.8h", 10, 11, 12)
|
||||
GEN_THREEVEC_TEST(facge_8h_11_12_13, "facge v11.8h, v12.8h, v13.8h", 11, 12, 13)
|
||||
GEN_THREEVEC_TEST(facge_8h_12_13_14, "facge v12.8h, v13.8h, v14.8h", 12, 13, 14)
|
||||
GEN_THREEVEC_TEST(facge_8h_13_14_15, "facge v13.8h, v14.8h, v15.8h", 13, 14, 15)
|
||||
GEN_THREEVEC_TEST(facge_8h_14_15_16, "facge v14.8h, v15.8h, v16.8h", 14, 15, 16)
|
||||
GEN_THREEVEC_TEST(facge_8h_15_16_17, "facge v15.8h, v16.8h, v17.8h", 15, 16, 17)
|
||||
GEN_THREEVEC_TEST(facge_8h_16_17_18, "facge v16.8h, v17.8h, v18.8h", 16, 17, 18)
|
||||
GEN_THREEVEC_TEST(facge_8h_17_18_19, "facge v17.8h, v18.8h, v19.8h", 17, 18, 19)
|
||||
GEN_THREEVEC_TEST(facge_8h_18_19_20, "facge v18.8h, v19.8h, v20.8h", 18, 19, 20)
|
||||
GEN_THREEVEC_TEST(facge_8h_19_20_21, "facge v19.8h, v20.8h, v21.8h", 19, 20, 21)
|
||||
GEN_THREEVEC_TEST(facge_8h_20_21_22, "facge v20.8h, v21.8h, v22.8h", 20, 21, 22)
|
||||
GEN_THREEVEC_TEST(facge_8h_21_22_23, "facge v21.8h, v22.8h, v23.8h", 21, 22, 23)
|
||||
GEN_THREEVEC_TEST(facge_8h_22_23_24, "facge v22.8h, v23.8h, v24.8h", 22, 23, 24)
|
||||
GEN_THREEVEC_TEST(facge_8h_23_24_25, "facge v23.8h, v24.8h, v25.8h", 23, 24, 25)
|
||||
GEN_THREEVEC_TEST(facge_8h_24_25_26, "facge v24.8h, v25.8h, v26.8h", 24, 25, 26)
|
||||
GEN_THREEVEC_TEST(facge_8h_25_26_27, "facge v25.8h, v26.8h, v27.8h", 25, 26, 27)
|
||||
GEN_THREEVEC_TEST(facge_8h_26_27_28, "facge v26.8h, v27.8h, v28.8h", 26, 27, 28)
|
||||
GEN_THREEVEC_TEST(facge_8h_27_28_29, "facge v27.8h, v28.8h, v29.8h", 27, 28, 29)
|
||||
GEN_THREEVEC_TEST(facge_8h_28_29_30, "facge v28.8h, v29.8h, v30.8h", 28, 29, 30)
|
||||
GEN_THREEVEC_TEST(facge_8h_29_30_31, "facge v29.8h, v30.8h, v31.8h", 29, 30, 31)
|
||||
|
||||
GEN_THREEVEC_TEST(facge_4h_00_01_02, "facge v0.4h, v1.4h, v2.4h", 0, 1, 2)
|
||||
GEN_THREEVEC_TEST(facge_4h_01_02_03, "facge v1.4h, v2.4h, v3.4h", 1, 2, 3)
|
||||
GEN_THREEVEC_TEST(facge_4h_02_03_04, "facge v2.4h, v3.4h, v4.4h", 2, 3, 4)
|
||||
GEN_THREEVEC_TEST(facge_4h_03_04_05, "facge v3.4h, v4.4h, v5.4h", 3, 4, 5)
|
||||
GEN_THREEVEC_TEST(facge_4h_04_05_06, "facge v4.4h, v5.4h, v6.4h", 4, 5, 6)
|
||||
GEN_THREEVEC_TEST(facge_4h_05_06_07, "facge v5.4h, v6.4h, v7.4h", 5, 6, 7)
|
||||
GEN_THREEVEC_TEST(facge_4h_06_07_08, "facge v6.4h, v7.4h, v8.4h", 6, 7, 8)
|
||||
GEN_THREEVEC_TEST(facge_4h_07_08_09, "facge v7.4h, v8.4h, v9.4h", 7, 8, 9)
|
||||
GEN_THREEVEC_TEST(facge_4h_08_09_10, "facge v8.4h, v9.4h, v10.4h", 8, 9, 10)
|
||||
GEN_THREEVEC_TEST(facge_4h_09_10_11, "facge v9.4h, v10.4h, v11.4h", 9, 10, 11)
|
||||
GEN_THREEVEC_TEST(facge_4h_10_11_12, "facge v10.4h, v11.4h, v12.4h", 10, 11, 12)
|
||||
GEN_THREEVEC_TEST(facge_4h_11_12_13, "facge v11.4h, v12.4h, v13.4h", 11, 12, 13)
|
||||
GEN_THREEVEC_TEST(facge_4h_12_13_14, "facge v12.4h, v13.4h, v14.4h", 12, 13, 14)
|
||||
GEN_THREEVEC_TEST(facge_4h_13_14_15, "facge v13.4h, v14.4h, v15.4h", 13, 14, 15)
|
||||
GEN_THREEVEC_TEST(facge_4h_14_15_16, "facge v14.4h, v15.4h, v16.4h", 14, 15, 16)
|
||||
GEN_THREEVEC_TEST(facge_4h_15_16_17, "facge v15.4h, v16.4h, v17.4h", 15, 16, 17)
|
||||
GEN_THREEVEC_TEST(facge_4h_16_17_18, "facge v16.4h, v17.4h, v18.4h", 16, 17, 18)
|
||||
GEN_THREEVEC_TEST(facge_4h_17_18_19, "facge v17.4h, v18.4h, v19.4h", 17, 18, 19)
|
||||
GEN_THREEVEC_TEST(facge_4h_18_19_20, "facge v18.4h, v19.4h, v20.4h", 18, 19, 20)
|
||||
GEN_THREEVEC_TEST(facge_4h_19_20_21, "facge v19.4h, v20.4h, v21.4h", 19, 20, 21)
|
||||
GEN_THREEVEC_TEST(facge_4h_20_21_22, "facge v20.4h, v21.4h, v22.4h", 20, 21, 22)
|
||||
GEN_THREEVEC_TEST(facge_4h_21_22_23, "facge v21.4h, v22.4h, v23.4h", 21, 22, 23)
|
||||
GEN_THREEVEC_TEST(facge_4h_22_23_24, "facge v22.4h, v23.4h, v24.4h", 22, 23, 24)
|
||||
GEN_THREEVEC_TEST(facge_4h_23_24_25, "facge v23.4h, v24.4h, v25.4h", 23, 24, 25)
|
||||
GEN_THREEVEC_TEST(facge_4h_24_25_26, "facge v24.4h, v25.4h, v26.4h", 24, 25, 26)
|
||||
GEN_THREEVEC_TEST(facge_4h_25_26_27, "facge v25.4h, v26.4h, v27.4h", 25, 26, 27)
|
||||
GEN_THREEVEC_TEST(facge_4h_26_27_28, "facge v26.4h, v27.4h, v28.4h", 26, 27, 28)
|
||||
GEN_THREEVEC_TEST(facge_4h_27_28_29, "facge v27.4h, v28.4h, v29.4h", 27, 28, 29)
|
||||
GEN_THREEVEC_TEST(facge_4h_28_29_30, "facge v28.4h, v29.4h, v30.4h", 28, 29, 30)
|
||||
GEN_THREEVEC_TEST(facge_4h_29_30_31, "facge v29.4h, v30.4h, v31.4h", 29, 30, 31)
|
||||
|
||||
/* ---------------------------------------------------------------- */
|
||||
/* -- main() -- */
|
||||
/* ---------------------------------------------------------------- */
|
||||
@ -2701,6 +2957,70 @@ int main ( void )
|
||||
if (1) test_fadd_h_28_29_30(TyH);
|
||||
if (1) test_fadd_h_29_30_31(TyH);
|
||||
|
||||
printf("\nFADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>\n\n");
|
||||
|
||||
if (1) test_fadd_8h_00_01_02(TyH);
|
||||
if (1) test_fadd_8h_01_02_03(TyH);
|
||||
if (1) test_fadd_8h_02_03_04(TyH);
|
||||
if (1) test_fadd_8h_03_04_05(TyH);
|
||||
if (1) test_fadd_8h_04_05_06(TyH);
|
||||
if (1) test_fadd_8h_05_06_07(TyH);
|
||||
if (1) test_fadd_8h_06_07_08(TyH);
|
||||
if (1) test_fadd_8h_07_08_09(TyH);
|
||||
if (1) test_fadd_8h_08_09_10(TyH);
|
||||
if (1) test_fadd_8h_09_10_11(TyH);
|
||||
if (1) test_fadd_8h_10_11_12(TyH);
|
||||
if (1) test_fadd_8h_11_12_13(TyH);
|
||||
if (1) test_fadd_8h_12_13_14(TyH);
|
||||
if (1) test_fadd_8h_13_14_15(TyH);
|
||||
if (1) test_fadd_8h_14_15_16(TyH);
|
||||
if (1) test_fadd_8h_15_16_17(TyH);
|
||||
if (1) test_fadd_8h_16_17_18(TyH);
|
||||
if (1) test_fadd_8h_17_18_19(TyH);
|
||||
if (1) test_fadd_8h_18_19_20(TyH);
|
||||
if (1) test_fadd_8h_19_20_21(TyH);
|
||||
if (1) test_fadd_8h_20_21_22(TyH);
|
||||
if (1) test_fadd_8h_21_22_23(TyH);
|
||||
if (1) test_fadd_8h_22_23_24(TyH);
|
||||
if (1) test_fadd_8h_23_24_25(TyH);
|
||||
if (1) test_fadd_8h_24_25_26(TyH);
|
||||
if (1) test_fadd_8h_25_26_27(TyH);
|
||||
if (1) test_fadd_8h_26_27_28(TyH);
|
||||
if (1) test_fadd_8h_27_28_29(TyH);
|
||||
if (1) test_fadd_8h_28_29_30(TyH);
|
||||
if (1) test_fadd_8h_29_30_31(TyH);
|
||||
|
||||
if (1) test_fadd_4h_00_01_02(TyH);
|
||||
if (1) test_fadd_4h_01_02_03(TyH);
|
||||
if (1) test_fadd_4h_02_03_04(TyH);
|
||||
if (1) test_fadd_4h_03_04_05(TyH);
|
||||
if (1) test_fadd_4h_04_05_06(TyH);
|
||||
if (1) test_fadd_4h_05_06_07(TyH);
|
||||
if (1) test_fadd_4h_06_07_08(TyH);
|
||||
if (1) test_fadd_4h_07_08_09(TyH);
|
||||
if (1) test_fadd_4h_08_09_10(TyH);
|
||||
if (1) test_fadd_4h_09_10_11(TyH);
|
||||
if (1) test_fadd_4h_10_11_12(TyH);
|
||||
if (1) test_fadd_4h_11_12_13(TyH);
|
||||
if (1) test_fadd_4h_12_13_14(TyH);
|
||||
if (1) test_fadd_4h_13_14_15(TyH);
|
||||
if (1) test_fadd_4h_14_15_16(TyH);
|
||||
if (1) test_fadd_4h_15_16_17(TyH);
|
||||
if (1) test_fadd_4h_16_17_18(TyH);
|
||||
if (1) test_fadd_4h_17_18_19(TyH);
|
||||
if (1) test_fadd_4h_18_19_20(TyH);
|
||||
if (1) test_fadd_4h_19_20_21(TyH);
|
||||
if (1) test_fadd_4h_20_21_22(TyH);
|
||||
if (1) test_fadd_4h_21_22_23(TyH);
|
||||
if (1) test_fadd_4h_22_23_24(TyH);
|
||||
if (1) test_fadd_4h_23_24_25(TyH);
|
||||
if (1) test_fadd_4h_24_25_26(TyH);
|
||||
if (1) test_fadd_4h_25_26_27(TyH);
|
||||
if (1) test_fadd_4h_26_27_28(TyH);
|
||||
if (1) test_fadd_4h_27_28_29(TyH);
|
||||
if (1) test_fadd_4h_28_29_30(TyH);
|
||||
if (1) test_fadd_4h_29_30_31(TyH);
|
||||
|
||||
printf("\nFADDP <V><d>, <Vn>.<T>\n\n");
|
||||
|
||||
if (1) test_faddp_h_2h_00_01(TyH);
|
||||
@ -3132,6 +3452,70 @@ int main ( void )
|
||||
if (1) test_fabd_h_28_29_30(TyH);
|
||||
if (1) test_fabd_h_29_30_31(TyH);
|
||||
|
||||
printf("\nFABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>\n\n");
|
||||
|
||||
if (1) test_fabd_8h_00_01_02(TyH);
|
||||
if (1) test_fabd_8h_01_02_03(TyH);
|
||||
if (1) test_fabd_8h_02_03_04(TyH);
|
||||
if (1) test_fabd_8h_03_04_05(TyH);
|
||||
if (1) test_fabd_8h_04_05_06(TyH);
|
||||
if (1) test_fabd_8h_05_06_07(TyH);
|
||||
if (1) test_fabd_8h_06_07_08(TyH);
|
||||
if (1) test_fabd_8h_07_08_09(TyH);
|
||||
if (1) test_fabd_8h_08_09_10(TyH);
|
||||
if (1) test_fabd_8h_09_10_11(TyH);
|
||||
if (1) test_fabd_8h_10_11_12(TyH);
|
||||
if (1) test_fabd_8h_11_12_13(TyH);
|
||||
if (1) test_fabd_8h_12_13_14(TyH);
|
||||
if (1) test_fabd_8h_13_14_15(TyH);
|
||||
if (1) test_fabd_8h_14_15_16(TyH);
|
||||
if (1) test_fabd_8h_15_16_17(TyH);
|
||||
if (1) test_fabd_8h_16_17_18(TyH);
|
||||
if (1) test_fabd_8h_17_18_19(TyH);
|
||||
if (1) test_fabd_8h_18_19_20(TyH);
|
||||
if (1) test_fabd_8h_19_20_21(TyH);
|
||||
if (1) test_fabd_8h_20_21_22(TyH);
|
||||
if (1) test_fabd_8h_21_22_23(TyH);
|
||||
if (1) test_fabd_8h_22_23_24(TyH);
|
||||
if (1) test_fabd_8h_23_24_25(TyH);
|
||||
if (1) test_fabd_8h_24_25_26(TyH);
|
||||
if (1) test_fabd_8h_25_26_27(TyH);
|
||||
if (1) test_fabd_8h_26_27_28(TyH);
|
||||
if (1) test_fabd_8h_27_28_29(TyH);
|
||||
if (1) test_fabd_8h_28_29_30(TyH);
|
||||
if (1) test_fabd_8h_29_30_31(TyH);
|
||||
|
||||
if (1) test_fabd_4h_00_01_02(TyH);
|
||||
if (1) test_fabd_4h_01_02_03(TyH);
|
||||
if (1) test_fabd_4h_02_03_04(TyH);
|
||||
if (1) test_fabd_4h_03_04_05(TyH);
|
||||
if (1) test_fabd_4h_04_05_06(TyH);
|
||||
if (1) test_fabd_4h_05_06_07(TyH);
|
||||
if (1) test_fabd_4h_06_07_08(TyH);
|
||||
if (1) test_fabd_4h_07_08_09(TyH);
|
||||
if (1) test_fabd_4h_08_09_10(TyH);
|
||||
if (1) test_fabd_4h_09_10_11(TyH);
|
||||
if (1) test_fabd_4h_10_11_12(TyH);
|
||||
if (1) test_fabd_4h_11_12_13(TyH);
|
||||
if (1) test_fabd_4h_12_13_14(TyH);
|
||||
if (1) test_fabd_4h_13_14_15(TyH);
|
||||
if (1) test_fabd_4h_14_15_16(TyH);
|
||||
if (1) test_fabd_4h_15_16_17(TyH);
|
||||
if (1) test_fabd_4h_16_17_18(TyH);
|
||||
if (1) test_fabd_4h_17_18_19(TyH);
|
||||
if (1) test_fabd_4h_18_19_20(TyH);
|
||||
if (1) test_fabd_4h_19_20_21(TyH);
|
||||
if (1) test_fabd_4h_20_21_22(TyH);
|
||||
if (1) test_fabd_4h_21_22_23(TyH);
|
||||
if (1) test_fabd_4h_22_23_24(TyH);
|
||||
if (1) test_fabd_4h_23_24_25(TyH);
|
||||
if (1) test_fabd_4h_24_25_26(TyH);
|
||||
if (1) test_fabd_4h_25_26_27(TyH);
|
||||
if (1) test_fabd_4h_26_27_28(TyH);
|
||||
if (1) test_fabd_4h_27_28_29(TyH);
|
||||
if (1) test_fabd_4h_28_29_30(TyH);
|
||||
if (1) test_fabd_4h_29_30_31(TyH);
|
||||
|
||||
printf("\nFACGT <Hd>, <Hn>, <Hm>\n\n");
|
||||
|
||||
if (1) test_facgt_h_00_01_02(TyH);
|
||||
@ -3165,6 +3549,70 @@ int main ( void )
|
||||
if (1) test_facgt_h_28_29_30(TyH);
|
||||
if (1) test_facgt_h_29_30_31(TyH);
|
||||
|
||||
printf("\nFACGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T>\n\n");
|
||||
|
||||
if (1) test_facgt_8h_00_01_02(TyH);
|
||||
if (1) test_facgt_8h_01_02_03(TyH);
|
||||
if (1) test_facgt_8h_02_03_04(TyH);
|
||||
if (1) test_facgt_8h_03_04_05(TyH);
|
||||
if (1) test_facgt_8h_04_05_06(TyH);
|
||||
if (1) test_facgt_8h_05_06_07(TyH);
|
||||
if (1) test_facgt_8h_06_07_08(TyH);
|
||||
if (1) test_facgt_8h_07_08_09(TyH);
|
||||
if (1) test_facgt_8h_08_09_10(TyH);
|
||||
if (1) test_facgt_8h_09_10_11(TyH);
|
||||
if (1) test_facgt_8h_10_11_12(TyH);
|
||||
if (1) test_facgt_8h_11_12_13(TyH);
|
||||
if (1) test_facgt_8h_12_13_14(TyH);
|
||||
if (1) test_facgt_8h_13_14_15(TyH);
|
||||
if (1) test_facgt_8h_14_15_16(TyH);
|
||||
if (1) test_facgt_8h_15_16_17(TyH);
|
||||
if (1) test_facgt_8h_16_17_18(TyH);
|
||||
if (1) test_facgt_8h_17_18_19(TyH);
|
||||
if (1) test_facgt_8h_18_19_20(TyH);
|
||||
if (1) test_facgt_8h_19_20_21(TyH);
|
||||
if (1) test_facgt_8h_20_21_22(TyH);
|
||||
if (1) test_facgt_8h_21_22_23(TyH);
|
||||
if (1) test_facgt_8h_22_23_24(TyH);
|
||||
if (1) test_facgt_8h_23_24_25(TyH);
|
||||
if (1) test_facgt_8h_24_25_26(TyH);
|
||||
if (1) test_facgt_8h_25_26_27(TyH);
|
||||
if (1) test_facgt_8h_26_27_28(TyH);
|
||||
if (1) test_facgt_8h_27_28_29(TyH);
|
||||
if (1) test_facgt_8h_28_29_30(TyH);
|
||||
if (1) test_facgt_8h_29_30_31(TyH);
|
||||
|
||||
if (1) test_facgt_4h_00_01_02(TyH);
|
||||
if (1) test_facgt_4h_01_02_03(TyH);
|
||||
if (1) test_facgt_4h_02_03_04(TyH);
|
||||
if (1) test_facgt_4h_03_04_05(TyH);
|
||||
if (1) test_facgt_4h_04_05_06(TyH);
|
||||
if (1) test_facgt_4h_05_06_07(TyH);
|
||||
if (1) test_facgt_4h_06_07_08(TyH);
|
||||
if (1) test_facgt_4h_07_08_09(TyH);
|
||||
if (1) test_facgt_4h_08_09_10(TyH);
|
||||
if (1) test_facgt_4h_09_10_11(TyH);
|
||||
if (1) test_facgt_4h_10_11_12(TyH);
|
||||
if (1) test_facgt_4h_11_12_13(TyH);
|
||||
if (1) test_facgt_4h_12_13_14(TyH);
|
||||
if (1) test_facgt_4h_13_14_15(TyH);
|
||||
if (1) test_facgt_4h_14_15_16(TyH);
|
||||
if (1) test_facgt_4h_15_16_17(TyH);
|
||||
if (1) test_facgt_4h_16_17_18(TyH);
|
||||
if (1) test_facgt_4h_17_18_19(TyH);
|
||||
if (1) test_facgt_4h_18_19_20(TyH);
|
||||
if (1) test_facgt_4h_19_20_21(TyH);
|
||||
if (1) test_facgt_4h_20_21_22(TyH);
|
||||
if (1) test_facgt_4h_21_22_23(TyH);
|
||||
if (1) test_facgt_4h_22_23_24(TyH);
|
||||
if (1) test_facgt_4h_23_24_25(TyH);
|
||||
if (1) test_facgt_4h_24_25_26(TyH);
|
||||
if (1) test_facgt_4h_25_26_27(TyH);
|
||||
if (1) test_facgt_4h_26_27_28(TyH);
|
||||
if (1) test_facgt_4h_27_28_29(TyH);
|
||||
if (1) test_facgt_4h_28_29_30(TyH);
|
||||
if (1) test_facgt_4h_29_30_31(TyH);
|
||||
|
||||
printf("\nFACGE <Hd>, <Hn>, <Hm>\n\n");
|
||||
|
||||
if (1) test_facge_h_00_01_02(TyH);
|
||||
@ -3198,6 +3646,70 @@ int main ( void )
|
||||
if (1) test_facge_h_28_29_30(TyH);
|
||||
if (1) test_facge_h_29_30_31(TyH);
|
||||
|
||||
printf("\nFACGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T>\n\n");
|
||||
|
||||
if (1) test_facge_8h_00_01_02(TyH);
|
||||
if (1) test_facge_8h_01_02_03(TyH);
|
||||
if (1) test_facge_8h_02_03_04(TyH);
|
||||
if (1) test_facge_8h_03_04_05(TyH);
|
||||
if (1) test_facge_8h_04_05_06(TyH);
|
||||
if (1) test_facge_8h_05_06_07(TyH);
|
||||
if (1) test_facge_8h_06_07_08(TyH);
|
||||
if (1) test_facge_8h_07_08_09(TyH);
|
||||
if (1) test_facge_8h_08_09_10(TyH);
|
||||
if (1) test_facge_8h_09_10_11(TyH);
|
||||
if (1) test_facge_8h_10_11_12(TyH);
|
||||
if (1) test_facge_8h_11_12_13(TyH);
|
||||
if (1) test_facge_8h_12_13_14(TyH);
|
||||
if (1) test_facge_8h_13_14_15(TyH);
|
||||
if (1) test_facge_8h_14_15_16(TyH);
|
||||
if (1) test_facge_8h_15_16_17(TyH);
|
||||
if (1) test_facge_8h_16_17_18(TyH);
|
||||
if (1) test_facge_8h_17_18_19(TyH);
|
||||
if (1) test_facge_8h_18_19_20(TyH);
|
||||
if (1) test_facge_8h_19_20_21(TyH);
|
||||
if (1) test_facge_8h_20_21_22(TyH);
|
||||
if (1) test_facge_8h_21_22_23(TyH);
|
||||
if (1) test_facge_8h_22_23_24(TyH);
|
||||
if (1) test_facge_8h_23_24_25(TyH);
|
||||
if (1) test_facge_8h_24_25_26(TyH);
|
||||
if (1) test_facge_8h_25_26_27(TyH);
|
||||
if (1) test_facge_8h_26_27_28(TyH);
|
||||
if (1) test_facge_8h_27_28_29(TyH);
|
||||
if (1) test_facge_8h_28_29_30(TyH);
|
||||
if (1) test_facge_8h_29_30_31(TyH);
|
||||
|
||||
if (1) test_facge_4h_00_01_02(TyH);
|
||||
if (1) test_facge_4h_01_02_03(TyH);
|
||||
if (1) test_facge_4h_02_03_04(TyH);
|
||||
if (1) test_facge_4h_03_04_05(TyH);
|
||||
if (1) test_facge_4h_04_05_06(TyH);
|
||||
if (1) test_facge_4h_05_06_07(TyH);
|
||||
if (1) test_facge_4h_06_07_08(TyH);
|
||||
if (1) test_facge_4h_07_08_09(TyH);
|
||||
if (1) test_facge_4h_08_09_10(TyH);
|
||||
if (1) test_facge_4h_09_10_11(TyH);
|
||||
if (1) test_facge_4h_10_11_12(TyH);
|
||||
if (1) test_facge_4h_11_12_13(TyH);
|
||||
if (1) test_facge_4h_12_13_14(TyH);
|
||||
if (1) test_facge_4h_13_14_15(TyH);
|
||||
if (1) test_facge_4h_14_15_16(TyH);
|
||||
if (1) test_facge_4h_15_16_17(TyH);
|
||||
if (1) test_facge_4h_16_17_18(TyH);
|
||||
if (1) test_facge_4h_17_18_19(TyH);
|
||||
if (1) test_facge_4h_18_19_20(TyH);
|
||||
if (1) test_facge_4h_19_20_21(TyH);
|
||||
if (1) test_facge_4h_20_21_22(TyH);
|
||||
if (1) test_facge_4h_21_22_23(TyH);
|
||||
if (1) test_facge_4h_22_23_24(TyH);
|
||||
if (1) test_facge_4h_23_24_25(TyH);
|
||||
if (1) test_facge_4h_24_25_26(TyH);
|
||||
if (1) test_facge_4h_25_26_27(TyH);
|
||||
if (1) test_facge_4h_26_27_28(TyH);
|
||||
if (1) test_facge_4h_27_28_29(TyH);
|
||||
if (1) test_facge_4h_28_29_30(TyH);
|
||||
if (1) test_facge_4h_29_30_31(TyH);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -3207,6 +3719,7 @@ int main ( void )
|
||||
/* ---------------------------------------------------------------- */
|
||||
/*
|
||||
FADD <Hd>, <Hn>, <Hm> Floating-point Add (scalar).
|
||||
FADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> Floating-point Add (vector).
|
||||
FADDP <V><d>, <Vn>.<T> Floating-point Add Pair of elements (scalar).
|
||||
FADDP <Vd>.<T>, <Vn>.<T>, <Vm>.<T> Floating-point Add Pairwise (vector).
|
||||
FABS <Hd>, <Hn> Floating-point Absolute value (scalar).
|
||||
@ -3216,6 +3729,9 @@ int main ( void )
|
||||
FSQRT <Hd>, <Hn> Floating-point Square Root (scalar).
|
||||
FSQRT <Vd>.<T>, <Vn>.<T> Floating-point Square Root (vector).
|
||||
FABD <Hd>, <Hn>, <Hm> Floating-point Absolute Difference (scalar).
|
||||
FABD <Vd>.<T>, <Vn>.<T>, <Vm>.<T> Floating-point Absolute Difference (vector).
|
||||
FACGT <Hd>, <Hn>, <Hm> Floating-point Absolute Compare Greater than (scalar).
|
||||
FACGT <Vd>.<T>, <Vn>.<T>, <Vm>.<T> Floating-point Absolute Compare Greater than (vector).
|
||||
FACGE <Hd>, <Hn>, <Hm> Floating-point Absolute Compare Greater than or Equal (scalar).
|
||||
FACGE <Vd>.<T>, <Vn>.<T>, <Vm>.<T> Floating-point Absolute Compare Greater than or Equal (vector).
|
||||
*/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user