zenithsiz/ftmemsim-valgrind
1
0
Fork 0
mirror of https://github.com/Zenithsiz/ftmemsim-valgrind.git synced 2026-02-14 06:48:06 +00:00
Code Issues Actions Packages Projects Releases Wiki Activity
745 Commits 1 Branch 0 Tags
01dd7600a10f44fa16fb06c6a492ad7d70ca6eb3
Commit Graph

745 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Cerion Armour-Brown
01dd7600a1 updated cpustate 
git-svn-id: svn://svn.valgrind.org/vex/trunk@745
 2005-01-25 16:56:18 +00:00
Julian Seward
5f8bd93071 Mucho baseline hacking to get amd64 front end to work. No luck so far :-) 
git-svn-id: svn://svn.valgrind.org/vex/trunk@744
 2005-01-25 15:48:43 +00:00
Julian Seward
d21677dc8a Don't do anything special with "rep nop". The former behaviour was to 
notify the scheduler that this thread wants to yield, but that gives
such huge delays as to mess up spin-wait loops using "rep nop".  New
behaviour is to simply treat it as a no-op, with no scheduling
consequences.



git-svn-id: svn://svn.valgrind.org/vex/trunk@743
 2005-01-25 15:47:39 +00:00
Cerion Armour-Brown
4af9a299b8 Initial file setup for guest-ppc 
git-svn-id: svn://svn.valgrind.org/vex/trunk@742
 2005-01-25 12:24:25 +00:00
Julian Seward
5f4281795e Test hackery for chasing across conditional branches. Experimental 
and currently disabled.


git-svn-id: svn://svn.valgrind.org/vex/trunk@741
 2005-01-24 11:54:11 +00:00
Julian Seward
8d66c3c8d9 This commit does multiple things (bad, I know): 
* Rearranged the order of functions in ghelpers.c to be cleaner and
  tidier
* Improved the %eflags-profiling machinery in ghelpers.c, so I can
  better understand the numbers it produces
* Using that, add some more eflags specialisation cases
* Make calculate_eflags_c into a regparm(3) function, since it can
  get called quite a lot.


git-svn-id: svn://svn.valgrind.org/vex/trunk@740
 2005-01-24 10:49:02 +00:00
Julian Seward
e151892d26 More tuning of the eflags machinery. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@739
 2005-01-23 11:39:02 +00:00
Julian Seward
8f63b956be Another speedup case resulting from profiled runs of bzip2. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@738
 2005-01-22 11:00:42 +00:00
Julian Seward
306665bf32 Paranoia in enum. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@737
 2005-01-22 11:00:07 +00:00
Julian Seward
a7bb1a8bce Add more gcc paranoia flags in Makefile, and fix a resulting warning. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@736
 2005-01-21 21:23:07 +00:00
Julian Seward
2790eda3b1 Fix various compilation warnings emitted by icc, mostly to do with 
dead code -- it is better at spotting it than gcc is.



git-svn-id: svn://svn.valgrind.org/vex/trunk@735
 2005-01-21 20:55:36 +00:00
Julian Seward
b29b6977ea Bring this up to date. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@734
 2005-01-21 20:54:33 +00:00
Julian Seward
e662a12518 First pass at doing amd64 address mode decoding. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@733
 2005-01-21 20:33:44 +00:00
Julian Seward
5f57b15774 Lots of grunge for dealing with amd64 integer registers. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@732
 2005-01-21 14:26:37 +00:00
Julian Seward
987261b200 Add stub definitions for amd64 front end functions. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@731
 2005-01-20 20:26:33 +00:00
Julian Seward
d20600ce98 Add a dummy AMD64 front end, as a completely commented-out version of 
the x86 equivalents.



git-svn-id: svn://svn.valgrind.org/vex/trunk@730
 2005-01-20 20:04:07 +00:00
Julian Seward
8b772f9c19 Fix comment. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@729
 2005-01-20 19:43:56 +00:00
Julian Seward
94d5d6cb5e Program for making bootstrap .orig files from 'as -a' output. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@728
 2005-01-20 17:57:55 +00:00
Julian Seward
d8e90ee930 Put a ret (0xC3) after each insn, to keep the decoder happy. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@727
 2005-01-20 17:56:39 +00:00
Julian Seward
f6107946a6 A bunch of insns to get the amd64 front end hackery started. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@726
 2005-01-20 17:29:03 +00:00
Julian Seward
c16f8fccae New directory, for messing with the amd64 front end. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@725
 2005-01-20 17:19:38 +00:00
Julian Seward
42015c066d Basic Block Profiler Roolz OK ! 
git-svn-id: svn://svn.valgrind.org/vex/trunk@724
 2005-01-20 12:00:51 +00:00
Julian Seward
ca81a4f6bb Fix performance hole exposed by profiling gzip. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@723
 2005-01-20 10:48:20 +00:00
Julian Seward
9992623c4d Reinstate "cmps" (without rep). gzip seems to require it. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@722
 2005-01-20 10:47:46 +00:00
Julian Seward
a97d45c929 First fruits from using new bb profiler: improve handling of guest x86 
floating point comparisons.  A lot.  There is more to be done here.



git-svn-id: svn://svn.valgrind.org/vex/trunk@721
 2005-01-20 10:04:05 +00:00
Julian Seward
ab71110bd4 Proper support for translation cache management: when a translation is 
made, record precisely the areas of guest address space from which the
translation was made.  This is needed to be sure we can later discard
translations accurately.  The new info is record in a structure called
VexGuestExtents.



git-svn-id: svn://svn.valgrind.org/vex/trunk@720
 2005-01-19 11:49:45 +00:00
Cerion Armour-Brown
2d49eb1690 fixed shift_immed & branch 
git-svn-id: svn://svn.valgrind.org/vex/trunk@719
 2005-01-18 14:55:12 +00:00
Julian Seward
1073520b66 Rename some functions and types in the top level interface to be more 
consistent.  Also make private some functions that Valgrind never
used.



git-svn-id: svn://svn.valgrind.org/vex/trunk@718
 2005-01-17 18:34:34 +00:00
Julian Seward
00de92635d Also test 64-bit add/sub insns (paddq/psubq), although these only 
appeared in sse2.


git-svn-id: svn://svn.valgrind.org/vex/trunk@717
 2005-01-15 23:35:03 +00:00
Julian Seward
2fcaf5ee4c Instruction selection/emission for Add64 and Sub64. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@716
 2005-01-15 20:43:10 +00:00
Julian Seward
715ca1b759 Add new IR primops: Iop_CmpNEZ8x8, Iop_CmpNEZ16x4, Iop_CmpNEZ32x2 and 
isel support for them in the x86 back end.  They are used for Memcheck
annotation of 64-bit SIMD code.



git-svn-id: svn://svn.valgrind.org/vex/trunk@715
 2005-01-13 19:16:04 +00:00
Julian Seward
0d4ff22359 Fix typos in comment. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@714
 2005-01-13 16:36:42 +00:00
Julian Seward
5ca186679b Comment-only change: record code generation conventions and 
limitations for x86.




git-svn-id: svn://svn.valgrind.org/vex/trunk@713
 2005-01-13 16:33:19 +00:00
Julian Seward
5f05f2a682 On x86 host and guest, re-implement the way MMX instructions are done, 
to bring them into line with how SSE works.  Previously, MMX was done
using helper functions calls inserted by the front end.  This meant
proper MMX instrumentation was impossible (unlike SSE).  Now it works
the way all other code does: the front end does not insert calls to
helper functions, but rather builds expression trees using 64-bit
vector primops.  These are instrumented as the 128-bit vector primops
already are, and passed to the back ends.

Because emitting combined x87 and MMX code together is too complex,
the x86 back end generates calls to the same helpers as before --
except they are invisible to the front end.  And, of course, some of
those calls may now be running instrumentation operations rather than
real-value operations.



git-svn-id: svn://svn.valgrind.org/vex/trunk@712
 2005-01-13 15:06:51 +00:00
Julian Seward
866f896155 Add some starting-off material for PPC32. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@711
 2005-01-12 11:25:02 +00:00
Julian Seward
8f57657569 Rename ... 
git-svn-id: svn://svn.valgrind.org/vex/trunk@710
 2005-01-12 11:12:49 +00:00
Julian Seward
cfed7ec9dd For holding 32-bit PPC originals. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@709
 2005-01-12 11:12:28 +00:00
Julian Seward
b00a46b995 This is no longer useful. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@708
 2005-01-12 11:10:40 +00:00
Julian Seward
47ecc83df5 Handle another PSLLDQ sub-case. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@707
 2005-01-11 15:03:53 +00:00
Julian Seward
6fef2ca38f Partial implementation of pslldq (SSE2). 
git-svn-id: svn://svn.valgrind.org/vex/trunk@706
 2005-01-10 20:37:31 +00:00
Julian Seward
3feb4705a7 x86 floating point accuracy improvements. The aim is to make x86 FP 
behave more consistently like an 64-bit implementation.  Mostly this
means running the host with the FPU set to 64-bit precision, not
80-bit.

Requires corresponding changes on the Valgrind side of the fence.




git-svn-id: svn://svn.valgrind.org/vex/trunk@705
 2005-01-10 16:49:19 +00:00
Julian Seward
1979c4a512 Program to check values of x87 constants. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@704
 2005-01-10 13:34:46 +00:00
Julian Seward
f9c3baa22f Program for investigating FP rounding error effects. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@703
 2005-01-08 18:26:47 +00:00
Julian Seward
dd57f1a169 Observe the memory fencing properties of CPUID. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@702
 2005-01-08 18:25:05 +00:00
Julian Seward
7064bcf7cf Fix printing of various instructions when disassembling. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@701
 2005-01-08 18:17:32 +00:00
Julian Seward
eae818a4d4 Fix some minor things to do with memory fences and the Elan3 drivers. 
Also recognise "lock addl $0,0(%esp)" as a memory fence.



git-svn-id: svn://svn.valgrind.org/vex/trunk@700
 2005-01-07 14:14:50 +00:00
Julian Seward
0c82ae8732 SSE2 fixes for mfence-ing. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@699
 2005-01-07 13:36:14 +00:00
Julian Seward
603ac0176b Machinery for investigation of LOCK prefixes. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@698
 2005-01-07 13:25:28 +00:00
Julian Seward
4ea7cb7702 Add a trivial new IR construction: a memory fence statement. Connect 
up to x86 front and back ends.



git-svn-id: svn://svn.valgrind.org/vex/trunk@697
 2005-01-07 12:09:15 +00:00
Julian Seward
bac1d406d1 Make it a more effective test. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@696
 2005-01-06 15:46:22 +00:00