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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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4456279023
Update the list of architectures to differentiate between the n32 and n64 abi for mips64 when defining the fast cache macros in coregrind/pub_core_transtab_asm.h. Also amend the VG_(disp_cp_xindir) function in coregrind/m_dispatch/dispatch-mips64-linux.S to use word-sized loads in case of the n32 abi since the FastCacheSet structure members are now 4 bytes in size for mips64 n32. Patch by Stefan Maksimovic.
123 lines
4.9 KiB
C
123 lines
4.9 KiB
C
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/*--------------------------------------------------------------------*/
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/*--- Asm-only TransTab stuff. pub_core_transtab_asm.h ---*/
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/*--------------------------------------------------------------------*/
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/*
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This file is part of Valgrind, a dynamic binary instrumentation
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framework.
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Copyright (C) 2000-2017 Julian Seward
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jseward@acm.org
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, see <http://www.gnu.org/licenses/>.
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The GNU General Public License is contained in the file COPYING.
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*/
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#ifndef __PUB_CORE_TRANSTAB_ASM_H
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#define __PUB_CORE_TRANSTAB_ASM_H
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/* Constants for the fast translation lookup cache. It is a 4 way associative
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cache, with more-or-less LRU replacement. It contains 2^VG_TT_FAST_BITS
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sets.
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On all targets, the set number is computed from least significant 2 *
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VG_TT_FAST_BITS of the guest address. This is a bit unusual in as much as
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it is more normal just to use a VG_TT_FAST_BITS-sized slice of the address
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as the set number. Using twice as many bits (the two chunks are xor'd)
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spreads entries out (reduces aliasing) and significantly reduces the overall
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miss rate. The cost is two extra cycles on the fast lookup path, to perform
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an extra shift and an xor.
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For each set there are 4 ways: way0, way1, way2 and way3. way0 is intended
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to be the MRU and way3 the LRU. Most lookups hit way0 and involve no
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modification of the line. A hit at way1 causes way0 and way1 to be swapped.
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A hit at way2 causes way1 and way2 to be swapped; that is, way2 is moved one
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step closer to the front. But not all the way to the front. Similarly a
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hit at way3 causes way2 and way3 to be swapped.
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See VG_(lookupInFastCache) for a C implementation of this logic and
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dispatch-*-*.S, label VG_(disp_cp_xindir), for the handcoded assembly
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equivalents for each target. Note that VG_(lookupInFastCache) is used in C
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land for some administrative lookups but isn't really performance critical.
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The dispatch-*-*.S implementations are used to process all indirect branches
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in the simulator and so *are* performance critical.
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Updates to the cache are rare. These are performed by setFastCacheEntry.
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New entries are put into way0 and all others are shifted down one slot, so
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that the contents of way3 falls out of the cache.
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On x86/amd64, the cache index is computed as
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(address ^ (address >>u VG_TT_FAST_BITS))[VG_TT_FAST_BITS-1 : 0]'.
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On ppc32/ppc64/mips32/mips64/arm64, the bottom two bits of instruction
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addresses are zero, which means the above function causes only 1/4 of the
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sets to ever be used. So instead the function is
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(address ^ (address >>u VG_TT_FAST_BITS))[VG_TT_FAST_BITS-1+2 : 0+2]'.
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On arm32, the minimum instruction size is 2, so we discard only the least
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significant bit of the address, hence:
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(address ^ (address >>u VG_TT_FAST_BITS))[VG_TT_FAST_BITS-1+1 : 0+1]'.
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On s390x the rightmost bit of an instruction address is zero, so the arm32
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scheme is used. */
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#define VG_TT_FAST_BITS 13
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#define VG_TT_FAST_SETS (1 << VG_TT_FAST_BITS)
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#define VG_TT_FAST_MASK ((VG_TT_FAST_SETS) - 1)
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// Log2(sizeof(FastCacheSet)). This is needed in the handwritten assembly.
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#if defined(VGA_amd64) || defined(VGA_arm64) \
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|| defined(VGA_ppc64be) || defined(VGA_ppc64le) \
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|| (defined(VGA_mips64) && defined(VGABI_64)) \
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|| defined(VGA_s390x)
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// And all other 64-bit hosts
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# define VG_FAST_CACHE_SET_BITS 6
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// These FCS_{g,h}{0,1,2,3} are the values of
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// offsetof(FastCacheSet,{guest,host}{0,1,2,3}).
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# define FCS_g0 0
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# define FCS_h0 8
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# define FCS_g1 16
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# define FCS_h1 24
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# define FCS_g2 32
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# define FCS_h2 40
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# define FCS_g3 48
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# define FCS_h3 56
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#elif defined(VGA_x86) || defined(VGA_arm) || defined(VGA_ppc32) \
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|| defined(VGA_mips32) || defined(VGP_nanomips_linux) \
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|| (defined(VGA_mips64) && defined(VGABI_N32))
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// And all other 32-bit hosts
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# define VG_FAST_CACHE_SET_BITS 5
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# define FCS_g0 0
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# define FCS_h0 4
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# define FCS_g1 8
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# define FCS_h1 12
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# define FCS_g2 16
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# define FCS_h2 20
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# define FCS_g3 24
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# define FCS_h3 28
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#else
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# error "VG_FAST_CACHE_SET_BITS not known"
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#endif
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#endif // __PUB_CORE_TRANSTAB_ASM_H
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/*--------------------------------------------------------------------*/
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/*--- end ---*/
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/*--------------------------------------------------------------------*/
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