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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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5cc18c19a2
computation) into the generic core, because it's needed by the dispatch loop of all archs. Also renamed it VG_(instr_ptr_offset), which is clearer. Since it was the last use of the VGOFF_ prefix, I removed that prefix. Also cleaned up the ARM stubs slightly, by removing some of the copied, commented-out x86 code which has since fallen out of date with the real x86 code and was thus misleading. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@3123
250 lines
8.3 KiB
C
250 lines
8.3 KiB
C
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/*--------------------------------------------------------------------*/
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/*--- x86 registers, etc. x86/state.c ---*/
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/*--------------------------------------------------------------------*/
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/*
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This file is part of Valgrind, an extensible x86 protected-mode
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emulator for monitoring program execution on x86-Unixes.
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Copyright (C) 2000-2004 Nicholas Nethercote
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njn25@cam.ac.uk
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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#include "core.h"
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#include "x86_private.h"
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#include <sys/ptrace.h>
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#include "libvex_guest_x86.h"
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/*------------------------------------------------------------*/
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/*--- Initialising the first thread ---*/
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/*------------------------------------------------------------*/
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/* Given a pointer to the ThreadArchState for thread 1 (the root
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thread), initialise the VEX guest state, and copy in essential
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starting values.
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*/
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void VGA_(init_thread1state) ( Addr client_eip,
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Addr esp_at_startup,
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/*MOD*/ ThreadArchState* arch )
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{
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vg_assert(0 == sizeof(VexGuestX86State) % 8);
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/* Zero out the initial state, and set up the simulated FPU in a
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sane way. */
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LibVEX_GuestX86_initialise(&arch->vex);
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/* Zero out the shadow area. */
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VG_(memset)(&arch->vex_shadow, 0, sizeof(VexGuestX86State));
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/* Put essential stuff into the new state. */
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/* initialise %cs, %ds and %ss to point at the operating systems
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default code, data and stack segments */
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arch->vex.guest_ESP = esp_at_startup;
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arch->vex.guest_EIP = client_eip;
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asm volatile("movw %%cs, %0"
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:
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: "m" (arch->vex.guest_CS));
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asm volatile("movw %%ds, %0"
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:
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: "m" (arch->vex.guest_DS));
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asm volatile("movw %%ss, %0"
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:
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: "m" (arch->vex.guest_SS));
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VG_TRACK( post_reg_write, Vg_CoreStartup, /*tid*/1, /*offset*/0,
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sizeof(VexGuestArchState));
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/* I assume that if we have SSE2 we also have SSE */
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VG_(have_ssestate) = False;
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// VG_(cpu_has_feature)(VG_X86_FEAT_FXSR) &&
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// VG_(cpu_has_feature)(VG_X86_FEAT_SSE);
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if (0) {
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if (VG_(have_ssestate))
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VG_(printf)("Looks like a SSE-capable CPU\n");
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else
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VG_(printf)("Looks like a MMX-only CPU\n");
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}
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}
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/*------------------------------------------------------------*/
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/*--- Thread stuff ---*/
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/*------------------------------------------------------------*/
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void VGA_(clear_thread)( ThreadArchState *arch )
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{
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arch->ldt = NULL;
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VG_(clear_TLS_for_thread)(arch->tls);
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}
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void VGA_(cleanup_thread) ( ThreadArchState *arch )
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{
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/* Deallocate its LDT, if it ever had one. */
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VG_(deallocate_LDT_for_thread)( arch->ldt );
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arch->ldt = NULL;
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/* Clear its TLS array. */
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VG_(clear_TLS_for_thread)( arch->tls );
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}
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void VGA_(setup_child) ( ThreadArchState *arch, ThreadArchState *parent_arch )
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{
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/* We inherit our parent's LDT. */
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if (parent_arch->ldt == NULL) {
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/* We hope this is the common case. */
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arch->ldt = NULL;
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} else {
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/* No luck .. we have to take a copy of the parent's. */
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arch->ldt = VG_(allocate_LDT_for_thread)( parent_arch->ldt );
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}
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/* Initialise the thread's TLS array */
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VG_(clear_TLS_for_thread)( arch->tls );
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}
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void VGA_(set_arg_and_bogus_ret)( ThreadId tid, UWord arg, Addr ret )
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{
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/* Push the arg, and mark it as readable. */
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SET_PTHREQ_ESP(tid, VG_(threads)[tid].arch.vex.guest_ESP - sizeof(UWord));
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* (UInt*)(VG_(threads)[tid].arch.vex.guest_ESP) = arg;
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VG_TRACK( post_mem_write, Vg_CoreSignal, tid,
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VG_(threads)[tid].arch.vex.guest_ESP, sizeof(void*) );
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/* Don't mark the pushed return address as readable; any attempt to read
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this is an internal valgrind bug since thread_exit_wrapper() should not
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return. */
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SET_PTHREQ_ESP(tid, VG_(threads)[tid].arch.vex.guest_ESP - sizeof(UWord));
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* (UInt*)(VG_(threads)[tid].arch.vex.guest_ESP) = ret;
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}
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void VGA_(thread_initial_stack)(ThreadId tid, UWord arg, Addr ret)
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{
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Addr esp = (Addr)STACK_PTR(VG_(threads)[tid].arch);
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/* push two args */
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esp -= 2 * sizeof(UWord);
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SET_PTHREQ_ESP(tid, esp);
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VG_TRACK ( new_mem_stack, esp, 2 * sizeof(UWord) );
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VG_TRACK ( pre_mem_write, Vg_CorePThread, tid, "new thread: stack",
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esp, 2 * sizeof(UWord) );
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/* push arg and (bogus) return address */
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*(UWord*)(esp+sizeof(UWord)) = arg;
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*(UWord*)(esp) = ret;
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VG_TRACK ( post_mem_write, Vg_CoreSignal, tid, esp, 2 * sizeof(UWord) );
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}
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/*------------------------------------------------------------*/
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/*--- Symtab stuff ---*/
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/*------------------------------------------------------------*/
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/* This is the Intel register encoding -- integer regs. */
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#define R_EAX 0
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#define R_ECX 1
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#define R_EDX 2
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#define R_EBX 3
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#define R_ESP 4
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#define R_EBP 5
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#define R_ESI 6
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#define R_EDI 7
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UInt *VGA_(reg_addr_from_tst)(Int regno, ThreadArchState *arch)
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{
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switch (regno) {
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case R_EAX: return &arch->vex.guest_EAX;
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case R_ECX: return &arch->vex.guest_ECX;
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case R_EDX: return &arch->vex.guest_EDX;
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case R_EBX: return &arch->vex.guest_EBX;
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case R_ESP: return &arch->vex.guest_ESP;
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case R_EBP: return &arch->vex.guest_EBP;
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case R_ESI: return &arch->vex.guest_ESI;
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case R_EDI: return &arch->vex.guest_EDI;
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default: return NULL;
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}
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}
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/*------------------------------------------------------------*/
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/*--- pointercheck ---*/
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/*------------------------------------------------------------*/
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Bool VGA_(setup_pointercheck)(void)
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{
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vki_modify_ldt_t ldt = {
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VG_POINTERCHECK_SEGIDX, // entry_number
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VG_(client_base), // base_addr
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(VG_(client_end)-VG_(client_base)) / VKI_PAGE_SIZE, // limit
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1, // seg_32bit
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0, // contents: data, RW, non-expanding
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0, // ! read_exec_only
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1, // limit_in_pages
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0, // ! seg not present
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1, // useable
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};
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int ret = VG_(do_syscall)(__NR_modify_ldt, 1, &ldt, sizeof(ldt));
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if (ret < 0) {
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VG_(message)(Vg_UserMsg,
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"Warning: ignoring --pointercheck=yes, "
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"because modify_ldt failed (errno=%d)", -ret);
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return False;
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} else {
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return True;
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}
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}
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/*------------------------------------------------------------*/
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/*--- Debugger-related operations ---*/
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/*------------------------------------------------------------*/
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Int VGA_(ptrace_setregs_from_tst)(Int pid, ThreadArchState* arch)
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{
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struct vki_user_regs_struct regs;
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regs.cs = arch->vex.guest_CS;
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regs.ss = arch->vex.guest_SS;
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regs.ds = arch->vex.guest_DS;
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regs.es = arch->vex.guest_ES;
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regs.fs = arch->vex.guest_FS;
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regs.gs = arch->vex.guest_GS;
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regs.eax = arch->vex.guest_EAX;
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regs.ebx = arch->vex.guest_EBX;
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regs.ecx = arch->vex.guest_ECX;
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regs.edx = arch->vex.guest_EDX;
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regs.esi = arch->vex.guest_ESI;
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regs.edi = arch->vex.guest_EDI;
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regs.ebp = arch->vex.guest_EBP;
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regs.esp = arch->vex.guest_ESP;
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regs.eflags = LibVEX_GuestX86_get_eflags(&arch->vex);
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regs.eip = arch->vex.guest_EIP;
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return ptrace(PTRACE_SETREGS, pid, NULL, ®s);
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}
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/*--------------------------------------------------------------------*/
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/*--- end ---*/
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/*--------------------------------------------------------------------*/
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