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Moved the variable VGOFF_(m_eip) from x86, and moved it (and its

Browse Source 
computation) into the generic core, because it's needed by the dispatch
loop of all archs.  Also renamed it VG_(instr_ptr_offset), which is
clearer.  Since it was the last use of the VGOFF_ prefix, I removed that
prefix.  

Also cleaned up the ARM stubs slightly, by removing some of the copied,
commented-out x86 code which has since fallen out of date with the real
x86 code and was thus misleading.


git-svn-id: svn://svn.valgrind.org/valgrind/trunk@3123
This commit is contained in:
Nicholas Nethercote 2004-11-27 14:27:21 +00:00
parent c40ff3902e
commit 5cc18c19a2
10 changed files with 18 additions and 93 deletions
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5
coregrind/arm/core_arch.h
View File

@ -74,11 +74,6 @@
I_die_here; \
} while (0)
#if 0
// So the dispatch loop can find %EIP
extern Int VGOFF_(m_eip);
#endif
/* ---------------------------------------------------------------------
Elf stuff
------------------------------------------------------------------ */

69
coregrind/arm/state.c
View File

@ -38,9 +38,6 @@
/*--- Initialising the first thread ---*/
/*------------------------------------------------------------*/
Int VGOFF_(m_eip) = INVALID_OFFSET;
/* Given a pointer to the ThreadArchState for thread 1 (the root
thread), initialise the VEX guest state, and copy in essential
starting values.
@ -51,49 +48,7 @@ void VGA_(init_thread1state) ( Addr client_eip,
{
I_die_here;
#if 0
vg_assert(0 == sizeof(VexGuestX86State) % 8);
/* Zero out the initial state, and set up the simulated FPU in a
sane way. */
LibVEX_GuestX86_initialise(&arch->vex);
/* Zero out the shadow area. */
VG_(memset)(&arch->vex_shadow, 0, sizeof(VexGuestX86State));
/* Put essential stuff into the new state. */
/* initialise %cs, %ds and %ss to point at the operating systems
default code, data and stack segments */
arch->vex.guest_ESP = esp_at_startup;
arch->vex.guest_EIP = client_eip;
asm volatile("movw %%cs, %0"
:
: "m" (arch->vex.guest_CS));
asm volatile("movw %%ds, %0"
:
: "m" (arch->vex.guest_DS));
asm volatile("movw %%ss, %0"
:
: "m" (arch->vex.guest_SS));
/* The dispatch loop needs to be able to find %EIP given a pointer
to the start of the .vex field. */
VGOFF_(m_eip) = offsetof(VexGuestX86State,guest_EIP)/4;
VG_TRACK( post_reg_write, Vg_CoreStartup, /*tid*/1, /*offset*/0,
sizeof(VexGuestArchState));
/* I assume that if we have SSE2 we also have SSE */
VG_(have_ssestate) = False;
// VG_(cpu_has_feature)(VG_X86_FEAT_FXSR) &&
// VG_(cpu_has_feature)(VG_X86_FEAT_SSE);
if (0) {
if (VG_(have_ssestate))
VG_(printf)("Looks like a SSE-capable CPU\n");
else
VG_(printf)("Looks like a MMX-only CPU\n");
}
// When implementing this, look at x86/state.c
#endif
}
@ -111,14 +66,6 @@ void VGA_(clear_thread)( ThreadArchState *arch )
#endif
}
void VGA_(init_thread)( ThreadArchState *arch )
{
I_die_here;
#if 0
VG_(baseBlock)[VGOFF_(tls_ptr)] = (UInt)arch->tls;
#endif
}
void VGA_(cleanup_thread) ( ThreadArchState *arch )
{
I_die_here;
@ -136,19 +83,7 @@ void VGA_(setup_child) ( ThreadArchState *regs, ThreadArchState *parent_regs )
{
I_die_here;
#if 0
/* We inherit our parent's LDT. */
if (parent_regs->ldt == NULL) {
/* We hope this is the common case. */
VG_(baseBlock)[VGOFF_(ldt)] = 0;
} else {
/* No luck .. we have to take a copy of the parent's. */
regs->ldt = VG_(allocate_LDT_for_thread)( parent_regs->ldt );
VG_(baseBlock)[VGOFF_(ldt)] = (UInt) regs->ldt;
}
/* Initialise the thread's TLS array */
VG_(clear_TLS_for_thread)( regs->tls );
VG_(baseBlock)[VGOFF_(tls_ptr)] = (UInt) regs->tls;
// XXX: look at x86/state.c
#endif
}

5
coregrind/core.h
View File

@ -1239,6 +1239,9 @@ extern void VG_(start_debugger) ( Int tid );
/* Counts downwards in vg_run_innerloop. */
extern UInt VG_(dispatch_ctr);
// Instruction pointer guest state offset, used by $VG_ARCH/dispatch.S.
extern UInt VG_(instr_ptr_offset);
/* --- Counters, for informational purposes only. --- */
// These counters must be declared here because they're maintained by
@ -1753,7 +1756,7 @@ extern void VG_(missing_tool_func) ( const Char* fn );
#define PTHREQ_RET(regs) ((regs).vex.ARCH_PTHREQ_RET)
#define CLREQ_RET(regs) ((regs).vex.ARCH_CLREQ_RET)
// Offsets for the shadow state
// Offsets for the Vex state
#define O_STACK_PTR (offsetof(VexGuestArchState, ARCH_STACK_PTR))
#define O_FRAME_PTR (offsetof(VexGuestArchState, ARCH_FRAME_PTR))

4
coregrind/core_asm.h
View File

@ -50,15 +50,11 @@
#define VG_TRC_INNER_COUNTERZERO 29 /* TRC only; means bb ctr == 0 */
#define VG_TRC_UNRESUMABLE_SIGNAL 37 /* TRC only; got sigsegv/sigbus */
/* Constants for the fast translation lookup cache. */
#define VG_TT_FAST_BITS 15
#define VG_TT_FAST_SIZE (1 << VG_TT_FAST_BITS)
#define VG_TT_FAST_MASK ((VG_TT_FAST_SIZE) - 1)
/* Constants for the fast original-code-write check cache. */
/* Assembly code stubs make this request */
#define VG_USERREQ__SIGNAL_RETURNS 0x4001

1
coregrind/valgrind.vs
View File

@ -3,7 +3,6 @@ VALGRIND_2.1 {
vgPlain_*;
vgTool_*;
vgProf_*;
vgOff_*;
vgArch_*;
*IROp*;
*IRExpr*;

4
coregrind/vg_main.c
View File

@ -142,6 +142,9 @@ Int VG_(client_argc);
Char** VG_(client_argv);
Char** VG_(client_envp);
// Instruction pointer guest state offset, used by $VG_ARCH/dispatch.S.
UInt VG_(instr_ptr_offset);
/* ---------------------------------------------------------------------
Running stuff
------------------------------------------------------------------ */
@ -2617,6 +2620,7 @@ int main(int argc, char **argv)
// setup_scheduler() [for the rest of state 1 stuff]
//--------------------------------------------------------------
VGA_(init_thread1state)(client_eip, sp_at_startup, &VG_(threads)[1].arch );
VG_(instr_ptr_offset) = offsetof(VexGuestArchState, ARCH_INSTR_PTR);
//--------------------------------------------------------------
// Set up the ProxyLWP machinery

2
coregrind/x86/core_arch.h
View File

@ -69,7 +69,7 @@
} while (0)
// So the dispatch loop can find %EIP
extern Int VGOFF_(m_eip);
extern Int vgoff_m_eip;
/* ---------------------------------------------------------------------

12
coregrind/x86/dispatch.S
View File

@ -85,15 +85,15 @@ VG_(run_innerloop):
movl 28(%esp), %ebp
/* fetch m_eip into %eax */
movl VGOFF_(m_eip), %esi
movl (%ebp, %esi, 4), %eax
movl VG_(instr_ptr_offset), %esi
movl (%ebp, %esi, 1), %eax
/* fall into main loop */
dispatch_boring:
/* save the jump address in the guest state */
movl VGOFF_(m_eip), %esi
movl %eax, (%ebp, %esi, 4)
movl VG_(instr_ptr_offset), %esi
movl %eax, (%ebp, %esi, 1)
/* Are we out of timeslice? If yes, defer to scheduler. */
subl $1, VG_(dispatch_ctr)
@ -160,9 +160,9 @@ dispatch_exceptional:
jz counter_is_zero
/* save %eax in %EIP and defer to sched */
movl VGOFF_(m_eip), %esi
movl VG_(instr_ptr_offset), %esi
movl 28(%esp), %edi
movl %eax, (%edi, %esi, 4)
movl %eax, (%edi, %esi, 1)
movl %ebp, %eax
jmp run_innerloop_exit

8
coregrind/x86/state.c
View File

@ -38,9 +38,6 @@
/*--- Initialising the first thread ---*/
/*------------------------------------------------------------*/
Int VGOFF_(m_eip) = INVALID_OFFSET;
/* Given a pointer to the ThreadArchState for thread 1 (the root
thread), initialise the VEX guest state, and copy in essential
starting values.
@ -74,10 +71,6 @@ void VGA_(init_thread1state) ( Addr client_eip,
:
: "m" (arch->vex.guest_SS));
/* The dispatch loop needs to be able to find %EIP given a pointer
to the start of the .vex field. */
VGOFF_(m_eip) = offsetof(VexGuestX86State,guest_EIP)/4;
VG_TRACK( post_reg_write, Vg_CoreStartup, /*tid*/1, /*offset*/0,
sizeof(VexGuestArchState));
@ -253,3 +246,4 @@ Int VGA_(ptrace_setregs_from_tst)(Int pid, ThreadArchState* arch)
/*--------------------------------------------------------------------*/
/*--- end ---*/
/*--------------------------------------------------------------------*/

1
include/tool_asm.h
View File

@ -42,7 +42,6 @@
name can safely be used across different macros. */
#define VG_(str) VGAPPEND(vgPlain_,str)
#define VGP_(str) VGAPPEND(vgProf_,str)
#define VGOFF_(str) VGAPPEND(vgOff_,str)
#define VGA_(str) VGAPPEND(vgArch_,str)
/* Tool-specific ones. Note that final name still starts with "vg". */