mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
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a30916183c
correctly
1) Fix Endianess issue that was missed in the BE to LE port. GDB was
not displaying the contents of the 64-bit and 128-bit registers
correctly due to an Endianess issue.
2) Fix displaying the shadow registers for the 64-bit and 128-bit
registers.
Bugzilla 360008 was opened for this issue.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15864
57 lines
2.6 KiB
XML
57 lines
2.6 KiB
XML
<?xml version="1.0"?>
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<!-- Copyright (C) 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE feature SYSTEM "gdb-target.dtd">
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<feature name="org.gnu.gdb.power.core">
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<reg name="r0" bitsize="64" type="uint64"/>
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<reg name="r1" bitsize="64" type="uint64"/>
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<reg name="r2" bitsize="64" type="uint64"/>
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<reg name="r3" bitsize="64" type="uint64"/>
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<reg name="r4" bitsize="64" type="uint64"/>
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<reg name="r5" bitsize="64" type="uint64"/>
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<reg name="r6" bitsize="64" type="uint64"/>
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<reg name="r7" bitsize="64" type="uint64"/>
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<reg name="r8" bitsize="64" type="uint64"/>
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<reg name="r9" bitsize="64" type="uint64"/>
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<reg name="r10" bitsize="64" type="uint64"/>
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<reg name="r11" bitsize="64" type="uint64"/>
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<reg name="r12" bitsize="64" type="uint64"/>
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<reg name="r13" bitsize="64" type="uint64"/>
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<reg name="r14" bitsize="64" type="uint64"/>
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<reg name="r15" bitsize="64" type="uint64"/>
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<reg name="r16" bitsize="64" type="uint64"/>
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<reg name="r17" bitsize="64" type="uint64"/>
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<reg name="r18" bitsize="64" type="uint64"/>
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<reg name="r19" bitsize="64" type="uint64"/>
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<reg name="r20" bitsize="64" type="uint64"/>
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<reg name="r21" bitsize="64" type="uint64"/>
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<reg name="r22" bitsize="64" type="uint64"/>
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<reg name="r23" bitsize="64" type="uint64"/>
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<reg name="r24" bitsize="64" type="uint64"/>
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<reg name="r25" bitsize="64" type="uint64"/>
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<reg name="r26" bitsize="64" type="uint64"/>
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<reg name="r27" bitsize="64" type="uint64"/>
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<reg name="r28" bitsize="64" type="uint64"/>
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<reg name="r29" bitsize="64" type="uint64"/>
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<reg name="r30" bitsize="64" type="uint64"/>
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<reg name="r31" bitsize="64" type="uint64"/>
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<!-- Note, the following register definitions must be in this file by
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the "standard target features" for this processor. GDB will reject
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this file description if the following register definitions are
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not in this file. Hence, they can't be moved to power64-core2.xml
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for consistency with what was done for the shadow register definitions
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to get the shadow register print order to match the print order of
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the HW registers -->
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<reg name="pc" bitsize="64" type="code_ptr" regnum="64"/>
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<reg name="msr" bitsize="64" type="uint64"/>
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<reg name="cr" bitsize="32" type="uint32"/>
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<reg name="lr" bitsize="64" type="code_ptr"/>
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<reg name="ctr" bitsize="64" type="uint64"/>
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<reg name="xer" bitsize="32" type="uint32"/>
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</feature>
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