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9fc2bfba5c
This set of tests covers MIPS r6 specific instructions: none/tests/mips32/MIPS32r6int none/tests/mips32/branch_pc none/tests/mips32/branches_r6 none/tests/mips32/fp_r6 none/tests/mips32/pc_instructions_r6 none/tests/mips64/MIPS64r6int none/tests/mips64/branch_pc none/tests/mips64/branches_r6 none/tests/mips64/fp_r6 none/tests/mips64/pc_instructions_r6 none/tests/mips64/r6_instructions The following tests had to be changed to be applicaple for Rev6: none/tests/libvex_test.c none/tests/mips32/LoadStore none/tests/mips32/LoadStore1 none/tests/mips32/MIPS32int none/tests/mips32/MoveIns none/tests/mips32/branches none/tests/mips32/change_fp_mode none/tests/mips32/mips32_dsp none/tests/mips32/vfp none/tests/mips64/arithmetic_instruction none/tests/mips64/branches none/tests/mips64/fpu_arithmetic none/tests/mips64/fpu_load_store none/tests/mips64/load_store none/tests/mips64/load_store_multiple none/tests/mips64/move_instructions The following tests are not applicable for Rev6: none/tests/mips32/fpu_branches none/tests/mips32/unaligned_load_store none/tests/mips64/branch_and_jump_instructions none/tests/mips64/change_fp_mode none/tests/mips64/fpu_branches none/tests/mips64/load_store_unaligned none/tests/mips64/unaligned_load none/tests/mips64/unaligned_load_store. Contributed by: Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic. Related BZ issue - #387410.
69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
#include <stdio.h>
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unsigned int mem[] = {
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0xaabbccdd, 0x11223344, 0x01823194, 0x01823a08,
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0x00000000, 0x77ff528c, 0x77deb460, 0x00000001
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};
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void printMem(char* s)
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{
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int i;
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printf("%s\n", s);
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for (i=0; i<7 ; i=i+1)
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printf("mem[%d]: 0x%x\n", i, mem[i]);
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}
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int main ()
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{
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#if (__mips_isa_rev<6)
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printMem("PRE lwl");
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__asm__ volatile("move $a0, %0" "\n\t"
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"lw $t0, 0($a0)" "\n\t"
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"lwl $t0, 4($a0)" "\n\t"
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"sw $t0, 8($a0)" "\n\t"
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"lw $t1, 0($a0)" "\n\t"
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"lwl $t1, 5($a0)" "\n\t"
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"sw $t1, 12($a0)" "\n\t"
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"lw $t2, 0($a0)" "\n\t"
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"lwl $t2, 6($a0)" "\n\t"
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"sw $t2, 16($a0)" "\n\t"
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"lw $t3, 0($a0)" "\n\t"
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"lwl $t3, 7($a0)" "\n\t"
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"sw $t3, 20($a0)" "\n\t"
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:
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: "r" (mem)
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: "a0", "t0", "t1", "t2", "t3", "cc", "memory"
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);
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printMem("POST lwl");
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mem[0] = 0xaabbccdd;
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mem[1] = 0x11223344;
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mem[2] = 0x01823194;
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mem[3] = 0x01823a08;
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mem[4] = 0x00000000;
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mem[5] = 0x77ff528c;
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mem[6] = 0x77deb460;
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mem[7] = 0x00000001;
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printMem("PRE lwr");
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__asm__ volatile("move $a0, %0" "\n\t"
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"lw $t0, 0($a0)" "\n\t"
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"lwr $t0, 4($a0)" "\n\t"
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"sw $t0, 8($a0)" "\n\t"
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"lw $t1, 0($a0)" "\n\t"
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"lwr $t1, 5($a0)" "\n\t"
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"sw $t1, 12($a0)" "\n\t"
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"lw $t2, 0($a0)" "\n\t"
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"lwr $t2, 6($a0)" "\n\t"
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"sw $t2, 16($a0)" "\n\t"
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"lw $t3, 0($a0)" "\n\t"
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"lwr $t3, 7($a0)" "\n\t"
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"sw $t3, 20($a0)" "\n\t"
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:
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: "r" (mem)
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: "a0", "t0", "t1", "t2", "t3", "cc", "memory"
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);
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printMem("POST lwr");
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#endif
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return 0;
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}
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