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This set of tests covers MIPS r6 specific instructions: none/tests/mips32/MIPS32r6int none/tests/mips32/branch_pc none/tests/mips32/branches_r6 none/tests/mips32/fp_r6 none/tests/mips32/pc_instructions_r6 none/tests/mips64/MIPS64r6int none/tests/mips64/branch_pc none/tests/mips64/branches_r6 none/tests/mips64/fp_r6 none/tests/mips64/pc_instructions_r6 none/tests/mips64/r6_instructions The following tests had to be changed to be applicaple for Rev6: none/tests/libvex_test.c none/tests/mips32/LoadStore none/tests/mips32/LoadStore1 none/tests/mips32/MIPS32int none/tests/mips32/MoveIns none/tests/mips32/branches none/tests/mips32/change_fp_mode none/tests/mips32/mips32_dsp none/tests/mips32/vfp none/tests/mips64/arithmetic_instruction none/tests/mips64/branches none/tests/mips64/fpu_arithmetic none/tests/mips64/fpu_load_store none/tests/mips64/load_store none/tests/mips64/load_store_multiple none/tests/mips64/move_instructions The following tests are not applicable for Rev6: none/tests/mips32/fpu_branches none/tests/mips32/unaligned_load_store none/tests/mips64/branch_and_jump_instructions none/tests/mips64/change_fp_mode none/tests/mips64/fpu_branches none/tests/mips64/load_store_unaligned none/tests/mips64/unaligned_load none/tests/mips64/unaligned_load_store. Contributed by: Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic. Related BZ issue - #387410.
152 lines
6.1 KiB
Makefile
152 lines
6.1 KiB
Makefile
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include $(top_srcdir)/Makefile.tool-tests.am
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dist_noinst_SCRIPTS = filter_stderr
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EXTRA_DIST = \
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arithmetic_instruction.stdout.exp-mips64 \
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arithmetic_instruction.stdout.exp-mips64r2 arithmetic_instruction.stderr.exp \
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arithmetic_instruction.vgtest arithmetic_instruction.stdout.exp-mips64r6 \
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branch_and_jump_instructions.stdout.exp \
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branch_and_jump_instructions.stderr.exp branch_and_jump_instructions.vgtest \
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branches.stdout.exp branches.stderr.exp branches.vgtest branches.stdout.exp-r6 \
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branches_r6.stderr.exp branches_r6.stdout.exp branches_r6.vgtest\
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branch_pc.stderr.exp branch_pc.stdout.exp branch_pc.vgtest \
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change_fp_mode.stderr.exp change_fp_mode.stdout.exp change_fp_mode.vgtest \
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cvm_bbit.stdout.exp cvm_bbit.stdout.exp-non-octeon \
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cvm_bbit.stderr.exp cvm_bbit.vgtest \
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cvm_ins.stdout.exp cvm_ins.stdout.exp-non-octeon \
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cvm_ins.stderr.exp cvm_ins.vgtest \
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cvm_lx_ins.stdout.exp-LE cvm_lx_ins.stdout.exp-BE \
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cvm_lx_ins.stdout.exp-non-octeon \
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cvm_lx_ins.stderr.exp cvm_lx_ins.vgtest \
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cvm_atomic.stdout.exp-LE cvm_atomic.stdout.exp-BE \
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cvm_atomic.stdout.exp-non-octeon \
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cvm_atomic.stderr.exp cvm_atomic.vgtest \
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cvm_atomic_thread.stdout.exp cvm_atomic_thread.stdout.exp-non-octeon \
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cvm_atomic_thread.stderr.exp cvm_atomic_thread.vgtest \
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extract_insert_bit_field.stdout.exp-mips64 \
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extract_insert_bit_field.stdout.exp-mips64r2 \
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extract_insert_bit_field.stderr.exp extract_insert_bit_field.vgtest \
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fpu_arithmetic.stdout.exp fpu_arithmetic.stderr.exp fpu_arithmetic.vgtest \
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fpu_arithmetic.stdout.exp-r6 \
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fpu_branches.stdout.exp fpu_branches.stderr.exp fpu_branches.vgtest \
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fpu_control_word.stdout.exp fpu_control_word.stderr.exp \
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fpu_control_word.vgtest \
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fpu_load_store.stdout.exp-BE fpu_load_store.stdout.exp-LE \
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fpu_load_store.stderr.exp fpu_load_store.vgtest \
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fpu_load_store.stdout.exp-BE-r2 fpu_load_store.stdout.exp-LE-r2 \
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fpu_load_store.stdout.exp-BE-r6 fpu_load_store.stdout.exp-LE-r6 \
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fp_r6.stderr.exp fp_r6.stdout.exp fp_r6.vgtest \
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load_indexed_instructions.stdout.exp-BE \
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load_indexed_instructions.stdout.exp-LE \
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load_indexed_instructions.stdout.exp-non-octeon \
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load_indexed_instructions.stderr.exp load_indexed_instructions.vgtest \
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load_store.stdout.exp-BE load_store.stdout.exp-LE load_store.stderr.exp \
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load_store.vgtest load_store.stdout.exp-LE-r6 load_store.stdout.exp-BE-r6 \
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load_store_multiple.stdout.exp-BE load_store_multiple.stdout.exp-LE \
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load_store_multiple.stderr.exp load_store_multiple.vgtest \
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load_store_multiple.stdout.exp-LE-r6 load_store_multiple.stdout.exp-BE-r6 \
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load_store_unaligned.stdout.exp load_store_unaligned.stderr.exp \
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logical_instructions.stdout.exp logical_instructions.stderr.exp \
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load_store_unaligned.vgtest \
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logical_instructions.vgtest \
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move_instructions.stdout.exp-BE move_instructions.stdout.exp-LE \
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move_instructions.stderr.exp move_instructions.vgtest \
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move_instructions.stdout.exp-r6 \
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MIPS64r6int.stderr.exp MIPS64r6int.stdout.exp MIPS64r6int.vgtest \
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msa_data_transfer.stdout.exp msa_data_transfer.stderr.exp \
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msa_data_transfer.vgtest msa_data_transfer.stdout.exp-BE \
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msa_arithmetic.stderr.exp msa_arithmetic.stdout.exp msa_arithmetic.vgtest \
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msa_comparison.stderr.exp msa_comparison.stdout.exp msa_comparison.vgtest \
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msa_fpu.stderr.exp msa_fpu.stdout.exp msa_fpu.vgtest \
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msa_logical_and_shift.stderr.exp msa_logical_and_shift.stdout.exp \
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msa_logical_and_shift.vgtest msa_shuffle.stderr.exp msa_shuffle.stdout.exp \
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msa_shuffle.vgtest\
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rotate_swap.stdout.exp-mips64 rotate_swap.stdout.exp-mips64r2 \
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rotate_swap.stderr.exp rotate_swap.vgtest \
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round.stdout.exp round.stderr.exp round.vgtest \
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r6_instructions.stdout.exp-LE r6_instructions.stdout.exp-BE r6_instructions.stderr.exp \
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r6_instructions.vgtest \
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pc_instructions_r6.stderr.exp pc_instructions_r6.stdout.exp pc_instructions_r6.vgtest \
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shift_instructions.stdout.exp-mips64 shift_instructions.stdout.exp-mips64r2 \
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shift_instructions.stderr.exp shift_instructions.vgtest \
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test_block_size.stdout.exp test_block_size.stderr.exp \
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test_block_size.vgtest \
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test_fcsr.stdout.exp test_fcsr.stderr.exp \
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test_fcsr.vgtest \
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test_math.stdout.exp test_math.stdout.exp-older-gcc \
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test_math.stderr.exp test_math.vgtest \
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unaligned_load.stdout.exp-BE unaligned_load.stdout.exp-LE \
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unaligned_load.stderr.exp unaligned_load.vgtest \
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unaligned_load_store.stdout.exp-LE unaligned_load_store.stdout.exp-BE \
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unaligned_load_store.stderr.exp unaligned_load_store.vgtest \
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const.h macro_fpu.h macro_int.h macro_load_store.h rounding_mode.h
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check_PROGRAMS = \
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allexec \
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arithmetic_instruction \
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branch_and_jump_instructions \
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branches \
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branches_r6 \
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branch_pc \
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change_fp_mode \
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cvm_bbit \
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cvm_ins \
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cvm_lx_ins \
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cvm_atomic \
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cvm_atomic_thread \
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extract_insert_bit_field \
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fpu_arithmetic \
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fpu_branches \
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fpu_control_word \
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fpu_load_store \
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fp_r6 \
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load_indexed_instructions \
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load_store \
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load_store_multiple \
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load_store_unaligned \
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logical_instructions \
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move_instructions \
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msa_data_transfer \
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msa_arithmetic \
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msa_comparison \
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msa_fpu \
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msa_logical_and_shift \
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msa_shuffle \
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r6_instructions \
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MIPS64r6int \
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pc_instructions_r6 \
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rotate_swap \
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round \
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shift_instructions \
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test_block_size \
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test_fcsr \
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test_math \
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unaligned_load \
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unaligned_load_store
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AM_CFLAGS += @FLAG_M64@
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AM_CXXFLAGS += @FLAG_M64@
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AM_CCASFLAGS += @FLAG_M64@
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allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
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cvm_bbit_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON@
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cvm_ins_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON@
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cvm_lx_ins_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@
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cvm_atomic_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@
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cvm_atomic_thread_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@
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load_indexed_instructions_CFLAGS = $(AM_CFLAGS) -g -O0 @FLAG_OCTEON2@
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fpu_arithmetic_CFLAGS = $(AM_CFLAGS) -lm
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msa_arithmetic_CFLAGS = $(AM_CFLAGS) @FLAG_MSA@
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msa_comparison_CFLAGS = $(AM_CFLAGS) @FLAG_MSA@
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msa_data_transfer_CFLAGS = $(AM_CFLAGS) @FLAG_MSA@
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msa_fpu_CFLAGS = $(AM_CFLAGS) @FLAG_MSA@
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msa_logical_and_shift_CFLAGS = $(AM_CFLAGS) @FLAG_MSA@
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msa_shuffle_CFLAGS = $(AM_CFLAGS) @FLAG_MSA@
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# C++ tests
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test_math_SOURCES = test_math.cpp
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