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9fc2bfba5c
This set of tests covers MIPS r6 specific instructions: none/tests/mips32/MIPS32r6int none/tests/mips32/branch_pc none/tests/mips32/branches_r6 none/tests/mips32/fp_r6 none/tests/mips32/pc_instructions_r6 none/tests/mips64/MIPS64r6int none/tests/mips64/branch_pc none/tests/mips64/branches_r6 none/tests/mips64/fp_r6 none/tests/mips64/pc_instructions_r6 none/tests/mips64/r6_instructions The following tests had to be changed to be applicaple for Rev6: none/tests/libvex_test.c none/tests/mips32/LoadStore none/tests/mips32/LoadStore1 none/tests/mips32/MIPS32int none/tests/mips32/MoveIns none/tests/mips32/branches none/tests/mips32/change_fp_mode none/tests/mips32/mips32_dsp none/tests/mips32/vfp none/tests/mips64/arithmetic_instruction none/tests/mips64/branches none/tests/mips64/fpu_arithmetic none/tests/mips64/fpu_load_store none/tests/mips64/load_store none/tests/mips64/load_store_multiple none/tests/mips64/move_instructions The following tests are not applicable for Rev6: none/tests/mips32/fpu_branches none/tests/mips32/unaligned_load_store none/tests/mips64/branch_and_jump_instructions none/tests/mips64/change_fp_mode none/tests/mips64/fpu_branches none/tests/mips64/load_store_unaligned none/tests/mips64/unaligned_load none/tests/mips64/unaligned_load_store. Contributed by: Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic. Related BZ issue - #387410.
373 lines
16 KiB
C
373 lines
16 KiB
C
#include <stdio.h>
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#include "const.h"
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#include "macro_int.h"
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#if (__mips_isa_rev < 6)
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typedef enum {
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ADD=0, ADDI, ADDIU, ADDU,
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CLO, CLZ, DADD, DADDI,
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DADDIU, DADDU, DCLO, DCLZ,
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DDIV, DDIVU, DIV, DIVU,
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DMULT, DMULTU, DSUB, DSUBU,
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MADD, MADDU, MSUB, MSUBU,
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MUL, MULT, MULTU, MOVN,
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MOVZ, SEB, SEH, SLT,
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SLTI, SLTIU, SLTU, SUB,
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SUBU
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} arithmetic_op;
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#else
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typedef enum {
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ADD=0, ADDIU, ADDU,
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CLO, CLZ, DCLO, DCLZ,
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DADD, DADDIU, DADDU,
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DSUB, DSUBU, SUB, SUBU,
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SEB, SEH,
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SLT, SLTI, SLTIU, SLTU
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} arithmetic_op;
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#endif
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int main()
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{
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arithmetic_op op;
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int i;
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init_reg_val2();
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for (op = ADD; op <= SUBU; op++) {
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for (i = 0; i < N; i++) {
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switch(op) {
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case ADD:
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/* If either GPR rt or GPR rs does not contain sign-extended
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32-bit values (bits 63..31 equal), then the result of the
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operation is UNPREDICTABLE. */
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TEST1("add $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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break;
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#if (__mips_isa_rev < 6)
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case ADDI:
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/* If GPR rs does not contain a sign-extended 32-bit
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value (bits 63..31 equal), then the result of the operation
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is UNPREDICTABLE. */
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TEST2("addi $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
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TEST2("addi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
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TEST2("addi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
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TEST2("addi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
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break;
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#endif
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case ADDIU:
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/* If GPR rs does not contain a sign-extended 32-bit
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value (bits 63..31 equal), then the result of the operation
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is UNPREDICTABLE. */
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TEST2("addiu $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
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TEST2("addiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
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TEST2("addiu $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
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TEST2("addiu $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
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break;
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case ADDU:
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/* If either GPR rt or GPR rs does not contain sign-extended
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32-bit values (bits 63..31 equal), then the result of the
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operation is UNPREDICTABLE. */
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TEST1("addu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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break;
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case CLO:
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/* If GPR rs does not contain a sign-extended 32-bit
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value (bits 63..31 equal), then the results of the operation
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are UNPREDICTABLE. */
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TEST3("clo $t0, $t1", reg_val1[i], t0, t1);
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break;
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case CLZ:
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/* If GPR rs does not contain a sign-extended 32-bit
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value (bits 63..31 equal), then the results of the operation
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are UNPREDICTABLE. */
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TEST3("clz $t0, $t1", reg_val1[i], t0, t1);
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break;
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case DADD:
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/* If the addition results in 64-bit 2âs complement arithmetic
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overflow, then the destination register is not modified and
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an IntegerOverflow exception occurs. */
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TEST1("dadd $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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break;
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#if (__mips_isa_rev < 6)
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case DADDI:
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/* If the addition results in 64-bit 2âs complement arithmetic
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overflow, then the destination register is not modified and
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an Integer Overflow exception occurs. */
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TEST2("daddi $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
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TEST2("daddi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
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TEST2("daddi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
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TEST2("daddi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
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TEST2("daddi $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1);
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TEST2("daddi $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
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TEST2("daddi $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1);
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TEST2("daddi $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1);
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break;
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#endif
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case DADDIU:
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/* No Integer Overflow exception occurs under any
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circumstances. */
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TEST2("daddiu $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
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TEST2("daddiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
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TEST2("daddiu $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
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TEST2("daddiu $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
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TEST2("daddiu $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1);
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TEST2("daddiu $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
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TEST2("daddiu $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1);
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TEST2("daddiu $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1);
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break;
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case DADDU:
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/* No Integer Overflow exception occurs under any
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circumstances. */
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TEST1("daddu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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TEST1("daddu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
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s0, s1, s2);
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break;
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case DCLO:
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/* No arithmetic exception occurs under any circumstances. */
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TEST3("dclo $t0, $t1", reg_val1[i], t0, t1);
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TEST3("dclo $v0, $v1", reg_val2[i], v0, v1);
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break;
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case DCLZ:
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/* No arithmetic exception occurs under any circumstances. */
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TEST3("dclz $t0, $t1", reg_val1[i], t0, t1);
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TEST3("dclz $v0, $v1", reg_val2[i], v0, v1);
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break;
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#if (__mips_isa_rev < 6)
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case DDIV:
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/* If the divisor in GPR rt is zero, the arithmetic result value
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is UNPREDICTABLE. */
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if (reg_val1[N-i-1] != 0)
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TEST4("ddiv $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
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if (reg_val2[N-i-1] != 0)
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TEST4("ddiv $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1);
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break;
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case DDIVU:
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/* If the divisor in GPR rt is zero, the arithmetic result value
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is UNPREDICTABLE. */
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if (reg_val1[N-i-1] != 0)
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TEST4("ddivu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
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if (reg_val2[N-i-1] != 0)
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TEST4("ddivu $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1);
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break;
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case DIV:
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/* If either GPR rt or GPR rs does not contain sign-extended
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32-bit values (bits 63..31 equal), then the result of the
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operation is UNPREDICTABLE.
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If the divisor in GPR rt is zero, the arithmetic result
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value is UNPREDICTABLE. */
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if (reg_val1[N-i-1] != 0)
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TEST4("div $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
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break;
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case DIVU:
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/* If either GPR rt or GPR rs does not contain sign-extended
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32-bit values (bits 63..31 equal), then the result of the
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operation is UNPREDICTABLE.
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If the divisor in GPR rt is zero, the arithmetic result
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value is UNPREDICTABLE. */
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if (reg_val1[N-i-1] != 0)
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TEST4("divu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
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break;
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case DMULT:
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/* No arithmetic exception occurs under any circumstances. */
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TEST4("dmult $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
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TEST4("dmult $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1);
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break;
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case DMULTU:
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/* No arithmetic exception occurs under any circumstances. */
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TEST4("dmultu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
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TEST4("dmultu $v0, $v1", reg_val2[i], reg_val2[N-i-1], v0, v1);
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break;
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#endif
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case DSUB:
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/* If the subtraction results in 64-bit 2âs complement
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arithmetic overflow, then the destination register is not
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modified and an Integer Overflow exception occurs. */
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TEST1("dsub $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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break;
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case DSUBU:
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/* No Integer Overflow exception occurs under any
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circumstances. */
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TEST1("dsubu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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TEST1("dsubu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
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s0, s1, s2);
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break;
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#if (__mips_isa_rev < 6)
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case MADD:
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/* If GPRs rs or rt do not contain sign-extended 32-bit
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values (bits 63..31 equal), then the results of the operation
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are UNPREDICTABLE. */
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TEST5("madd $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
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break;
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case MADDU:
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/* If GPRs rs or rt do not contain sign-extended 32-bit
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values (bits 63..31 equal), then the results of the operation
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are UNPREDICTABLE. */
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TEST5("maddu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
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break;
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case MSUB:
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/* If GPR rs or rt do not contain a sign-extended 32-bit
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value (bits 63..31 equal), then the results of the operation
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are UNPREDICTABLE. */
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TEST5("msub $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
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break;
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case MSUBU:
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/* If GPRs rs or rt do not contain sign-extended 32-bit
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values (bits 63..31 equal), then the results of the operation
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are UNPREDICTABLE.
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This instruction does not provide the capability of writing
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directly to a target GPR. */
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TEST5("msubu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
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break;
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case MUL:
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/* On 64-bit processors, if either GPR rt or GPR rs does not
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contain sign-extended 32-bit values (bits 63..31 equal), then
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the result of the operation is UNPREDICTABLE. */
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TEST1("mul $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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break;
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case MULT:
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/* On 64-bit processors, if either GPR rt or GPR rs does not
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contain sign-extended 32-bit values (bits 63..31 equal), then
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the result of the operation is UNPREDICTABLE. */
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TEST4("mult $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
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break;
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case MULTU:
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/* On 64-bit processors, if either GPR rt or GPR rs does not
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contain sign-extended 32-bit values (bits 63..31 equal), then
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the result of the operation is UNPREDICTABLE. */
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TEST4("multu $t0, $t1", reg_val1[i], reg_val1[N-i-1], t0, t1);
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break;
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case MOVN:
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/* The arithmetic comparison does not cause an Integer Overflow
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exception. */
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TEST1("movn $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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TEST1("movn $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
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s0, s1, s2);
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break;
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case MOVZ:
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/* The arithmetic comparison does not cause an Integer Overflow
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exception. */
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TEST1("movz $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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TEST1("movz $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
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s0, s1, s2);
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break;
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#endif
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case SEB:
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#if (__mips==64) && (__mips_isa_rev>=2)
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/* If GPR rt does not contain a sign-extended 32-bit
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value (bits 63..31 equal), then the result of the operation
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is UNPREDICTABLE. */
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TEST3("seb $t0, $t1", reg_val1[i], t0, t1);
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#endif
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break;
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case SEH:
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#if (__mips==64) && (__mips_isa_rev>=2)
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/* If GPR rt does not contain a sign-extended 32-bit
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value (bits 63..31 equal), then the result of the operation
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is UNPREDICTABLE. */
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TEST3("seh $t0, $t1", reg_val1[i], t0, t1);
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#endif
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break;
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case SLT:
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/* The arithmetic comparison does not cause an Integer Overflow
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exception. */
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TEST1("slt $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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break;
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case SLTI:
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/* The arithmetic comparison does not cause an Integer Overflow
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exception. */
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TEST2("slti $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
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TEST2("slti $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
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TEST2("slti $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
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TEST2("slti $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
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TEST2("slti $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1);
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TEST2("slti $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
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TEST2("slti $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1);
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TEST2("slti $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1);
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break;
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case SLTIU:
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/* The arithmetic comparison does not cause an Integer Overflow
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exception. */
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TEST2("sltiu $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
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TEST2("sltiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
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TEST2("sltiu $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
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TEST2("sltiu $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
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TEST2("sltiu $t0, $t1, 0xff", reg_val2[i], 0xff, t0, t1);
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TEST2("sltiu $t2, $t3, 0xffff", reg_val2[i], 0xffff, t2, t3);
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TEST2("sltiu $a0, $a1, 0x0", reg_val2[i], 0x0, a0, a1);
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TEST2("sltiu $s0, $s1, 0x23", reg_val2[i], 0x23, s0, s1);
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break;
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case SLTU:
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/* The arithmetic comparison does not cause an Integer Overflow
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exception. */
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TEST1("sltu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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TEST1("sltu $s0, $s1, $s2", reg_val2[i], reg_val2[N-i-1],
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s0, s1, s2);
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break;
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case SUB:
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/* On 64-bit processors, if either GPR rt or GPR rs does not
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contain sign-extended 32-bit values (bits 63..31 equal), then
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the result of the operation is UNPREDICTABLE. */
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if (i < 8 || (i > 15 && i < 22))
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TEST1("sub $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
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t0, t1, t2);
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break;
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case SUBU:
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/* On 64-bit processors, if either GPR rt or GPR rs does not
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contain sign-extended 32-bit values (bits 63..31 equal), then
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the result of the operation is UNPREDICTABLE. */
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TEST1("subu $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
|
|
t0, t1, t2);
|
|
break;
|
|
default:
|
|
printf("Error!\n");
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
return 0;
|
|
}
|