ftmemsim-valgrind/none/tests/mips32/SignalException.c
Petar Jovanovic 9fc2bfba5c mips: add tests for mips32/mips64 R6
This set of tests covers MIPS r6 specific instructions:

  none/tests/mips32/MIPS32r6int
  none/tests/mips32/branch_pc
  none/tests/mips32/branches_r6
  none/tests/mips32/fp_r6
  none/tests/mips32/pc_instructions_r6

  none/tests/mips64/MIPS64r6int
  none/tests/mips64/branch_pc
  none/tests/mips64/branches_r6
  none/tests/mips64/fp_r6
  none/tests/mips64/pc_instructions_r6
  none/tests/mips64/r6_instructions

The following tests had to be changed to be applicaple for Rev6:

  none/tests/libvex_test.c

  none/tests/mips32/LoadStore
  none/tests/mips32/LoadStore1
  none/tests/mips32/MIPS32int
  none/tests/mips32/MoveIns
  none/tests/mips32/branches
  none/tests/mips32/change_fp_mode
  none/tests/mips32/mips32_dsp
  none/tests/mips32/vfp

  none/tests/mips64/arithmetic_instruction
  none/tests/mips64/branches
  none/tests/mips64/fpu_arithmetic
  none/tests/mips64/fpu_load_store
  none/tests/mips64/load_store
  none/tests/mips64/load_store_multiple
  none/tests/mips64/move_instructions

The following tests are not applicable for Rev6:

  none/tests/mips32/fpu_branches
  none/tests/mips32/unaligned_load_store

  none/tests/mips64/branch_and_jump_instructions
  none/tests/mips64/change_fp_mode
  none/tests/mips64/fpu_branches
  none/tests/mips64/load_store_unaligned
  none/tests/mips64/unaligned_load
  none/tests/mips64/unaligned_load_store.

Contributed by:
  Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic.

Related BZ issue - #387410.
2018-02-01 18:37:28 +01:00

106 lines
2.3 KiB
C

/*
Check that a fault signal handler gets the expected info
*/
#include <signal.h>
#include <stdio.h>
#include <stdlib.h>
#include <fcntl.h>
#include <setjmp.h>
#include <unistd.h>
struct test {
void (*test)(void);
int sig;
int code;
};
static const struct test *curr_test;
static jmp_buf escape;
static int testsig(int sig, int want)
{
if (sig != want) {
fprintf(stderr, " FAIL: expected signal %d, not %d\n", want, sig);
return 0;
}
return 1;
}
static int testcode(int code, int want)
{
if (code != want) {
fprintf(stderr, " FAIL: expected si_code==%d, not %d\n", want, code);
return 0;
}
return 1;
}
static void handler(int sig, siginfo_t *si, void *uc)
{
int ok = 1;
ok = ok && testsig(sig, curr_test->sig);
ok = ok && testcode(si->si_code, curr_test->code);
if (ok)
fprintf(stderr, " PASS\n");
siglongjmp(escape, ok + 1);
}
static void test1(void)
{
__asm__ volatile("li $t0, 0x80000000\n\t"
"move $t1, $t0\n\t"
"add $a0, $t0, $t1\n\t"
: : : "t0", "t1", "a0", "cc", "memory");
}
static void test2()
{
__asm__ volatile("li $t0, 0x7fffffff\n\t"
"li $a0, 0x7fff\n\t"
"add $a0, $t0, $a0\n\t"
: : : "t0", "a0", "cc", "memory");
}
static void test3(void)
{
__asm__ volatile("li $t0, 0xffff0000\n\t"
"li $t1, 0x7fffffff\n\t"
"sub $a0, $t0, $t1\n\t"
: : : "t0", "t1", "a0", "cc", "memory");
}
int main()
{
int i;
static const int sigs[] = { SIGFPE };
struct sigaction sa;
sa.sa_sigaction = handler;
sa.sa_flags = SA_SIGINFO;
sigfillset(&sa.sa_mask);
for(i = 0; i < sizeof(sigs)/sizeof(*sigs); i++)
sigaction(sigs[i], &sa, NULL);
const struct test tests[] = {
#define T(n, sig, code) { test##n, sig, code }
T(1, SIGFPE, FPE_INTOVF),
T(2, SIGFPE, FPE_INTOVF),
T(3, SIGFPE, FPE_INTOVF),
#undef T
};
for(i = 0; i < sizeof(tests)/sizeof(*tests); i++) {
curr_test = &tests[i];
if (sigsetjmp(escape, 1) == 0) {
fprintf(stderr, "Test %d: ", i+1);
tests[i].test();
fprintf(stderr, " FAIL: no fault, or handler returned\n");
}
}
return 0;
}