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This set of tests covers MIPS r6 specific instructions: none/tests/mips32/MIPS32r6int none/tests/mips32/branch_pc none/tests/mips32/branches_r6 none/tests/mips32/fp_r6 none/tests/mips32/pc_instructions_r6 none/tests/mips64/MIPS64r6int none/tests/mips64/branch_pc none/tests/mips64/branches_r6 none/tests/mips64/fp_r6 none/tests/mips64/pc_instructions_r6 none/tests/mips64/r6_instructions The following tests had to be changed to be applicaple for Rev6: none/tests/libvex_test.c none/tests/mips32/LoadStore none/tests/mips32/LoadStore1 none/tests/mips32/MIPS32int none/tests/mips32/MoveIns none/tests/mips32/branches none/tests/mips32/change_fp_mode none/tests/mips32/mips32_dsp none/tests/mips32/vfp none/tests/mips64/arithmetic_instruction none/tests/mips64/branches none/tests/mips64/fpu_arithmetic none/tests/mips64/fpu_load_store none/tests/mips64/load_store none/tests/mips64/load_store_multiple none/tests/mips64/move_instructions The following tests are not applicable for Rev6: none/tests/mips32/fpu_branches none/tests/mips32/unaligned_load_store none/tests/mips64/branch_and_jump_instructions none/tests/mips64/change_fp_mode none/tests/mips64/fpu_branches none/tests/mips64/load_store_unaligned none/tests/mips64/unaligned_load none/tests/mips64/unaligned_load_store. Contributed by: Tamara Vlahovic, Aleksandar Rikalo and Aleksandra Karadzic. Related BZ issue - #387410.
106 lines
2.3 KiB
C
106 lines
2.3 KiB
C
/*
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Check that a fault signal handler gets the expected info
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*/
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#include <signal.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <fcntl.h>
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#include <setjmp.h>
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#include <unistd.h>
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struct test {
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void (*test)(void);
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int sig;
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int code;
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};
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static const struct test *curr_test;
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static jmp_buf escape;
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static int testsig(int sig, int want)
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{
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if (sig != want) {
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fprintf(stderr, " FAIL: expected signal %d, not %d\n", want, sig);
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return 0;
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}
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return 1;
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}
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static int testcode(int code, int want)
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{
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if (code != want) {
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fprintf(stderr, " FAIL: expected si_code==%d, not %d\n", want, code);
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return 0;
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}
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return 1;
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}
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static void handler(int sig, siginfo_t *si, void *uc)
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{
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int ok = 1;
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ok = ok && testsig(sig, curr_test->sig);
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ok = ok && testcode(si->si_code, curr_test->code);
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if (ok)
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fprintf(stderr, " PASS\n");
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siglongjmp(escape, ok + 1);
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}
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static void test1(void)
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{
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__asm__ volatile("li $t0, 0x80000000\n\t"
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"move $t1, $t0\n\t"
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"add $a0, $t0, $t1\n\t"
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: : : "t0", "t1", "a0", "cc", "memory");
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}
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static void test2()
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{
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__asm__ volatile("li $t0, 0x7fffffff\n\t"
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"li $a0, 0x7fff\n\t"
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"add $a0, $t0, $a0\n\t"
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: : : "t0", "a0", "cc", "memory");
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}
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static void test3(void)
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{
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__asm__ volatile("li $t0, 0xffff0000\n\t"
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"li $t1, 0x7fffffff\n\t"
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"sub $a0, $t0, $t1\n\t"
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: : : "t0", "t1", "a0", "cc", "memory");
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}
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int main()
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{
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int i;
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static const int sigs[] = { SIGFPE };
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struct sigaction sa;
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sa.sa_sigaction = handler;
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sa.sa_flags = SA_SIGINFO;
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sigfillset(&sa.sa_mask);
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for(i = 0; i < sizeof(sigs)/sizeof(*sigs); i++)
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sigaction(sigs[i], &sa, NULL);
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const struct test tests[] = {
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#define T(n, sig, code) { test##n, sig, code }
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T(1, SIGFPE, FPE_INTOVF),
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T(2, SIGFPE, FPE_INTOVF),
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T(3, SIGFPE, FPE_INTOVF),
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#undef T
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};
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for(i = 0; i < sizeof(tests)/sizeof(*tests); i++) {
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curr_test = &tests[i];
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if (sigsetjmp(escape, 1) == 0) {
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fprintf(stderr, "Test %d: ", i+1);
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tests[i].test();
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fprintf(stderr, " FAIL: no fault, or handler returned\n");
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}
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}
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return 0;
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}
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