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Author SHA1 Message Date
Julian Seward
c4fa13144d In iropt, try and call flatten_BB less. Enhance the sanity checker 
so that it does check for flatness at the relevant places.


git-svn-id: svn://svn.valgrind.org/vex/trunk@683
 2004-12-29 19:25:06 +00:00
Julian Seward
0bef1ed004 Fix nonsensical assertion. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@682
 2004-12-29 19:23:49 +00:00
Julian Seward
6a66d4e659 Oops. Track arch/subarch changes. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@681
 2004-12-29 17:48:22 +00:00
Julian Seward
42eafce9cc Sanity check re support for precise exceptions, resulting in more 
comments.  No functionality change.



git-svn-id: svn://svn.valgrind.org/vex/trunk@680
 2004-12-29 17:34:50 +00:00
Julian Seward
c48d6e72eb Looks like major changes, but in fact are just rearrangements and 
further commenting of code.  Rearrange sequence of procedures to
better reflect the flow of data through iropt.  Add documentation at
the start explaining more precisely what it does.

The only functional change is to do initial flattening even at
optimisation level 0, so we can disable most of iropt for debugging
purposes and still have a functioning Valgrind.



git-svn-id: svn://svn.valgrind.org/vex/trunk@679
 2004-12-29 17:09:11 +00:00
Julian Seward
be957c107a Add support for subarchitectures. Currently ignored. 
Supported x86 subarchitectures:
* sse0 - have fxsave/fxrstor (ie, the SSE state), but no sse insns
         That is, Pentium II and later
* sse1 - have SSE1 - Pentium III and later
* sse2 - have SSE2 - Pentium 4 and M and later



git-svn-id: svn://svn.valgrind.org/vex/trunk@678
 2004-12-21 01:23:00 +00:00
Julian Seward
60f5eced31 Duh. Un-break specialisation of x86 guest helper functions. Duh. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@677
 2004-12-20 05:45:39 +00:00
Julian Seward
a78bd5e8bb iselCondCode: better handling of a pattern frequently generated by 
memcheck.



git-svn-id: svn://svn.valgrind.org/vex/trunk@676
 2004-12-20 05:07:38 +00:00
Julian Seward
e5e6288d83 Fix autoversioning a bit more. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@675
 2004-12-20 04:42:49 +00:00
Julian Seward
0d26e5ca99 New function LibVEX_Version, returning version string automagically 
generated by 'svnversion -n .'.  Only updated when you do 'make
version'.



git-svn-id: svn://svn.valgrind.org/vex/trunk@674
 2004-12-20 04:37:50 +00:00
Julian Seward
b9a7b8a138 Move the IR tree matcher into its own module to get rid of 
duplication.



git-svn-id: svn://svn.valgrind.org/vex/trunk@673
 2004-12-20 04:12:14 +00:00
Cerion Armour-Brown
f022a59a1d Skeleton work on host-arm/isel, plus some cleaning up of hdefs 
git-svn-id: svn://svn.valgrind.org/vex/trunk@672
 2004-12-17 20:30:21 +00:00
Julian Seward
7a8ecf526c Don't squawk about kludged RDTSC, and update list of limitations. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@671
 2004-12-17 19:14:24 +00:00
Cerion Armour-Brown
8408b3c81d Cleaned up hdefs.h, fleshed out hdefs.c 
git-svn-id: svn://svn.valgrind.org/vex/trunk@670
 2004-12-16 14:06:34 +00:00
Cerion Armour-Brown
99e14dc8ee ahem - copy/paste comment error 
git-svn-id: svn://svn.valgrind.org/vex/trunk@669
 2004-12-16 12:10:59 +00:00
Cerion Armour-Brown
018026146f First stab at host arm instruction defs 
git-svn-id: svn://svn.valgrind.org/vex/trunk@668
 2004-12-16 11:50:19 +00:00
Julian Seward
9f6ba7be6f constant folder: try a bit harder to clean up memcheck's output 
git-svn-id: svn://svn.valgrind.org/vex/trunk@667
 2004-12-16 11:41:06 +00:00
Julian Seward
15a71c4eba Special case for CmpNE64(x,0), which is frequently generated when 
Memchecking floating point code.



git-svn-id: svn://svn.valgrind.org/vex/trunk@666
 2004-12-16 11:40:20 +00:00
Julian Seward
054153f439 More needles in haystacks: pmovmskb (sse): pass args to helper in the 
correct order :-)



git-svn-id: svn://svn.valgrind.org/vex/trunk@665
 2004-12-16 11:39:04 +00:00
Julian Seward
c2c2e989f8 Don't inadvertantly invert the D flag when doing pushfl. Real needle 
in a haystack job, finding this one.



git-svn-id: svn://svn.valgrind.org/vex/trunk@664
 2004-12-16 02:54:54 +00:00
Julian Seward
18ee709ba4 Implement pusha/popa. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@663
 2004-12-15 18:43:39 +00:00
Julian Seward
77788899d8 More SSE2 cases needed for gsl-1.5 regtests with icc -O -xW (SSE2). 
git-svn-id: svn://svn.valgrind.org/vex/trunk@662
 2004-12-15 17:42:58 +00:00
Cerion Armour-Brown
da7f752f5b Added DIP()s everywhere, removed all the vex_printf()s 
git-svn-id: svn://svn.valgrind.org/vex/trunk@661
 2004-12-15 13:04:06 +00:00
Julian Seward
667e964a6e x86 guest: implement SSE1 movaps G -> E (stores) 
git-svn-id: svn://svn.valgrind.org/vex/trunk@660
 2004-12-15 12:35:00 +00:00
Julian Seward
5bc8ffc865 #if 0 some unused fns in an attempt to reduce the noise level from gcc. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@659
 2004-12-15 12:21:28 +00:00
Julian Seward
c349b5c2d5 Give different emulation warnings for setting of %mxcsr.fz and %mxcsr.daz. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@658
 2004-12-15 12:13:52 +00:00
Julian Seward
1405b9db10 Fixes to get gsl-1.5 regressions to work with icc-8.0 -xK (SSE1) 
git-svn-id: svn://svn.valgrind.org/vex/trunk@657
 2004-12-15 11:57:58 +00:00
Cerion Armour-Brown
4bfc335ad9 fixed oldFlagC usage 
git-svn-id: svn://svn.valgrind.org/vex/trunk@656
 2004-12-14 12:08:09 +00:00
Julian Seward
04cb55aaee Fix push/pop/load/store of segment registers. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@655
 2004-12-14 10:00:16 +00:00
Julian Seward
b8c23f6482 * x86 host: make SSE spills/restores work 
* x86 guest: fill in some missing SSE cases


git-svn-id: svn://svn.valgrind.org/vex/trunk@654
 2004-12-14 01:16:59 +00:00
Julian Seward
d6dea91979 Improve redundant-PutI elimination a bit, so it is not completely 
fooled by some of the stupidities from guest x86 MMX code.



git-svn-id: svn://svn.valgrind.org/vex/trunk@653
 2004-12-13 18:22:48 +00:00
Julian Seward
282caf54c3 Even more folding rules. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@652
 2004-12-13 14:14:16 +00:00
Julian Seward
71d97365c4 Mechanism for dealing with failures of instruction decodes, and also 
of LibVEX-provided address translation.


git-svn-id: svn://svn.valgrind.org/vex/trunk@651
 2004-12-13 14:09:01 +00:00
Julian Seward
106fd4b1f7 x86 guest: simulate LDT/GDT enough that code using segment override 
prefixes can work.



git-svn-id: svn://svn.valgrind.org/vex/trunk@650
 2004-12-13 10:48:19 +00:00
Julian Seward
b69b1851ee Folding rule for Iop_64to32. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@649
 2004-12-13 10:47:15 +00:00
Julian Seward
8b99fb8b87 x86 guest/host: fix enough 128-bit vector stuff that memcheck works for 
SSE2.  Added a new Iop_Not128 bit primop and generate at least tolerable
SSE code for it.


git-svn-id: svn://svn.valgrind.org/vex/trunk@648
 2004-12-12 16:46:47 +00:00
Julian Seward
62b1fa8079 x86 host: Stuff in support of memchecking of 64x2 vector FP. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@647
 2004-12-10 21:45:38 +00:00
Julian Seward
e02f9b6c7a Stuff needed for Memcheck of SSE1 instructions. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@646
 2004-12-10 18:56:29 +00:00
Cerion Armour-Brown
c27dff378d Dealt with more 'unpredictables' (all of them?) 
Reworked some bad code - was assigning multiple times to an IRTemp (apparently
not allowed?!)



git-svn-id: svn://svn.valgrind.org/vex/trunk@645
 2004-12-10 15:28:43 +00:00
Julian Seward
87c3a34a1b More support for memchecking 128-bit SIMD code. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@644
 2004-12-10 14:59:57 +00:00
Cerion Armour-Brown
eff25d02ed Dealt with undefined instr's properly 
git-svn-id: svn://svn.valgrind.org/vex/trunk@643
 2004-12-10 11:43:10 +00:00
Cerion Armour-Brown
e2419dbd5d added padding to VexGuestArmState 
git-svn-id: svn://svn.valgrind.org/vex/trunk@642
 2004-12-10 10:46:16 +00:00
Cerion Armour-Brown
79595c01ac Finished dis_branch, so we get IR code for a complete bb now - yay! 
Fixed a bunch of type errors picked up by the sanity checker



git-svn-id: svn://svn.valgrind.org/vex/trunk@641
 2004-12-10 10:18:58 +00:00
Julian Seward
cca70dff12 Finish almost all SSE2 integer instructions. (!) 
git-svn-id: svn://svn.valgrind.org/vex/trunk@640
 2004-12-10 01:48:18 +00:00
Julian Seward
e5119dcd20 x86 host/guest: SSE2 integer shifts and subtracts 
git-svn-id: svn://svn.valgrind.org/vex/trunk@639
 2004-12-09 23:25:14 +00:00
Cerion Armour-Brown
09d1a87ef6 Reworked dis_loadstore_mult(): load/store multiple 
Reworked data processing instrs:
 - all dpi's are dealt with in dis_dataproc()
 - dis_shifter_op() finds the shift expression
   - directly if 'immediate', else via dis_shift(), dis_rotate
   - returns the shifter_carry_out
     (would rather not to do this... how to avoid it?!)

Added dis_loadstore_w_ub : load/store word|unsigned byte

First stab at dis_branch(), but not there yet.

Laid out disInstr to parse the entire arm instruction set.
 - was the easiest thing to do to avoid all the undefined and not-yet-implemented instructions.

Some work on flag calculations - not yet right!




git-svn-id: svn://svn.valgrind.org/vex/trunk@638
 2004-12-09 19:04:57 +00:00
Julian Seward
90969d6910 x86 guest/host: implement a whole bunch of SSE2 integer insns 
git-svn-id: svn://svn.valgrind.org/vex/trunk@637
 2004-12-09 03:44:34 +00:00
Julian Seward
f273b21842 IR level for support of 128 integer SIMD operations. Use this to do 
SSE2 integer operations (x86 guest/host).



git-svn-id: svn://svn.valgrind.org/vex/trunk@636
 2004-12-09 00:39:32 +00:00
Julian Seward
a310e39a1f Delete commented-out bits of the old UCode insn decoder. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@635
 2004-12-08 17:01:23 +00:00
Julian Seward
b4c4fd0ab9 x86 guest: finish SSE2 floating point insns. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@634
 2004-12-08 14:37:10 +00:00