The LDR (literal, int reg) testcase takes a code label and compares the
instructions around the label with known instructions in the code stream.
There were only fixed insns on either side of the checking instruction
which isn't enough given that offsets of +/-8 are used, instructions are
only 4 wide and the values loaded are 64bit. Newer gcc versions would
generate different code around the label and cause the tests to fail.
Add enough nops around the actual instruction to really give known
expected constant values to check against.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15829
FMLA 2d_2d_d[], 4s_4s_s[], 2s_2s_s[]
FMLS 2d_2d_d[], 4s_4s_s[], 2s_2s_s[]
PRFM (immediate)
Unfortunately huge diff for arm64/fp_and_simd.stdout.exp because the
new cases are not at the end, and the random data for all after it is
different. ToDo: reset RNG after each test.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@14679
