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Add test cases for PRFM (register). Pertains to #345177.

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git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15555
This commit is contained in:
Julian Seward 2015-08-16 11:46:16 +00:00
parent e4ef13d89c
commit 0f002eb44d
2 changed files with 378 additions and 0 deletions
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17
none/tests/arm64/memory.c
View File

@ -1591,6 +1591,23 @@ printf("PRFM (immediate)\n");
MEM_TEST("prfm pldl1keep, [x5, #40]", 12, -4);
MEM_TEST("prfm pstl3strm, [x5, #56]", 12, -4);
////////////////////////////////////////////////////////////////
printf("PRFM (register)\n");
MEM_TEST("prfm pldl1keep, [x5,x6]", 12, -4);
MEM_TEST("prfm pldl1strm, [x5,x6, lsl #3]", 12, -4);
MEM_TEST("prfm pldl2keep, [x5,w6,uxtw #0]", 12, 4);
MEM_TEST("prfm pldl2strm, [x5,w6,uxtw #3]", 12, 4);
MEM_TEST("prfm pldl3keep, [x5,w6,sxtw #0]", 12, 4);
MEM_TEST("prfm pldl3strm, [x5,w6,sxtw #3]", 12, -4);
MEM_TEST("prfm pstl1keep, [x5,x6]", 12, -4);
MEM_TEST("prfm pstl1strm, [x5,x6, lsl #3]", 12, -4);
MEM_TEST("prfm pstl2keep, [x5,w6,uxtw #0]", 12, 4);
MEM_TEST("prfm pstl2strm, [x5,w6,uxtw #3]", 12, 4);
MEM_TEST("prfm pstl3keep, [x5,w6,sxtw #0]", 12, 4);
MEM_TEST("prfm pstl3strm, [x5,w6,sxtw #3]", 12, -4);
} /* end of test_memory2() */
////////////////////////////////////////////////////////////////

361
none/tests/arm64/memory.stdout.exp
View File

@ -25897,3 +25897,364 @@ prfm pstl3strm, [x5, #56] with x5 = middle_of_block+12, x6=-4
0 x5 (sub, base reg)
0 x6 (sub, index reg)
PRFM (register)
prfm pldl1keep, [x5,x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
prfm pldl1strm, [x5,x6, lsl #3] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
prfm pldl2keep, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
prfm pldl2strm, [x5,w6,uxtw #3] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
prfm pldl3keep, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
prfm pldl3strm, [x5,w6,sxtw #3] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
prfm pstl1keep, [x5,x6] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
prfm pstl1strm, [x5,x6, lsl #3] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
prfm pstl2keep, [x5,w6,uxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
prfm pstl2strm, [x5,w6,uxtw #3] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
prfm pstl3keep, [x5,w6,sxtw #0] with x5 = middle_of_block+12, x6=4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)
prfm pstl3strm, [x5,w6,sxtw #3] with x5 = middle_of_block+12, x6=-4
[ 0] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 16] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 32] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 48] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 64] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 80] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[ 96] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[112] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[128] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[144] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[160] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[176] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[192] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[208] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[224] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
[240] .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. ..
0000000000000000 x13 (xor, xfer intreg #1)
0000000000000000 x23 (xor, xfer intreg #2)
0000000000000000 v17.d[0] (xor, xfer vecreg #1)
0000000000000000 v17.d[1] (xor, xfer vecreg #1)
0000000000000000 v18.d[0] (xor, xfer vecreg #2)
0000000000000000 v18.d[1] (xor, xfer vecreg #2)
0000000000000000 v19.d[0] (xor, xfer vecreg #3)
0000000000000000 v19.d[1] (xor, xfer vecreg #3)
0000000000000000 v20.d[0] (xor, xfer vecreg #3)
0000000000000000 v20.d[1] (xor, xfer vecreg #3)
0 x5 (sub, base reg)
0 x6 (sub, index reg)