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180 Commits

Author SHA1 Message Date
Julian Seward
7d761cb6a7 Fill in a huge number of amd64 floating point cases, and start to 
reinstate the old x87 instruction decoder.



git-svn-id: svn://svn.valgrind.org/vex/trunk@960
 2005-02-25 02:48:47 +00:00
Julian Seward
f47d5bde59 Add %xmm0 .. %xmm15 to the amd64 guest state. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@935
 2005-02-21 08:23:39 +00:00
Julian Seward
ba2e9245e9 Fix many amd64 guest/host cases required to run test/test-amd64.c. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@929
 2005-02-19 15:22:38 +00:00
Julian Seward
a0b00aa5a6 Fix enough stuff to get through 'hello world' on amd64. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@919
 2005-02-17 09:28:28 +00:00
Cerion Armour-Brown
2b2549ae53 spacing/comment cleanup only 
git-svn-id: svn://svn.valgrind.org/vex/trunk@909
 2005-02-16 08:54:33 +00:00
Julian Seward
7f3a53ba86 Fill in many amd64 integer cases. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@898
 2005-02-13 02:26:41 +00:00
Julian Seward
dd06920d1c Don't redefine offsetof if it is already defined. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@896
 2005-02-13 02:22:41 +00:00
Julian Seward
3a3abc6d7e Fill in many amd64 front end and back end cases. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@879
 2005-02-10 02:07:43 +00:00
Julian Seward
0437812bcc Add a new IR type -- 128-bit integral (I128) and a small collection of 
primops operating on it.  Use this to implement amd64 64x64->128
multiplies (will also be useful for divides).



git-svn-id: svn://svn.valgrind.org/vex/trunk@870
 2005-02-08 11:13:09 +00:00
Cerion Armour-Brown
9b86bf4eed This belonged with last nights changes... r868 
git-svn-id: svn://svn.valgrind.org/vex/trunk@869
 2005-02-08 11:12:02 +00:00
Julian Seward
53c35e60c2 Consistently rename all existing IROps which operate on 128-bit values 
to make it clear they operate on 128-bit *vector* values.  This is so
as to facilitate introduction of a 128-bit *scalar* type into IR
without causing confusion.



git-svn-id: svn://svn.valgrind.org/vex/trunk@867
 2005-02-07 23:47:38 +00:00
Julian Seward
2955c11bc3 More typechecker police. Hopefully this doesn't break anything. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@861
 2005-02-07 03:11:17 +00:00
Julian Seward
2c1e2edde0 Make iropt.c compile cleanly with icc in paranoid mode. Along the way, 
find and fix what looked like a bug in the folding rule for Iop_32to1.


git-svn-id: svn://svn.valgrind.org/vex/trunk@856
 2005-02-07 01:11:31 +00:00
Julian Seward
04149a3b0b Define ULong_to_Ptr / Ptr_to_ULong to help clean up 64/32 bit issues. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@853
 2005-02-07 00:00:50 +00:00
Cerion Armour-Brown
01e7da0fab Represent floats in guest_ppc32 
git-svn-id: svn://svn.valgrind.org/vex/trunk@836
 2005-02-04 16:13:58 +00:00
Cerion Armour-Brown
f479082422 Added new ir ops Iop_DivU32, Iop_DivS32 
git-svn-id: svn://svn.valgrind.org/vex/trunk@828
 2005-02-03 13:59:46 +00:00
Julian Seward
8f1c38012d Make the guest-state-size 64-bit aligned, else some assertion or other 
throws a wobbly.



git-svn-id: svn://svn.valgrind.org/vex/trunk@821
 2005-02-03 03:52:21 +00:00
Julian Seward
6a105519f5 Make the x86 back end happy to chew through IR from the ppc32 front 
end, so we can now translate integer ppc32 code into x86 (!)



git-svn-id: svn://svn.valgrind.org/vex/trunk@819
 2005-02-02 17:52:37 +00:00
Cerion Armour-Brown
42878f8918 Cleaned up clean-helper functions 
Added various vasserts around the place.



git-svn-id: svn://svn.valgrind.org/vex/trunk@812
 2005-02-01 21:29:39 +00:00
Cerion Armour-Brown
22b9405167 More ops.... 
arith, loads, stores, branch, shifts, move from/to spr



git-svn-id: svn://svn.valgrind.org/vex/trunk@804
 2005-02-01 15:56:25 +00:00
Julian Seward
2d362402b4 PowerPC-32 has at at least two variant (with and without Altivec). 
Add preliminary support for distinguishing the two.


git-svn-id: svn://svn.valgrind.org/vex/trunk@801
 2005-02-01 15:24:10 +00:00
Julian Seward
bb60571735 Typechecker (icc) police. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@800
 2005-02-01 00:37:06 +00:00
Julian Seward
cb01734976 Add two new primops needed by the amd64 front end. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@792
 2005-01-31 18:08:45 +00:00
Cerion Armour-Brown
0983b7d62e - Set up proper support for PPC32 archictecture 
- Wrote the OR ops



git-svn-id: svn://svn.valgrind.org/vex/trunk@774
 2005-01-29 12:56:15 +00:00
Cerion Armour-Brown
981df44978 Added dis_int_cmp, dis_int_logic functions 
Wrote cmp ops
Corrected size types of clean helper functions



git-svn-id: svn://svn.valgrind.org/vex/trunk@771
 2005-01-29 09:32:07 +00:00
Julian Seward
db4c74b3e1 Build fixes for icc in ultra-paranoid mode. This may not in the end 
be a good thing to do, but we'll try it for now.


git-svn-id: svn://svn.valgrind.org/vex/trunk@767
 2005-01-28 21:37:12 +00:00
Cerion Armour-Brown
defb5d0f79 - Added ops enum for xer ov,ca flag calculation 
- Filled out the helper functions for xer_ov,ca
- Added some DIPs
- Using storeBE(),loadBE instead of LE
  TODO:  Need to set up the IR for this!




git-svn-id: svn://svn.valgrind.org/vex/trunk@765
 2005-01-28 17:52:47 +00:00
Cerion Armour-Brown
704a51b82e Cleaned up and filled out: 
Added some clean helper functions to calculate CR0 and XER flags
Made a start on add and branch ops (mostly to get a feel, will prob have
to redo)



git-svn-id: svn://svn.valgrind.org/vex/trunk@755
 2005-01-27 23:02:41 +00:00
Cerion Armour-Brown
9b53aca59f changed all occurences of ppc to ppc32 (filenames and text) 
git-svn-id: svn://svn.valgrind.org/vex/trunk@747
 2005-01-25 17:21:23 +00:00
Cerion Armour-Brown
01dd7600a1 updated cpustate 
git-svn-id: svn://svn.valgrind.org/vex/trunk@745
 2005-01-25 16:56:18 +00:00
Cerion Armour-Brown
4af9a299b8 Initial file setup for guest-ppc 
git-svn-id: svn://svn.valgrind.org/vex/trunk@742
 2005-01-25 12:24:25 +00:00
Julian Seward
8b772f9c19 Fix comment. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@729
 2005-01-20 19:43:56 +00:00
Julian Seward
ab71110bd4 Proper support for translation cache management: when a translation is 
made, record precisely the areas of guest address space from which the
translation was made.  This is needed to be sure we can later discard
translations accurately.  The new info is record in a structure called
VexGuestExtents.



git-svn-id: svn://svn.valgrind.org/vex/trunk@720
 2005-01-19 11:49:45 +00:00
Julian Seward
1073520b66 Rename some functions and types in the top level interface to be more 
consistent.  Also make private some functions that Valgrind never
used.



git-svn-id: svn://svn.valgrind.org/vex/trunk@718
 2005-01-17 18:34:34 +00:00
Julian Seward
715ca1b759 Add new IR primops: Iop_CmpNEZ8x8, Iop_CmpNEZ16x4, Iop_CmpNEZ32x2 and 
isel support for them in the x86 back end.  They are used for Memcheck
annotation of 64-bit SIMD code.



git-svn-id: svn://svn.valgrind.org/vex/trunk@715
 2005-01-13 19:16:04 +00:00
Julian Seward
0d4ff22359 Fix typos in comment. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@714
 2005-01-13 16:36:42 +00:00
Julian Seward
5ca186679b Comment-only change: record code generation conventions and 
limitations for x86.




git-svn-id: svn://svn.valgrind.org/vex/trunk@713
 2005-01-13 16:33:19 +00:00
Julian Seward
5f05f2a682 On x86 host and guest, re-implement the way MMX instructions are done, 
to bring them into line with how SSE works.  Previously, MMX was done
using helper functions calls inserted by the front end.  This meant
proper MMX instrumentation was impossible (unlike SSE).  Now it works
the way all other code does: the front end does not insert calls to
helper functions, but rather builds expression trees using 64-bit
vector primops.  These are instrumented as the 128-bit vector primops
already are, and passed to the back ends.

Because emitting combined x87 and MMX code together is too complex,
the x86 back end generates calls to the same helpers as before --
except they are invisible to the front end.  And, of course, some of
those calls may now be running instrumentation operations rather than
real-value operations.



git-svn-id: svn://svn.valgrind.org/vex/trunk@712
 2005-01-13 15:06:51 +00:00
Julian Seward
4ea7cb7702 Add a trivial new IR construction: a memory fence statement. Connect 
up to x86 front and back ends.



git-svn-id: svn://svn.valgrind.org/vex/trunk@697
 2005-01-07 12:09:15 +00:00
Julian Seward
af50309b3d * x86 guest: fix bug in stmxcsr -- rounding mode field set wrongly 
* x86 guest: fix longstanding bug in fsave/frstor -- they dumped
             FP registers in physical order, instead of ST order
* x86 guest: implement fxsave


git-svn-id: svn://svn.valgrind.org/vex/trunk@694
 2005-01-06 12:36:38 +00:00
Julian Seward
c4fa13144d In iropt, try and call flatten_BB less. Enhance the sanity checker 
so that it does check for flatness at the relevant places.


git-svn-id: svn://svn.valgrind.org/vex/trunk@683
 2004-12-29 19:25:06 +00:00
Julian Seward
be957c107a Add support for subarchitectures. Currently ignored. 
Supported x86 subarchitectures:
* sse0 - have fxsave/fxrstor (ie, the SSE state), but no sse insns
         That is, Pentium II and later
* sse1 - have SSE1 - Pentium III and later
* sse2 - have SSE2 - Pentium 4 and M and later



git-svn-id: svn://svn.valgrind.org/vex/trunk@678
 2004-12-21 01:23:00 +00:00
Julian Seward
0d26e5ca99 New function LibVEX_Version, returning version string automagically 
generated by 'svnversion -n .'.  Only updated when you do 'make
version'.



git-svn-id: svn://svn.valgrind.org/vex/trunk@674
 2004-12-20 04:37:50 +00:00
Cerion Armour-Brown
f022a59a1d Skeleton work on host-arm/isel, plus some cleaning up of hdefs 
git-svn-id: svn://svn.valgrind.org/vex/trunk@672
 2004-12-17 20:30:21 +00:00
Julian Seward
c349b5c2d5 Give different emulation warnings for setting of %mxcsr.fz and %mxcsr.daz. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@658
 2004-12-15 12:13:52 +00:00
Julian Seward
71d97365c4 Mechanism for dealing with failures of instruction decodes, and also 
of LibVEX-provided address translation.


git-svn-id: svn://svn.valgrind.org/vex/trunk@651
 2004-12-13 14:09:01 +00:00
Julian Seward
106fd4b1f7 x86 guest: simulate LDT/GDT enough that code using segment override 
prefixes can work.



git-svn-id: svn://svn.valgrind.org/vex/trunk@650
 2004-12-13 10:48:19 +00:00
Julian Seward
8b99fb8b87 x86 guest/host: fix enough 128-bit vector stuff that memcheck works for 
SSE2.  Added a new Iop_Not128 bit primop and generate at least tolerable
SSE code for it.


git-svn-id: svn://svn.valgrind.org/vex/trunk@648
 2004-12-12 16:46:47 +00:00
Julian Seward
62b1fa8079 x86 host: Stuff in support of memchecking of 64x2 vector FP. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@647
 2004-12-10 21:45:38 +00:00
Julian Seward
87c3a34a1b More support for memchecking 128-bit SIMD code. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@644
 2004-12-10 14:59:57 +00:00