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Author SHA1 Message Date
Julian Seward
aa4d1e2dcc Fill in a bunch more amd64 floating point cases. Some non-trivial 
FP programs are beginning to work now.


git-svn-id: svn://svn.valgrind.org/vex/trunk@965
 2005-02-25 13:03:03 +00:00
Cerion Armour-Brown
4cb4bc2ade Re-arranged switchback::run_simulator a little, so can print translation of current bb (so if test breaks @ N, we can switchback @ N and N gets printed) 
git-svn-id: svn://svn.valgrind.org/vex/trunk@964
 2005-02-25 12:33:12 +00:00
Cerion Armour-Brown
71d16e21cf Correction to iselCC::IexTmp 
git-svn-id: svn://svn.valgrind.org/vex/trunk@963
 2005-02-25 12:08:02 +00:00
Cerion Armour-Brown
a851121cb9 Added a couple of unhandled isel instrs: 
IselStmt::Ist_Tmp::Ity_I1
iselCondCode::Iex_Tmp



git-svn-id: svn://svn.valgrind.org/vex/trunk@962
 2005-02-25 11:16:58 +00:00
Cerion Armour-Brown
4bec5bcc68 Fix to guest-ppc32 subfic 
git-svn-id: svn://svn.valgrind.org/vex/trunk@961
 2005-02-25 10:23:46 +00:00
Julian Seward
7d761cb6a7 Fill in a huge number of amd64 floating point cases, and start to 
reinstate the old x87 instruction decoder.



git-svn-id: svn://svn.valgrind.org/vex/trunk@960
 2005-02-25 02:48:47 +00:00
Cerion Armour-Brown
0ae631d5bf Fixed a backend shift bug: src/dst were swapped in emitted code. 
Also fixed an assembly printf for Set32.



git-svn-id: svn://svn.valgrind.org/vex/trunk@959
 2005-02-24 20:01:02 +00:00
Cerion Armour-Brown
b4705d1d06 Another go at fixing the rotate mask 
git-svn-id: svn://svn.valgrind.org/vex/trunk@958
 2005-02-24 16:59:17 +00:00
Cerion Armour-Brown
12d61352fc Fixed a rotate bug: IBM bit labelling got me again 
git-svn-id: svn://svn.valgrind.org/vex/trunk@957
 2005-02-24 14:57:12 +00:00
Cerion Armour-Brown
f76dd013ea Some simplifying of guest register access in toIR.c 
getReg_masked no longer calls getReg_bit for XER


git-svn-id: svn://svn.valgrind.org/vex/trunk@956
 2005-02-24 11:19:51 +00:00
Cerion Armour-Brown
a68a60fb09 Added front-end code for conditional register logic instrs 
Cleaned up the register access interface a little.



git-svn-id: svn://svn.valgrind.org/vex/trunk@955
 2005-02-23 23:13:29 +00:00
Cerion Armour-Brown
ae5c0e7a1b Just some assembly printout changes 
git-svn-id: svn://svn.valgrind.org/vex/trunk@954
 2005-02-23 18:21:31 +00:00
Julian Seward
dc97aab5f5 Cleaning up the x86 back end: get rid of instruction variants which 
the instruction selector will never generate.  I guess this
demonstrates that the majority of operations are sufficiently rare
that it is not worth going to much effort to generate good code for
them.



git-svn-id: svn://svn.valgrind.org/vex/trunk@953
 2005-02-23 13:31:25 +00:00
Julian Seward
79b57447fe Fix wrong comments (comment-only change) 
git-svn-id: svn://svn.valgrind.org/vex/trunk@952
 2005-02-23 13:28:27 +00:00
Julian Seward
eddcdc8b8a Many amd64 FP cases, including conversion to/from int (tedious stuff). 
git-svn-id: svn://svn.valgrind.org/vex/trunk@951
 2005-02-23 11:39:21 +00:00
Cerion Armour-Brown
10387d6109 Fix to run_translation: need to save LR on _caller's_ stack, and leave a hole for a callee to do the same on our stack. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@950
 2005-02-23 11:20:53 +00:00
Cerion Armour-Brown
ee3dba903c Added new instruction RdWrLR to read/write link register. 
The LR is saved in ISelEnv at the start of every bb
The LR is restored before any Goto.
This is needed because LR is a caller-saved register on PPC32, so helper functions may kill it.
(Could save/restore around each helper call, but not efficient)



git-svn-id: svn://svn.valgrind.org/vex/trunk@949
 2005-02-22 20:36:49 +00:00
Cerion Armour-Brown
9c25c18042 Coupl'a front-end load / save bugs 
git-svn-id: svn://svn.valgrind.org/vex/trunk@948
 2005-02-22 18:39:18 +00:00
Julian Seward
6361b196ae Make the switchbacker work on ppc32. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@947
 2005-02-22 15:12:00 +00:00
Cerion Armour-Brown
0f5e455967 Better assembly printouts, and added iselCondCode 1:Bit Const 
git-svn-id: svn://svn.valgrind.org/vex/trunk@946
 2005-02-22 11:16:54 +00:00
Cerion Armour-Brown
370b4d12df Gotcha! 
git-svn-id: svn://svn.valgrind.org/vex/trunk@945
 2005-02-22 11:07:35 +00:00
Cerion Armour-Brown
15076c1759 just turned off some debug printfs 
git-svn-id: svn://svn.valgrind.org/vex/trunk@944
 2005-02-21 16:44:03 +00:00
Cerion Armour-Brown
aaa0a411ba coupl'a small fixes for ppc32 
git-svn-id: svn://svn.valgrind.org/vex/trunk@943
 2005-02-21 16:30:45 +00:00
Cerion Armour-Brown
9e28880165 Fixes to host_ppc32: 
- correct assembly printouts for goto, load
 - emit_instrn
   - cmp: 7-crfD (f'ing ibm)
   - added mkLoadImm(), mkMoveReg()
   - call: 'target >> 2'
   - call,goto,cmov: fixed conditional jumps
   - goto: return correctly
   - set32: fix src,dst regs for flag rotate

 - isel:
   mk_iMOVds_RRI(): ORi, not ANDi




git-svn-id: svn://svn.valgrind.org/vex/trunk@942
 2005-02-21 15:09:19 +00:00
Cerion Armour-Brown
1a45f34a1c Corrected some mistakes in guest_ppc32 
- getReg(): bad mask
 - incorrect instr decode for addi, addic, addic.
 - compares: set bad compare flags: 8,4
 - andi: 'And', not 'Add' !
 - branches: deal properly with negative offsets/addresses




git-svn-id: svn://svn.valgrind.org/vex/trunk@941
 2005-02-21 14:07:48 +00:00
Cerion Armour-Brown
d01f09b852 finished off switchback code for ppc32 
git-svn-id: svn://svn.valgrind.org/vex/trunk@940
 2005-02-21 13:58:38 +00:00
Julian Seward
e871d908c6 More amd64 SSE/FP bits and pieces. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@939
 2005-02-21 13:58:26 +00:00
Julian Seward
74f9067905 amd64 guest/host floating point square root (easy) and comparisons 
(difficult)



git-svn-id: svn://svn.valgrind.org/vex/trunk@938
 2005-02-21 12:36:54 +00:00
Julian Seward
7462fb9f9f Make a start on floating point for AMD64 (really part of rev 936 but I 
missed it for some reason).



git-svn-id: svn://svn.valgrind.org/vex/trunk@937
 2005-02-21 08:28:46 +00:00
Julian Seward
a939d4eb7a Make a start on floating point for AMD64. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@936
 2005-02-21 08:25:55 +00:00
Julian Seward
f47d5bde59 Add %xmm0 .. %xmm15 to the amd64 guest state. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@935
 2005-02-21 08:23:39 +00:00
Julian Seward
dd14dfa2ed Add to-do note (comment-only change) 
git-svn-id: svn://svn.valgrind.org/vex/trunk@934
 2005-02-21 08:22:44 +00:00
Julian Seward
36e8605514 Folding rule for Shr64. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@933
 2005-02-21 08:20:22 +00:00
Julian Seward
02d57b0810 Fix various front-end anomalies found by the amd64 test program. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@932
 2005-02-19 22:47:41 +00:00
Julian Seward
86ededc22e Test a few more bits and pieces. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@931
 2005-02-19 22:46:11 +00:00
Julian Seward
a6e40599a3 Deal correctly with out-of-range shifts/rotates. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@930
 2005-02-19 18:12:45 +00:00
Julian Seward
ba2e9245e9 Fix many amd64 guest/host cases required to run test/test-amd64.c. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@929
 2005-02-19 15:22:38 +00:00
Julian Seward
d02735cd65 This is the same as the test-x86*.[ch] but modified for AMD64. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@928
 2005-02-19 15:20:43 +00:00
Julian Seward
6115012787 Advance ppc32 to the point where we can hope to start the program. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@927
 2005-02-17 18:07:56 +00:00
Julian Seward
a9dc13f5de Handle some ppc32 relocation types. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@926
 2005-02-17 17:42:30 +00:00
Cerion Armour-Brown
e2a16a4120 correction to branch instr for ppc hack 
git-svn-id: svn://svn.valgrind.org/vex/trunk@925
 2005-02-17 16:14:16 +00:00
Cerion Armour-Brown
bd98149439 surely it couldn't be still more ppc hacks... 
git-svn-id: svn://svn.valgrind.org/vex/trunk@924
 2005-02-17 15:54:44 +00:00
Julian Seward
96547bed9d Even more ppc32 hacks 
git-svn-id: svn://svn.valgrind.org/vex/trunk@923
 2005-02-17 15:16:08 +00:00
Julian Seward
6215a76506 More ppc hacks 
git-svn-id: svn://svn.valgrind.org/vex/trunk@922
 2005-02-17 15:02:10 +00:00
Julian Seward
348634bc14 ppc32 hacks 
git-svn-id: svn://svn.valgrind.org/vex/trunk@921
 2005-02-17 14:35:24 +00:00
Cerion Armour-Brown
7a8b4dc0f4 first ppc32 assembly attempts... 
git-svn-id: svn://svn.valgrind.org/vex/trunk@920
 2005-02-17 14:17:12 +00:00
Julian Seward
a0b00aa5a6 Fix enough stuff to get through 'hello world' on amd64. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@919
 2005-02-17 09:28:28 +00:00
Julian Seward
b060b0f143 Tidy up the constant folder and add some more rules. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@918
 2005-02-17 09:26:05 +00:00
Cerion Armour-Brown
09d35a8b99 Cleaned up a little more 
Set Pin_Goto to use GPR3 for the return register (holding next address for dispacher)




git-svn-id: svn://svn.valgrind.org/vex/trunk@917
 2005-02-16 18:08:25 +00:00
Cerion Armour-Brown
33fd9d35ce Fixed silly bug (and->add ahem.) 
Fixed up some DIPs
Took out bypasses for floating point and a bad instr.



git-svn-id: svn://svn.valgrind.org/vex/trunk@916
 2005-02-16 18:05:16 +00:00