20 Commits

Author SHA1 Message Date
Julian Seward
5e77fedd75 Fix more ppc64-linux function wrapping and symbol-table bits and pieces.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5523
2006-01-12 21:15:35 +00:00
Julian Seward
d8e230f171 Make function wrapping work on ppc32-linux.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5522
2006-01-12 14:04:46 +00:00
Julian Seward
65c73f3155 Fix up ppc64 dispatcher following the changes made by r5441.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5460
2005-12-30 04:16:37 +00:00
Julian Seward
139021b70c More dispatcher tuning for ppc32/64. Makes a big difference for
perf/tinycc.

- run_thread_for_a_while: just clear this thread's reservation when
  starting, not all of them.

- use a different fast-cache hashing function for ppc32/64 than for
  x86/amd64.  This allows the former to use all the fast-cache entries
  rather than just 1/4 of them.



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5441
2005-12-26 17:58:58 +00:00
Cerion Armour-Brown
cd0478d807 Rewrite ppc64 dispatch loop to avoid profiling overhead, as per ppc32 rewrite (r5352).
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5393
2005-12-20 20:48:50 +00:00
Julian Seward
c2a49bec4b Hold the event count in r29 rather than the count register, since the
former doesn't need to be spilled and reloaded for every bb run.



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5358
2005-12-16 01:08:22 +00:00
Julian Seward
02a7e5b5d0 Rewrite ppc32 dispatch loop to avoid profiling overhead, as per
today's x86 and amd64 rewrites.



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5352
2005-12-15 21:40:34 +00:00
Cerion Armour-Brown
b714685c63 Take ppc64 startup further along the road
- fixed launcher.c to recognise ppc32/64-linux platforms properly
 - lots of assembly fixes to handle func descriptors, toc references, 64bit regs.
 - fixed var types in vki-ppc64-linux

Now gets as far as VG_(translate), but dies from a case of invalid orig_addr.




git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5299
2005-12-06 19:07:08 +00:00
Cerion Armour-Brown
2696e0a828 Fix for a nasty bug in loading an fp reg with zero - thanks J!
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5262
2005-12-01 19:05:41 +00:00
Nicholas Nethercote
50ad55bc19 add comment from log message
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5216
2005-11-19 23:22:18 +00:00
Julian Seward
0a8b82057a Hacks needed for self-hosting on ppc32 (may be removable if stfiwx is implemented).
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5215
2005-11-19 23:08:49 +00:00
Cerion Armour-Brown
0f776af6d2 Changed altivec floating point setup to Java/IEEE mode
- Non-Java mode is the system default, but was causing some accuracy problems by rounding off intermediate denormalised results to zero.
   We now have some small errors (lowest bit only) due to using greater accuracy than the system default, but is better overall.

Also expanded dispatcher check of FPSCR to include all contol bits




git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5196
2005-11-18 20:45:18 +00:00
Cerion Armour-Brown
973949d2b3 Implemented checks for FPSCR and VSCR on leaving dispatcher
- required flags: FPSCR[RM] == 0, VSCR[NJ] == 1



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5155
2005-11-16 20:22:11 +00:00
Julian Seward
f306ed7f00 The absolute bare minimum changes needed to make it work on an
integer-only PPC processor (PPC440GX).



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5110
2005-11-13 01:59:22 +00:00
Julian Seward
77a40e2556 Hook the ppc32 stuff up to the revised CPU detection machinery, and
add a bunch of code to detect what the cpu can do at startup by
catching SIGILLs.  Shame PPC doesn't offer any sane mechanism for
finding out what instruction subsets the CPU is capable of (a la
x86/amd64 cpuid).



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5108
2005-11-13 00:30:22 +00:00
Cerion Armour-Brown
4d0a44c474 Comments from Greg Parker re ppc ABI conventions.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5077
2005-11-11 01:00:36 +00:00
Cerion Armour-Brown
3acbecc3c6 Save/Restore condition register, and VRSAVE register in core dispatch loop.
Cleaned up stack according to common abi constraints.




git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5055
2005-11-09 14:13:08 +00:00
Cerion Armour-Brown
207b24c793 store & load callee-saved floating-point and vector registers in core dispatch loop.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5047
2005-11-08 22:03:07 +00:00
Julian Seward
073c102b95 Use standard syntax for the rlwinm.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@4946
2005-10-19 10:14:19 +00:00
Nicholas Nethercote
4ef4aabbd0 Make the dispatch files platform-specific, not just arch-specific,
as requested by Greg Parker.  (The ppc32/Darwin dispatch loop is
different to the ppc32/Linux one, for example.)



git-svn-id: svn://svn.valgrind.org/valgrind/trunk@4843
2005-10-02 14:48:09 +00:00