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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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f306ed7f00
integer-only PPC processor (PPC440GX). git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5110
457 lines
13 KiB
ArmAsm
457 lines
13 KiB
ArmAsm
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##--------------------------------------------------------------------##
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##--- The core dispatch loop, for jumping to a code address. ---##
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##--- dispatch-ppc32.S ---##
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##--------------------------------------------------------------------##
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/*
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This file is part of Valgrind, a dynamic binary instrumentation
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framework.
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Copyright (C) 2005 Cerion Armour-Brown <cerion@open-works.co.uk>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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#include "pub_core_basics_asm.h"
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#include "pub_core_dispatch_asm.h"
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#include "pub_core_transtab_asm.h"
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#include "libvex_guest_offsets.h" /* for OFFSET_ppc32_CIA */
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/*------------------------------------------------------------*/
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/*--- The dispatch loop. ---*/
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/*------------------------------------------------------------*/
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/* signature: UWord VG_(run_innerloop) ( void* guest_state ) */
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.globl VG_(run_innerloop)
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VG_(run_innerloop):
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/* ----- entry point to VG_(run_innerloop) ----- */
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/* For Linux/ppc32 we need the SysV ABI, which uses
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LR->4(parent_sp), CR->anywhere.
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(The AIX ABI, used on Darwin, and maybe Linux/ppc64?,
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uses LR->8(prt_sp), CR->4(prt_sp))
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*/
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/* Save lr */
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mflr 0
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stw 0,4(1)
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/* New stack frame */
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stwu 1,-496(1) /* sp should maintain 16-byte alignment */
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/* Save callee-saved registers... */
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/* r3 is live here (guest state ptr), so use r4 */
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lis 4,VG_(machine_ppc32_has_FP)@ha
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lwz 4,VG_(machine_ppc32_has_FP)@l(4)
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cmplwi 4,0
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beq LafterFP1
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/* Floating-point reg save area : 144 bytes */
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stfd 31,488(1)
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stfd 30,480(1)
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stfd 29,472(1)
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stfd 28,464(1)
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stfd 27,456(1)
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stfd 26,448(1)
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stfd 25,440(1)
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stfd 24,432(1)
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stfd 23,424(1)
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stfd 22,416(1)
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stfd 21,408(1)
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stfd 20,400(1)
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stfd 19,392(1)
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stfd 18,384(1)
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stfd 17,376(1)
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stfd 16,368(1)
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stfd 15,360(1)
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stfd 14,352(1)
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LafterFP1:
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/* General reg save area : 72 bytes */
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stw 31,348(1)
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stw 30,344(1)
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stw 29,340(1)
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stw 28,336(1)
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stw 27,332(1)
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stw 26,328(1)
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stw 25,324(1)
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stw 24,320(1)
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stw 23,316(1)
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stw 22,312(1)
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stw 21,308(1)
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stw 20,304(1)
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stw 19,300(1)
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stw 18,296(1)
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stw 17,292(1)
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stw 16,288(1)
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stw 15,284(1)
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stw 14,280(1)
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/* Probably not necessary to save r13 (thread-specific ptr),
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as VEX stays clear of it... but what the hey. */
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stw 13,276(1)
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/* It's necessary to save/restore VRSAVE in the AIX / Darwin ABI.
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The Linux kernel might not actually use VRSAVE for its intended
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purpose, but it should be harmless to preserve anyway. */
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/* r3 is live here (guest state ptr), so use r4 */
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lis 4,VG_(machine_ppc32_has_VMX)@ha
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lwz 4,VG_(machine_ppc32_has_VMX)@l(4)
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cmplwi 4,0
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beq LafterVMX1
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/* VRSAVE save word : 32 bytes */
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mfspr 4,256 /* vrsave reg is spr number 256 */
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stw 4,244(1)
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/* Alignment padding : 4 bytes */
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/* Vector reg save area (quadword aligned) : 192 bytes */
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li 4,224
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stvx 31,4,1
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li 4,208
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stvx 30,4,1
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li 4,192
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stvx 29,4,1
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li 4,176
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stvx 28,4,1
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li 4,160
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stvx 27,4,1
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li 4,144
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stvx 26,4,1
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li 4,128
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stvx 25,4,1
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li 4,112
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stvx 24,4,1
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li 4,96
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stvx 23,4,1
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li 4,80
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stvx 22,4,1
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li 4,64
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stvx 21,4,1
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li 4,48
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stvx 20,4,1
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LafterVMX1:
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/* Save cr */
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mfcr 0
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stw 0,32(1)
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/* Local variable space... */
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/* r3 holds guest_state */
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mr 31,3
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stw 3,28(1) /* spill orig guest_state ptr */
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/* 24(sp) used later to stop ctr reg being clobbered */
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/* Linkage Area (reserved)
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20(sp) : TOC save area
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16(sp) : link editor word
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12(sp) : compiler word
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8(sp) : LR
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4(sp) : CR
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0(sp) : back-chain
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*/
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// CAB TODO: Use a caller-saved reg for orig guest_state ptr
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// - rem to set non-allocateable in isel.c
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/* hold dispatch_ctr in ctr reg */
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lis 17,VG_(dispatch_ctr)@ha
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lwz 17,VG_(dispatch_ctr)@l(17)
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mtctr 17
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/* fetch %CIA into r30 */
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lwz 30,OFFSET_ppc32_CIA(31)
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/* set host FPU control word to the default mode expected
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by VEX-generated code. See comments in libvex.h for
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more info. */
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lis 3,VG_(machine_ppc32_has_FP)@ha
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lwz 3,VG_(machine_ppc32_has_FP)@l(3)
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cmplwi 3,0
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beq LafterFP2
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fsub 3,3,3 /* generate zero */
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mtfsf 0xFF,3
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LafterFP2:
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/* set host AltiVec control word to the default mode expected
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by VEX-generated code. */
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lis 3,VG_(machine_ppc32_has_VMX)@ha
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lwz 3,VG_(machine_ppc32_has_VMX)@l(3)
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cmplwi 3,0
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beq LafterVMX2
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/* generate vector {0x0,0x0,0x0,0x00010000} */
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vspltisw 3,0x1 /* 4x 0x00000001 */
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vspltisw 4,0x0 /* generate zero */
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vsldoi 3,4,3,0x6 /* v3 = v3 >> 10 bytes */
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mtvscr 3
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LafterVMX2:
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/* make a stack frame for the code we are calling */
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stwu 1,-16(1)
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/* fall into main loop */
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/* Live regs:
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r1 (=sp)
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r30 (=CIA = jump address)
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r31 (=guest_state)
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ctr (=dispatch_ctr)
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Stack state:
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44(r1) (=orig guest_state)
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*/
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dispatch_boring:
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/* save the jump address in the guest state */
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stw 30,OFFSET_ppc32_CIA(31)
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/* Are we out of timeslice? If yes, defer to scheduler. */
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bdz counter_is_zero /* decrements ctr reg */
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/* try a fast lookup in the translation cache */
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/* r4=((r30<<2) & (VG_TT_FAST_MASK<<2)) */
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rlwinm 4,30, 2, 32-2-VG_TT_FAST_BITS, 31-2
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// CAB: use a caller-saved reg for this ?
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addis 5,4,VG_(tt_fast)@ha
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lwz 5,VG_(tt_fast)@l(5)
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lwz 6,4(5) /* big-endian, so comparing 2nd 32bit word */
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cmpw 30,6
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bne fast_lookup_failed
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/* increment bb profile counter */
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// CAB: use a caller-saved reg for this ?
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addis 6,4,VG_(tt_fastN)@ha
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lwz 7,VG_(tt_fastN)@l(6)
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lwz 8,0(7)
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addi 8,8,1
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stw 8,0(7)
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/* Found a match. Call tce[1], which is 8 bytes along, since
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each tce element is a 64-bit int. */
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addi 8,5,8
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mtlr 8
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/* stop ctr being clobbered */
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// CAB: use a caller-saved reg for this ?
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// but then (bdz) => (decr, cmp, bc)... still better than a stw?
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mfctr 9
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stw 9,40(1) /* => 40-16 = 24(1) on our parent stack */
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blrl
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/* On return from guest code:
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r3 holds destination (original) address.
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r31 may be unchanged (guest_state), or may indicate further
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details of the control transfer requested to *r3.
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If r31 is unchanged (== 44(r1)), just jump next to r3.
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Otherwise fall out, back to the scheduler, and let it
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figure out what to do next.
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*/
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/* reinstate clobbered ctr */
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lwz 9,40(1)
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mtctr 9
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mr 30,3 /* put CIA (=r3) in r30 */
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lwz 16,44(1) /* original guest_state ptr */
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cmpw 16,31
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beq dispatch_boring /* r31 unchanged... */
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mr 3,31 /* put return val (=r31) in r3 */
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b dispatch_exceptional
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/* All exits from the dispatcher go through here.
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r3 holds the return value.
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*/
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run_innerloop_exit:
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/* We're leaving. Check that nobody messed with
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%mxcsr or %fpucw. We can't mess with %eax here as it
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holds the tentative return value, but any other is OK. */
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// CAB: TODO
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//.. pushl $0
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//.. fstcw (%esp)
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//.. cmpl $0x027F, (%esp)
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//.. popl %esi /* get rid of the word without trashing %eflags */
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//.. jnz invariant_violation
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//.. pushl $0
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//.. stmxcsr (%esp)
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//.. andl $0xFFFFFFC0, (%esp) /* mask out status flags */
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//.. cmpl $0x1F80, (%esp)
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//.. popl %esi
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//.. jnz invariant_violation
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/* otherwise we're OK */
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b run_innerloop_exit_REALLY
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invariant_violation:
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li 3,VG_TRC_INVARIANT_FAILED
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b run_innerloop_exit_REALLY
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run_innerloop_exit_REALLY:
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/* r3 holds VG_TRC_* value to return */
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/* Return to parent stack */
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addi 1,1,16
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/* Write ctr to VG(dispatch_ctr) */
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mfctr 17
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lis 18,VG_(dispatch_ctr)@ha
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stw 17,VG_(dispatch_ctr)@l(18)
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/* Restore cr */
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lwz 0,32(1)
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mtcr 0
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/* Restore callee-saved registers... */
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/* must use r4 since r3 holds return value */
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lis 4,VG_(machine_ppc32_has_FP)@ha
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lwz 4,VG_(machine_ppc32_has_FP)@l(4)
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cmplwi 4,0
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beq LafterFP9
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/* Floating-point regs */
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lfd 31,488(1)
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lfd 30,480(1)
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lfd 29,472(1)
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lfd 28,464(1)
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lfd 27,456(1)
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lfd 26,448(1)
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lfd 25,440(1)
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lfd 24,432(1)
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lfd 23,424(1)
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lfd 22,416(1)
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lfd 21,408(1)
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lfd 20,400(1)
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lfd 19,392(1)
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lfd 18,384(1)
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lfd 17,376(1)
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lfd 16,368(1)
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lfd 15,360(1)
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lfd 14,352(1)
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LafterFP9:
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/* General regs */
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lwz 31,348(1)
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lwz 30,344(1)
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lwz 29,340(1)
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lwz 28,336(1)
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lwz 27,332(1)
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lwz 26,328(1)
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lwz 25,324(1)
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lwz 24,320(1)
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lwz 23,316(1)
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lwz 22,312(1)
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lwz 21,308(1)
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lwz 20,304(1)
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lwz 19,300(1)
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lwz 18,296(1)
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lwz 17,292(1)
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lwz 16,288(1)
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lwz 15,284(1)
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lwz 14,280(1)
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lwz 13,276(1)
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/* must use r4 since r3 holds return value */
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lis 4,VG_(machine_ppc32_has_VMX)@ha
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lwz 4,VG_(machine_ppc32_has_VMX)@l(4)
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cmplwi 4,0
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beq LafterVMX9
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/* VRSAVE */
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lwz 4,244(1)
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mfspr 4,256 /* VRSAVE reg is spr number 256 */
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/* Vector regs */
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li 4,224
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lvx 31,4,1
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li 4,208
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lvx 30,4,1
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li 4,192
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lvx 29,4,1
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li 4,176
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lvx 28,4,1
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li 4,160
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lvx 27,4,1
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li 4,144
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lvx 26,4,1
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li 4,128
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lvx 25,4,1
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li 4,112
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lvx 24,4,1
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li 4,96
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lvx 23,4,1
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li 4,80
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lvx 22,4,1
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li 4,64
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lvx 21,4,1
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li 4,48
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lvx 20,4,1
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LafterVMX9:
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/* reset lr & sp */
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lwz 0,500(1) /* stack_size + 4 */
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mtlr 0
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addi 1,1,496 /* stack_size */
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blr
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/* Other ways of getting out of the inner loop. Placed out-of-line to
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make it look cleaner.
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*/
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dispatch_exceptional:
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/* this is jumped to only, not fallen-through from above */
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/* save r30 in %CIA and defer to sched */
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lwz 16,44(1)
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stw 30,OFFSET_ppc32_CIA(16)
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b run_innerloop_exit
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fast_lookup_failed:
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/* %CIA is up to date here since dispatch_boring dominates */
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mfctr 17
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addi 17,17,1
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mtctr 17
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li 3,VG_TRC_INNER_FASTMISS
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b run_innerloop_exit
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counter_is_zero:
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/* %CIA is up to date here since dispatch_boring dominates */
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mfctr 17
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addi 17,17,1
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mtctr 17
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li 3,VG_TRC_INNER_COUNTERZERO
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b run_innerloop_exit
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/* Let the linker know we don't need an executable stack */
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.section .note.GNU-stack,"",@progbits
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##--------------------------------------------------------------------##
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##--- end ---##
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##--------------------------------------------------------------------##
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