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Author SHA1 Message Date
Julian Seward
2fcaf5ee4c Instruction selection/emission for Add64 and Sub64. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@716
 2005-01-15 20:43:10 +00:00
Julian Seward
715ca1b759 Add new IR primops: Iop_CmpNEZ8x8, Iop_CmpNEZ16x4, Iop_CmpNEZ32x2 and 
isel support for them in the x86 back end.  They are used for Memcheck
annotation of 64-bit SIMD code.



git-svn-id: svn://svn.valgrind.org/vex/trunk@715
 2005-01-13 19:16:04 +00:00
Julian Seward
0d4ff22359 Fix typos in comment. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@714
 2005-01-13 16:36:42 +00:00
Julian Seward
5ca186679b Comment-only change: record code generation conventions and 
limitations for x86.




git-svn-id: svn://svn.valgrind.org/vex/trunk@713
 2005-01-13 16:33:19 +00:00
Julian Seward
5f05f2a682 On x86 host and guest, re-implement the way MMX instructions are done, 
to bring them into line with how SSE works.  Previously, MMX was done
using helper functions calls inserted by the front end.  This meant
proper MMX instrumentation was impossible (unlike SSE).  Now it works
the way all other code does: the front end does not insert calls to
helper functions, but rather builds expression trees using 64-bit
vector primops.  These are instrumented as the 128-bit vector primops
already are, and passed to the back ends.

Because emitting combined x87 and MMX code together is too complex,
the x86 back end generates calls to the same helpers as before --
except they are invisible to the front end.  And, of course, some of
those calls may now be running instrumentation operations rather than
real-value operations.



git-svn-id: svn://svn.valgrind.org/vex/trunk@712
 2005-01-13 15:06:51 +00:00
Julian Seward
866f896155 Add some starting-off material for PPC32. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@711
 2005-01-12 11:25:02 +00:00
Julian Seward
8f57657569 Rename ... 
git-svn-id: svn://svn.valgrind.org/vex/trunk@710
 2005-01-12 11:12:49 +00:00
Julian Seward
cfed7ec9dd For holding 32-bit PPC originals. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@709
 2005-01-12 11:12:28 +00:00
Julian Seward
b00a46b995 This is no longer useful. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@708
 2005-01-12 11:10:40 +00:00
Julian Seward
47ecc83df5 Handle another PSLLDQ sub-case. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@707
 2005-01-11 15:03:53 +00:00
Julian Seward
6fef2ca38f Partial implementation of pslldq (SSE2). 
git-svn-id: svn://svn.valgrind.org/vex/trunk@706
 2005-01-10 20:37:31 +00:00
Julian Seward
3feb4705a7 x86 floating point accuracy improvements. The aim is to make x86 FP 
behave more consistently like an 64-bit implementation.  Mostly this
means running the host with the FPU set to 64-bit precision, not
80-bit.

Requires corresponding changes on the Valgrind side of the fence.




git-svn-id: svn://svn.valgrind.org/vex/trunk@705
 2005-01-10 16:49:19 +00:00
Julian Seward
1979c4a512 Program to check values of x87 constants. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@704
 2005-01-10 13:34:46 +00:00
Julian Seward
f9c3baa22f Program for investigating FP rounding error effects. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@703
 2005-01-08 18:26:47 +00:00
Julian Seward
dd57f1a169 Observe the memory fencing properties of CPUID. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@702
 2005-01-08 18:25:05 +00:00
Julian Seward
7064bcf7cf Fix printing of various instructions when disassembling. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@701
 2005-01-08 18:17:32 +00:00
Julian Seward
eae818a4d4 Fix some minor things to do with memory fences and the Elan3 drivers. 
Also recognise "lock addl $0,0(%esp)" as a memory fence.



git-svn-id: svn://svn.valgrind.org/vex/trunk@700
 2005-01-07 14:14:50 +00:00
Julian Seward
0c82ae8732 SSE2 fixes for mfence-ing. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@699
 2005-01-07 13:36:14 +00:00
Julian Seward
603ac0176b Machinery for investigation of LOCK prefixes. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@698
 2005-01-07 13:25:28 +00:00
Julian Seward
4ea7cb7702 Add a trivial new IR construction: a memory fence statement. Connect 
up to x86 front and back ends.



git-svn-id: svn://svn.valgrind.org/vex/trunk@697
 2005-01-07 12:09:15 +00:00
Julian Seward
bac1d406d1 Make it a more effective test. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@696
 2005-01-06 15:46:22 +00:00
Julian Seward
694bd05976 Darn; fix stupid copy-n-paste bug introduced in previous fsave/frstor 
fix.  Thanks to 'make regtest' for finding it.



git-svn-id: svn://svn.valgrind.org/vex/trunk@695
 2005-01-06 15:45:54 +00:00
Julian Seward
af50309b3d * x86 guest: fix bug in stmxcsr -- rounding mode field set wrongly 
* x86 guest: fix longstanding bug in fsave/frstor -- they dumped
             FP registers in physical order, instead of ST order
* x86 guest: implement fxsave


git-svn-id: svn://svn.valgrind.org/vex/trunk@694
 2005-01-06 12:36:38 +00:00
Julian Seward
955cb78e27 Improve these test programs. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@693
 2005-01-06 12:33:30 +00:00
Julian Seward
ad829fd971 Test program for x86 fxsave insn. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@692
 2005-01-06 10:57:16 +00:00
Julian Seward
59f3c4bc62 Add crude 'minidist' target (not yet entirely satisfactory). 
git-svn-id: svn://svn.valgrind.org/vex/trunk@691
 2005-01-05 19:11:09 +00:00
Julian Seward
830da1aa7a Remove old CPUID stuff that wasn't being used. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@690
 2005-01-05 10:38:54 +00:00
Julian Seward
0060619e2c Push subarchitecture stuff through the x86 parts. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@689
 2004-12-31 22:37:42 +00:00
Julian Seward
c0b3ddcb71 C89 police (make buildable with gcc-2.96) 
git-svn-id: svn://svn.valgrind.org/vex/trunk@688
 2004-12-31 17:22:04 +00:00
Julian Seward
094785a778 No longer try to build the attached Valgrind snapshots. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@687
 2004-12-31 17:21:28 +00:00
Julian Seward
798ee7f8ea Update the memcheck instrumenter embedded herein. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@686
 2004-12-30 02:05:34 +00:00
Julian Seward
d21448887c Rename some variables and types, to make it easier to read. No 
functionality changes.



git-svn-id: svn://svn.valgrind.org/vex/trunk@685
 2004-12-30 01:44:51 +00:00
Julian Seward
39789516fc Remove register preferencing mechanism; does not seem to help. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@684
 2004-12-30 00:14:54 +00:00
Julian Seward
c4fa13144d In iropt, try and call flatten_BB less. Enhance the sanity checker 
so that it does check for flatness at the relevant places.


git-svn-id: svn://svn.valgrind.org/vex/trunk@683
 2004-12-29 19:25:06 +00:00
Julian Seward
0bef1ed004 Fix nonsensical assertion. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@682
 2004-12-29 19:23:49 +00:00
Julian Seward
6a66d4e659 Oops. Track arch/subarch changes. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@681
 2004-12-29 17:48:22 +00:00
Julian Seward
42eafce9cc Sanity check re support for precise exceptions, resulting in more 
comments.  No functionality change.



git-svn-id: svn://svn.valgrind.org/vex/trunk@680
 2004-12-29 17:34:50 +00:00
Julian Seward
c48d6e72eb Looks like major changes, but in fact are just rearrangements and 
further commenting of code.  Rearrange sequence of procedures to
better reflect the flow of data through iropt.  Add documentation at
the start explaining more precisely what it does.

The only functional change is to do initial flattening even at
optimisation level 0, so we can disable most of iropt for debugging
purposes and still have a functioning Valgrind.



git-svn-id: svn://svn.valgrind.org/vex/trunk@679
 2004-12-29 17:09:11 +00:00
Julian Seward
be957c107a Add support for subarchitectures. Currently ignored. 
Supported x86 subarchitectures:
* sse0 - have fxsave/fxrstor (ie, the SSE state), but no sse insns
         That is, Pentium II and later
* sse1 - have SSE1 - Pentium III and later
* sse2 - have SSE2 - Pentium 4 and M and later



git-svn-id: svn://svn.valgrind.org/vex/trunk@678
 2004-12-21 01:23:00 +00:00
Julian Seward
60f5eced31 Duh. Un-break specialisation of x86 guest helper functions. Duh. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@677
 2004-12-20 05:45:39 +00:00
Julian Seward
a78bd5e8bb iselCondCode: better handling of a pattern frequently generated by 
memcheck.



git-svn-id: svn://svn.valgrind.org/vex/trunk@676
 2004-12-20 05:07:38 +00:00
Julian Seward
e5e6288d83 Fix autoversioning a bit more. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@675
 2004-12-20 04:42:49 +00:00
Julian Seward
0d26e5ca99 New function LibVEX_Version, returning version string automagically 
generated by 'svnversion -n .'.  Only updated when you do 'make
version'.



git-svn-id: svn://svn.valgrind.org/vex/trunk@674
 2004-12-20 04:37:50 +00:00
Julian Seward
b9a7b8a138 Move the IR tree matcher into its own module to get rid of 
duplication.



git-svn-id: svn://svn.valgrind.org/vex/trunk@673
 2004-12-20 04:12:14 +00:00
Cerion Armour-Brown
f022a59a1d Skeleton work on host-arm/isel, plus some cleaning up of hdefs 
git-svn-id: svn://svn.valgrind.org/vex/trunk@672
 2004-12-17 20:30:21 +00:00
Julian Seward
7a8ecf526c Don't squawk about kludged RDTSC, and update list of limitations. 
git-svn-id: svn://svn.valgrind.org/vex/trunk@671
 2004-12-17 19:14:24 +00:00
Cerion Armour-Brown
8408b3c81d Cleaned up hdefs.h, fleshed out hdefs.c 
git-svn-id: svn://svn.valgrind.org/vex/trunk@670
 2004-12-16 14:06:34 +00:00
Cerion Armour-Brown
99e14dc8ee ahem - copy/paste comment error 
git-svn-id: svn://svn.valgrind.org/vex/trunk@669
 2004-12-16 12:10:59 +00:00
Cerion Armour-Brown
018026146f First stab at host arm instruction defs 
git-svn-id: svn://svn.valgrind.org/vex/trunk@668
 2004-12-16 11:50:19 +00:00
Julian Seward
9f6ba7be6f constant folder: try a bit harder to clean up memcheck's output 
git-svn-id: svn://svn.valgrind.org/vex/trunk@667
 2004-12-16 11:41:06 +00:00