mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-12 22:24:53 +00:00
Correctly implement x86 bt/btc/bts/btr insn. Previous impl was wrong:
* Didn't handle correctly operands in memory, where arbitrary signed bit offsets are allowed. Prior impl will trash the client's stack and give the wrong answer. * Was done by a helper function and therefore could give spurious value errors. Now the address computations are done in-line. Old implementation is there, but unused and scheduled for demolition. Test case to follow. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@73
This commit is contained in:
Julian Seward
@@ -2537,6 +2537,7 @@ static Char* nameBtOp ( BtOp op )
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}
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}
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#if 0
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static
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Addr dis_bt_G_E ( UCodeBlock* cb, Int sz, Addr eip, BtOp op )
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{
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@@ -2599,6 +2600,148 @@ Addr dis_bt_G_E ( UCodeBlock* cb, Int sz, Addr eip, BtOp op )
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return eip;
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}
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#endif
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static
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Addr dis_bt_G_E ( UCodeBlock* cb, Int sz, Addr eip, BtOp op )
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{
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UInt pair;
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UChar dis_buf[50];
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UChar modrm;
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Int t_addr, t_bitno, t_mask, t_fetched, t_esp, temp, lit;
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/* 2 and 4 are actually possible. */
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vg_assert(sz == 2 || sz == 4);
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/* We only handle 4. */
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vg_assert(sz == 4);
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t_addr = t_bitno = t_mask
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= t_fetched = t_esp = temp = INVALID_TEMPREG;
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t_fetched = newTemp(cb);
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t_bitno = newTemp(cb);
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temp = newTemp(cb);
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lit = newTemp(cb);
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modrm = getUChar(eip);
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uInstr2(cb, GET, sz, ArchReg, gregOfRM(modrm), TempReg, t_bitno);
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if (epartIsReg(modrm)) {
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eip++;
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/* Get it onto the client's stack. */
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t_esp = newTemp(cb);
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t_addr = newTemp(cb);
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uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t_esp);
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uInstr2(cb, SUB, sz, Literal, 0, TempReg, t_esp);
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uLiteral(cb, sz);
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uInstr2(cb, PUT, 4, TempReg, t_esp, ArchReg, R_ESP);
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uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, temp);
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uInstr2(cb, STORE, sz, TempReg, temp, TempReg, t_esp);
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/* Make ta point at it. */
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uInstr2(cb, MOV, 4, TempReg, t_esp, TempReg, t_addr);
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/* Mask out upper bits of the shift amount, since we're doing a
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reg. */
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uInstr2(cb, MOV, 4, Literal, 0, TempReg, lit);
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uLiteral(cb, sz == 4 ? 31 : 15);
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uInstr2(cb, AND, 4, TempReg, lit, TempReg, t_bitno);
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} else {
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pair = disAMode ( cb, eip, dis?dis_buf:NULL );
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t_addr = LOW24(pair);
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eip += HI8(pair);
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}
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/* At this point: ta points to the address being operated on. If
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it was a reg, we will have pushed it onto the client's stack.
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t_bitno is the bit number, suitable masked in the case of a reg. */
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/* Now the main sequence. */
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uInstr2(cb, MOV, 4, TempReg, t_bitno, TempReg, temp);
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uInstr2(cb, SAR, 4, Literal, 0, TempReg, temp);
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uLiteral(cb, 3);
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uInstr2(cb, ADD, 4, TempReg, temp, TempReg, t_addr);
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/* ta now holds effective address */
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uInstr2(cb, MOV, 4, Literal, 0, TempReg, lit);
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uLiteral(cb, 7);
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uInstr2(cb, AND, 4, TempReg, lit, TempReg, t_bitno);
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/* bitno contains offset of bit within byte */
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if (op != BtOpNone) {
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t_mask = newTemp(cb);
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uInstr2(cb, MOV, 4, Literal, 0, TempReg, t_mask);
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uLiteral(cb, 1);
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uInstr2(cb, SHL, 4, TempReg, t_bitno, TempReg, t_mask);
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}
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/* mask is now a suitable byte mask */
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uInstr2(cb, LOAD, 1, TempReg, t_addr, TempReg, t_fetched);
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if (op != BtOpNone) {
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uInstr2(cb, MOV, 4, TempReg, t_fetched, TempReg, temp);
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switch (op) {
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case BtOpSet:
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uInstr2(cb, OR, 4, TempReg, t_mask, TempReg, temp);
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break;
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case BtOpComp:
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uInstr2(cb, XOR, 4, TempReg, t_mask, TempReg, temp);
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break;
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case BtOpReset:
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uInstr1(cb, NOT, 4, TempReg, t_mask);
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uInstr2(cb, AND, 4, TempReg, t_mask, TempReg, temp);
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break;
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default:
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VG_(panic)("dis_bt_G_E");
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}
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uInstr2(cb, STORE, 1, TempReg, temp, TempReg, t_addr);
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}
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/* Side effect done; now get selected bit into Carry flag */
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uInstr2(cb, SHR, 4, TempReg, t_bitno, TempReg, t_fetched);
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/* at bit 0 of fetched */
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uInstr2(cb, MOV, 4, Literal, 0, TempReg, lit);
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uLiteral(cb, 1);
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uInstr2(cb, AND, 4, TempReg, lit, TempReg, t_fetched);
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/* fetched is now 1 or 0 */
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/* NEG is a handy way to convert zero/nonzero into the carry
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flag. */
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uInstr1(cb, NEG, 4, TempReg, t_fetched);
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setFlagsFromUOpcode(cb, NEG);
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/* fetched is now in carry flag */
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/* Move reg operand from stack back to reg */
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if (epartIsReg(modrm)) {
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/* t_esp still points at it. */
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uInstr2(cb, LOAD, sz, TempReg, t_esp, TempReg, temp);
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uInstr2(cb, PUT, sz, TempReg, temp, ArchReg, eregOfRM(modrm));
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uInstr2(cb, ADD, sz, Literal, 0, TempReg, t_esp);
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uLiteral(cb, sz);
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uInstr2(cb, PUT, 4, TempReg, t_esp, ArchReg, R_ESP);
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}
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if (epartIsReg(modrm)) {
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if (dis)
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VG_(printf)("bt%s%c %s, %s\n",
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nameBtOp(op),
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nameISize(sz), nameIReg(sz, gregOfRM(modrm)),
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nameIReg(sz, eregOfRM(modrm)));
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} else {
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if (dis)
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VG_(printf)("bt%s%c %s, %s\n",
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nameBtOp(op),
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nameISize(sz), nameIReg(sz, gregOfRM(modrm)),
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dis_buf);
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}
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return eip;
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}
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/* Handle BSF/BSR. Only v-size seems necessary. */
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143
vg_to_ucode.c
143
vg_to_ucode.c
@@ -2537,6 +2537,7 @@ static Char* nameBtOp ( BtOp op )
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}
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}
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#if 0
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static
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Addr dis_bt_G_E ( UCodeBlock* cb, Int sz, Addr eip, BtOp op )
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{
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@@ -2599,6 +2600,148 @@ Addr dis_bt_G_E ( UCodeBlock* cb, Int sz, Addr eip, BtOp op )
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return eip;
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}
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#endif
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static
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Addr dis_bt_G_E ( UCodeBlock* cb, Int sz, Addr eip, BtOp op )
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{
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UInt pair;
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UChar dis_buf[50];
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UChar modrm;
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Int t_addr, t_bitno, t_mask, t_fetched, t_esp, temp, lit;
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/* 2 and 4 are actually possible. */
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vg_assert(sz == 2 || sz == 4);
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/* We only handle 4. */
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vg_assert(sz == 4);
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t_addr = t_bitno = t_mask
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= t_fetched = t_esp = temp = INVALID_TEMPREG;
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t_fetched = newTemp(cb);
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t_bitno = newTemp(cb);
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temp = newTemp(cb);
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lit = newTemp(cb);
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modrm = getUChar(eip);
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uInstr2(cb, GET, sz, ArchReg, gregOfRM(modrm), TempReg, t_bitno);
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if (epartIsReg(modrm)) {
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eip++;
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/* Get it onto the client's stack. */
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t_esp = newTemp(cb);
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t_addr = newTemp(cb);
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uInstr2(cb, GET, 4, ArchReg, R_ESP, TempReg, t_esp);
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uInstr2(cb, SUB, sz, Literal, 0, TempReg, t_esp);
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uLiteral(cb, sz);
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uInstr2(cb, PUT, 4, TempReg, t_esp, ArchReg, R_ESP);
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uInstr2(cb, GET, sz, ArchReg, eregOfRM(modrm), TempReg, temp);
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uInstr2(cb, STORE, sz, TempReg, temp, TempReg, t_esp);
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/* Make ta point at it. */
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uInstr2(cb, MOV, 4, TempReg, t_esp, TempReg, t_addr);
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/* Mask out upper bits of the shift amount, since we're doing a
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reg. */
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uInstr2(cb, MOV, 4, Literal, 0, TempReg, lit);
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uLiteral(cb, sz == 4 ? 31 : 15);
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uInstr2(cb, AND, 4, TempReg, lit, TempReg, t_bitno);
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} else {
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pair = disAMode ( cb, eip, dis?dis_buf:NULL );
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t_addr = LOW24(pair);
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eip += HI8(pair);
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}
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/* At this point: ta points to the address being operated on. If
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it was a reg, we will have pushed it onto the client's stack.
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t_bitno is the bit number, suitable masked in the case of a reg. */
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/* Now the main sequence. */
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uInstr2(cb, MOV, 4, TempReg, t_bitno, TempReg, temp);
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uInstr2(cb, SAR, 4, Literal, 0, TempReg, temp);
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uLiteral(cb, 3);
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uInstr2(cb, ADD, 4, TempReg, temp, TempReg, t_addr);
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/* ta now holds effective address */
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uInstr2(cb, MOV, 4, Literal, 0, TempReg, lit);
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uLiteral(cb, 7);
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uInstr2(cb, AND, 4, TempReg, lit, TempReg, t_bitno);
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/* bitno contains offset of bit within byte */
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if (op != BtOpNone) {
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t_mask = newTemp(cb);
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uInstr2(cb, MOV, 4, Literal, 0, TempReg, t_mask);
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uLiteral(cb, 1);
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uInstr2(cb, SHL, 4, TempReg, t_bitno, TempReg, t_mask);
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}
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/* mask is now a suitable byte mask */
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uInstr2(cb, LOAD, 1, TempReg, t_addr, TempReg, t_fetched);
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if (op != BtOpNone) {
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uInstr2(cb, MOV, 4, TempReg, t_fetched, TempReg, temp);
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switch (op) {
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case BtOpSet:
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uInstr2(cb, OR, 4, TempReg, t_mask, TempReg, temp);
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break;
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case BtOpComp:
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uInstr2(cb, XOR, 4, TempReg, t_mask, TempReg, temp);
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break;
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case BtOpReset:
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uInstr1(cb, NOT, 4, TempReg, t_mask);
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uInstr2(cb, AND, 4, TempReg, t_mask, TempReg, temp);
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break;
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default:
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VG_(panic)("dis_bt_G_E");
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}
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uInstr2(cb, STORE, 1, TempReg, temp, TempReg, t_addr);
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}
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/* Side effect done; now get selected bit into Carry flag */
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uInstr2(cb, SHR, 4, TempReg, t_bitno, TempReg, t_fetched);
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/* at bit 0 of fetched */
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uInstr2(cb, MOV, 4, Literal, 0, TempReg, lit);
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uLiteral(cb, 1);
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uInstr2(cb, AND, 4, TempReg, lit, TempReg, t_fetched);
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/* fetched is now 1 or 0 */
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/* NEG is a handy way to convert zero/nonzero into the carry
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flag. */
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uInstr1(cb, NEG, 4, TempReg, t_fetched);
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setFlagsFromUOpcode(cb, NEG);
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/* fetched is now in carry flag */
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/* Move reg operand from stack back to reg */
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if (epartIsReg(modrm)) {
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/* t_esp still points at it. */
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uInstr2(cb, LOAD, sz, TempReg, t_esp, TempReg, temp);
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uInstr2(cb, PUT, sz, TempReg, temp, ArchReg, eregOfRM(modrm));
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uInstr2(cb, ADD, sz, Literal, 0, TempReg, t_esp);
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uLiteral(cb, sz);
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uInstr2(cb, PUT, 4, TempReg, t_esp, ArchReg, R_ESP);
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}
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if (epartIsReg(modrm)) {
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if (dis)
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VG_(printf)("bt%s%c %s, %s\n",
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nameBtOp(op),
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nameISize(sz), nameIReg(sz, gregOfRM(modrm)),
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nameIReg(sz, eregOfRM(modrm)));
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} else {
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if (dis)
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VG_(printf)("bt%s%c %s, %s\n",
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nameBtOp(op),
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nameISize(sz), nameIReg(sz, gregOfRM(modrm)),
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dis_buf);
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}
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return eip;
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}
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/* Handle BSF/BSR. Only v-size seems necessary. */
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