mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-10 13:40:25 +00:00
Update.
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12668
This commit is contained in:
@@ -176,6 +176,14 @@ GEN_test_RandM(VCVTTSD2SI_64,
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"vcvttsd2si %%xmm8, %%r14",
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"vcvttsd2si (%%rax), %%r14")
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GEN_test_RandM(VCVTSD2SI_32,
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"vcvtsd2si %%xmm8, %%r14d",
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"vcvtsd2si (%%rax), %%r14d")
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GEN_test_RandM(VCVTSD2SI_64,
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"vcvtsd2si %%xmm8, %%r14",
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"vcvtsd2si (%%rax), %%r14")
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GEN_test_RandM(VPSHUFB_128,
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"vpshufb %%xmm6, %%xmm8, %%xmm7",
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"vpshufb (%%rax), %%xmm8, %%xmm7")
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@@ -248,6 +256,10 @@ GEN_test_RandM(VCVTTSS2SI_32,
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"vcvttss2si %%xmm8, %%r14d",
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"vcvttss2si (%%rax), %%r14d")
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GEN_test_RandM(VCVTSS2SI_32,
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"vcvtss2si %%xmm8, %%r14d",
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"vcvtss2si (%%rax), %%r14d")
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GEN_test_RandM(VMOVQ_XMMorMEM64_to_XMM,
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"vmovq %%xmm7, %%xmm8",
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"vmovq (%%rax), %%xmm8")
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@@ -303,6 +315,10 @@ GEN_test_RandM(VCVTTSS2SI_64,
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"vcvttss2si %%xmm8, %%r14",
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"vcvttss2si (%%rax), %%r14")
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GEN_test_RandM(VCVTSS2SI_64,
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"vcvtss2si %%xmm8, %%r14",
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"vcvtss2si (%%rax), %%r14")
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GEN_test_Ronly(VPMOVMSKB_128,
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"vpmovmskb %%xmm8, %%r14")
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@@ -1120,6 +1136,32 @@ GEN_test_RandM(VDPPD_128_4of4,
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"vdppd $0xF0, %%xmm6, %%xmm8, %%xmm7",
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"vdppd $0x73, (%%rax), %%xmm9, %%xmm6")
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GEN_test_RandM(VDPPS_128_1of4,
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"vdpps $0x00, %%xmm6, %%xmm8, %%xmm7",
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"vdpps $0xA5, (%%rax), %%xmm9, %%xmm6")
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GEN_test_RandM(VDPPS_128_2of4,
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"vdpps $0x5A, %%xmm6, %%xmm8, %%xmm7",
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"vdpps $0xFF, (%%rax), %%xmm9, %%xmm6")
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GEN_test_RandM(VDPPS_128_3of4,
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"vdpps $0x0F, %%xmm6, %%xmm8, %%xmm7",
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"vdpps $0x37, (%%rax), %%xmm9, %%xmm6")
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GEN_test_RandM(VDPPS_128_4of4,
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"vdpps $0xF0, %%xmm6, %%xmm8, %%xmm7",
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"vdpps $0x73, (%%rax), %%xmm9, %%xmm6")
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GEN_test_RandM(VDPPS_256_1of4,
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"vdpps $0x00, %%ymm6, %%ymm8, %%ymm7",
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"vdpps $0xA5, (%%rax), %%ymm9, %%ymm6")
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GEN_test_RandM(VDPPS_256_2of4,
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"vdpps $0x5A, %%ymm6, %%ymm8, %%ymm7",
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"vdpps $0xFF, (%%rax), %%ymm9, %%ymm6")
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GEN_test_RandM(VDPPS_256_3of4,
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"vdpps $0x0F, %%ymm6, %%ymm8, %%ymm7",
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"vdpps $0x37, (%%rax), %%ymm9, %%ymm6")
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GEN_test_RandM(VDPPS_256_4of4,
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"vdpps $0xF0, %%ymm6, %%ymm8, %%ymm7",
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"vdpps $0x73, (%%rax), %%ymm9, %%ymm6")
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GEN_test_Monly(VBROADCASTSS_256,
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"vbroadcastss (%%rax), %%ymm8")
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@@ -1700,6 +1742,61 @@ GEN_test_RandM(VBLENDVPD_256,
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"vblendvpd %%ymm9, (%%rax), %%ymm8, %%ymm7")
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GEN_test_RandM(VHADDPS_128,
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"vhaddps %%xmm6, %%xmm8, %%xmm7",
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"vhaddps (%%rax), %%xmm8, %%xmm7")
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GEN_test_RandM(VHADDPS_256,
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"vhaddps %%ymm6, %%ymm8, %%ymm7",
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"vhaddps (%%rax), %%ymm8, %%ymm7")
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GEN_test_RandM(VHADDPD_128,
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"vhaddpd %%xmm6, %%xmm8, %%xmm7",
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"vhaddpd (%%rax), %%xmm8, %%xmm7")
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GEN_test_RandM(VHADDPD_256,
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"vhaddpd %%ymm6, %%ymm8, %%ymm7",
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"vhaddpd (%%rax), %%ymm8, %%ymm7")
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GEN_test_RandM(VHSUBPS_128,
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"vhsubps %%xmm6, %%xmm8, %%xmm7",
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"vhsubps (%%rax), %%xmm8, %%xmm7")
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GEN_test_RandM(VHSUBPS_256,
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"vhsubps %%ymm6, %%ymm8, %%ymm7",
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"vhsubps (%%rax), %%ymm8, %%ymm7")
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GEN_test_RandM(VHSUBPD_128,
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"vhsubpd %%xmm6, %%xmm8, %%xmm7",
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"vhsubpd (%%rax), %%xmm8, %%xmm7")
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GEN_test_RandM(VHSUBPD_256,
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"vhsubpd %%ymm6, %%ymm8, %%ymm7",
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"vhsubpd (%%rax), %%ymm8, %%ymm7")
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GEN_test_RandM(VEXTRACTPS_0x0,
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"vextractps $0, %%xmm8, %%r14d",
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"vextractps $0, %%xmm8, (%%rax)")
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GEN_test_RandM(VEXTRACTPS_0x1,
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"vextractps $1, %%xmm8, %%r14d",
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"vextractps $1, %%xmm8, (%%rax)")
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GEN_test_RandM(VEXTRACTPS_0x2,
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"vextractps $2, %%xmm8, %%r14d",
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"vextractps $2, %%xmm8, (%%rax)")
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GEN_test_RandM(VEXTRACTPS_0x3,
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"vextractps $3, %%xmm8, %%r14d",
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"vextractps $3, %%xmm8, (%%rax)")
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GEN_test_Monly(VLDDQU_128,
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"vlddqu 1(%%rax), %%xmm8")
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GEN_test_Monly(VLDDQU_256,
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"vlddqu 1(%%rax), %%ymm8")
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/* Comment duplicated above, for convenient reference:
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Allowed operands in test insns:
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Reg form: %ymm6, %ymm7, %ymm8, %ymm9 and %r14.
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@@ -2113,5 +2210,31 @@ int main ( void )
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DO_D( VADDSUBPS_256 );
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DO_D( VADDSUBPD_128 );
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DO_D( VADDSUBPD_256 );
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DO_D( VCVTSS2SI_64 );
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DO_D( VCVTSS2SI_32 );
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DO_D( VCVTSD2SI_32 );
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DO_D( VCVTSD2SI_64 );
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DO_D( VDPPS_128_1of4 );
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DO_D( VDPPS_128_2of4 );
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DO_D( VDPPS_128_3of4 );
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DO_D( VDPPS_128_4of4 );
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DO_D( VDPPS_256_1of4 );
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DO_D( VDPPS_256_2of4 );
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DO_D( VDPPS_256_3of4 );
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DO_D( VDPPS_256_4of4 );
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DO_D( VHADDPS_128 );
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DO_D( VHADDPS_256 );
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DO_D( VHADDPD_128 );
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DO_D( VHADDPD_256 );
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DO_D( VHSUBPS_128 );
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DO_D( VHSUBPS_256 );
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DO_D( VHSUBPD_128 );
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DO_D( VHSUBPD_256 );
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DO_D( VEXTRACTPS_0x0 );
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DO_D( VEXTRACTPS_0x1 );
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DO_D( VEXTRACTPS_0x2 );
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DO_D( VEXTRACTPS_0x3 );
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DO_D( VLDDQU_128 );
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DO_D( VLDDQU_256 );
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return 0;
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}
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