mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-13 06:33:56 +00:00
Remove all references to hardwired guest state offsets. Instead,
allow definition of a struct containing the guest state (eg, VexGuestX86State in pub/libvex_guest_x86.h) and derive all offsets from that struct. git-svn-id: svn://svn.valgrind.org/vex/trunk@365
This commit is contained in:
Julian Seward
@@ -144,99 +144,6 @@ typedef
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}
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Condcode;
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/*---------------------------------------------------------*/
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/*--- Simulated state offsets ---*/
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/*---------------------------------------------------------*/
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/* Hmm, subregisters. The simulated state is stored in memory in the
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host's byte ordering, so we can't say here what the offsets of %ax,
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%al, %ah etc are since that depends on the host's byte ordering,
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which we don't know. */
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#define OFFB_EAX (0*4)
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#define OFFB_ECX (1*4)
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#define OFFB_EDX (2*4)
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#define OFFB_EBX (3*4)
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#define OFFB_ESP (4*4)
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#define OFFB_EBP (5*4)
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#define OFFB_ESI (6*4)
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#define OFFB_EDI (7*4)
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/* 3-word thunk used to calculate O S Z A C P flags. */
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#define OFFB_CC_OP (8*4)
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#define OFFB_CC_SRC (9*4)
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#define OFFB_CC_DST (10*4)
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/* The D flag is stored here, as either -1 or +1 */
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#define OFFB_DFLAG (11*4)
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/* EIP */
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#define OFFB_EIP (12*4)
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/* FPU. For now, just simulate 8 64-bit registers, their tags, and
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the reg-stack top pointer, of which only the least significant
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three bits are relevant.
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The model is:
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F0 .. F7 are the 8 registers. FTOP[2:0] contains the
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index of the current 'stack top' -- pretty meaningless, but
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still. FTOP is a 32-bit value. FTOP[31:3] can be anything
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(not guaranteed to be zero).
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When a value is pushed onto the stack, ftop is first replaced by
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(ftop-1) & 7, and then F[ftop] is assigned the value.
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When a value is popped off the stack, the value is read from
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F[ftop], and then ftop is replaced by (ftop+1) & 7.
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In general, a reference to a register ST(i) actually references
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F[ (ftop+i) & 7 ].
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FTAG0 .. FTAG0+7 are the tags. Each is a byte, zero means empty,
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non-zero means non-empty.
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The general rule appears to be that a read or modify of a register
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gets a stack underflow fault if the register is empty. A write of
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a register (only a write, not a modify) gets a stack overflow fault
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if the register is full. Note that "over" vs "under" is pretty
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meaningless since the FP stack pointer can move around arbitrarily,
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so it's really just two different kinds of exceptions:
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register-empty and register full.
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Naturally Intel (in its infinite wisdom) has seen fit to throw in
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some ad-hoc inconsistencies to the fault-generation rules of the
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above para, just to complicate everything. Known inconsistencies:
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* fxam can read a register in any state without taking an underflow
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fault.
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* fst from st(0) to st(i) does not take an overflow fault even if the
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destination is already full.
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FPUCW[15:0] is the FPU's control word. FPUCW[31:16] is unused.
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FC3210 contains the C3, C2, C1 and C0 bits in the same place they
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are in the FPU's status word. (bits 14, 10, 9, 8 respectively).
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All other bits should be zero. The relevant mask to select just
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those bits is 0x4700. To select C3, C2 and C0 only, the mask is
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0x4500.
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*/
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#define OFFB_FTOP (13*4)
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#define OFFB_F0 (14*4)
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#define OFFB_F1 (16*4)
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#define OFFB_F2 (18*4)
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#define OFFB_F3 (20*4)
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#define OFFB_F4 (22*4)
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#define OFFB_F5 (24*4)
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#define OFFB_F6 (26*4)
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#define OFFB_F7 (28*4)
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#define OFFB_FTAG0 (30*4) // up to 30*4 + 7
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#define OFFB_FPUCW (32*4)
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#define OFFB_FC3210 (33*4)
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/* Don't forget to keep this up to date. */
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#define SIZEOF_X86H_STATE (OFFB_FC3210 + 4)
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#endif /* ndef __LIBVEX_X86GUEST_DEFS_H */
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/*---------------------------------------------------------------*/
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@@ -1218,12 +1218,13 @@ typedef
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/* VISIBLE TO LIBVEX CLIENT */
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void x87_to_vex ( /*IN*/UChar* x87_state, /*OUT*/UChar* vex_state )
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void x87_to_vex ( /*IN*/UChar* x87_state,
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/*OUT*/VexGuestX86State* vex_state )
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{
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Int r;
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UInt tag;
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Double* vexRegs = (Double*)(vex_state + OFFB_F0);
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UChar* vexTags = (UChar*)(vex_state + OFFB_FTAG0);
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Double* vexRegs = (Double*)(&vex_state->guest_FPREG[0]);
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UChar* vexTags = (UChar*)(&vex_state->guest_FPTAG[0]);
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Fpu_State* x87 = (Fpu_State*)x87_state;
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UInt ftop = (x87->env[FP_ENV_STAT] >> 11) & 7;
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UInt tagw = x87->env[FP_ENV_TAG];
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@@ -1245,32 +1246,33 @@ void x87_to_vex ( /*IN*/UChar* x87_state, /*OUT*/UChar* vex_state )
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}
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/* stack pointer */
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*(UInt*)(vex_state + OFFB_FTOP) = ftop;
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vex_state->guest_FTOP = ftop;
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/* control word */
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*(UInt*)(vex_state + OFFB_FPUCW) = fpucw;
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vex_state->guest_FPUCW = fpucw;
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/* status word */
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*(UInt*)(vex_state + OFFB_FC3210) = c3210;
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vex_state->guest_FC3210 = c3210;
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}
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/* VISIBLE TO LIBVEX CLIENT */
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void vex_to_x87 ( /*IN*/UChar* vex_state, /*OUT*/UChar* x87_state )
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void vex_to_x87 ( /*IN*/VexGuestX86State* vex_state,
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/*OUT*/UChar* x87_state )
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{
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Int i, r;
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UInt tagw;
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Double* vexRegs = (Double*)(vex_state + OFFB_F0);
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UChar* vexTags = (UChar*)(vex_state + OFFB_FTAG0);
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Double* vexRegs = (Double*)(&vex_state->guest_FPREG[0]);
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UChar* vexTags = (UChar*)(&vex_state->guest_FPTAG[0]);
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Fpu_State* x87 = (Fpu_State*)x87_state;
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UInt ftop = *(UInt*)(vex_state + OFFB_FTOP);
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UInt c3210 = *(UInt*)(vex_state + OFFB_FC3210);
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UInt ftop = vex_state->guest_FTOP;
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UInt c3210 = vex_state->guest_FC3210;
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for (i = 0; i < 14; i++)
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x87->env[i] = 0;
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x87->env[1] = x87->env[3] = x87->env[5] = x87->env[13] = 0xFFFF;
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x87->env[FP_ENV_CTRL] = (UShort)( *(UInt*)(vex_state + OFFB_FPUCW) );
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x87->env[FP_ENV_CTRL] = (UShort)( vex_state->guest_FPUCW );
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x87->env[FP_ENV_STAT] = ((ftop & 7) << 11) | (c3210 & 0x4700);
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tagw = 0;
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@@ -1289,6 +1291,42 @@ void vex_to_x87 ( /*IN*/UChar* vex_state, /*OUT*/UChar* x87_state )
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}
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/* VISIBLE TO LIBVEX CLIENT */
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void eflags_to_vex ( UInt eflags_native,
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/*OUT*/VexGuestX86State* vex_state )
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{
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vex_state->guest_DFLAG
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= (eflags_native & (1<<10)) ? 0xFFFFFFFF : 0x00000001;
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/* Mask out everything except O S Z A C P. */
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eflags_native
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&= (CC_MASK_C | CC_MASK_P | CC_MASK_A
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| CC_MASK_Z | CC_MASK_S | CC_MASK_O);
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vex_state->guest_CC_OP = CC_OP_COPY;
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vex_state->guest_CC_DST = 0;
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vex_state->guest_CC_DST = eflags_native;
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}
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/* VISIBLE TO LIBVEX CLIENT */
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UInt vex_to_eflags ( /*IN*/VexGuestX86State* vex_state )
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{
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UInt eflags = calculate_eflags_all(
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vex_state->guest_CC_OP,
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vex_state->guest_CC_SRC,
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vex_state->guest_CC_DST
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);
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UInt dflag = vex_state->guest_DFLAG;
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vassert(dflag == 1 || dflag == 0xFFFFFFFF);
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if (dflag == 0xFFFFFFFF)
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eflags |= (1<<10);
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return eflags;
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}
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/*---------------------------------------------------------------*/
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/*--- end guest-x86/ghelpers.c ---*/
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/*---------------------------------------------------------------*/
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@@ -27,6 +27,7 @@
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#include "libvex_basictypes.h"
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#include "libvex_ir.h"
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#include "libvex.h"
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#include "libvex_guest_x86.h"
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#include "main/vex_util.h"
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#include "main/vex_globals.h"
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@@ -198,6 +199,24 @@ IRBB* bbToIR_X86Instr ( UChar* x86code,
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}
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/*------------------------------------------------------------*/
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/*--- Offsets of various parts of the x86 guest state. ---*/
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/*------------------------------------------------------------*/
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#define offsetof(type,memb) ((Int)&((type*)0)->memb)
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#define OFFB_FPREGS offsetof(VexGuestX86State,guest_FPREG[0])
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#define OFFB_FPTAGS offsetof(VexGuestX86State,guest_FPTAG[0])
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#define OFFB_EAX offsetof(VexGuestX86State,guest_EAX)
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#define OFFB_CC_OP offsetof(VexGuestX86State,guest_CC_OP)
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#define OFFB_CC_SRC offsetof(VexGuestX86State,guest_CC_SRC)
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#define OFFB_CC_DST offsetof(VexGuestX86State,guest_CC_DST)
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#define OFFB_DFLAG offsetof(VexGuestX86State,guest_DFLAG)
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#define OFFB_FTOP offsetof(VexGuestX86State,guest_FTOP)
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#define OFFB_FC3210 offsetof(VexGuestX86State,guest_FC3210)
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#define OFFB_FPUCW offsetof(VexGuestX86State,guest_FPUCW)
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/*------------------------------------------------------------*/
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/*--- Helper bits and pieces for deconstructing the ---*/
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/*--- x86 insn stream. ---*/
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@@ -3217,7 +3236,7 @@ static void put_ST_TAG ( Int i, IRExpr* value )
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{
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IRArray* descr;
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vassert(typeOfIRExpr(irbb->tyenv, value) == Ity_I8);
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descr = mkIRArray( OFFB_FTAG0, Ity_I8, 8 );
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descr = mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
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stmt( IRStmt_PutI( descr, get_ftop(), i, value ) );
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}
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@@ -3226,7 +3245,7 @@ static void put_ST_TAG ( Int i, IRExpr* value )
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static IRExpr* get_ST_TAG ( Int i )
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{
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IRArray* descr = mkIRArray( OFFB_FTAG0, Ity_I8, 8 );
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IRArray* descr = mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
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return IRExpr_GetI( descr, get_ftop(), i );
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}
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@@ -3241,7 +3260,7 @@ static void put_ST_UNCHECKED ( Int i, IRExpr* value )
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{
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IRArray* descr;
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vassert(typeOfIRExpr(irbb->tyenv, value) == Ity_F64);
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descr = mkIRArray( OFFB_F0, Ity_F64, 8 );
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descr = mkIRArray( OFFB_FPREGS, Ity_F64, 8 );
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stmt( IRStmt_PutI( descr, get_ftop(), i, value ) );
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/* Mark the register as in-use. */
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put_ST_TAG(i, mkU8(1));
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@@ -3269,7 +3288,7 @@ static void put_ST ( Int i, IRExpr* value )
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static IRExpr* get_ST_UNCHECKED ( Int i )
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{
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IRArray* descr = mkIRArray( OFFB_F0, Ity_F64, 8 );
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IRArray* descr = mkIRArray( OFFB_FPREGS, Ity_F64, 8 );
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return IRExpr_GetI( descr, get_ftop(), i );
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}
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@@ -11,19 +11,127 @@
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#include "libvex_basictypes.h"
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/*---------------------------------------------------------------*/
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/*--- Vex's representation of the x86 CPU state. ---*/
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/*---------------------------------------------------------------*/
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/* The integer parts should be pretty straightforward. */
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/* Hmm, subregisters. The simulated state is stored in memory in the
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host's byte ordering, so we can't say here what the offsets of %ax,
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%al, %ah etc are since that depends on the host's byte ordering,
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which we don't know. */
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/* FPU. For now, just simulate 8 64-bit registers, their tags, and
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the reg-stack top pointer, of which only the least significant
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three bits are relevant.
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The model is:
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F0 .. F7 are the 8 registers. FTOP[2:0] contains the
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index of the current 'stack top' -- pretty meaningless, but
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still. FTOP is a 32-bit value. FTOP[31:3] can be anything
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(not guaranteed to be zero).
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When a value is pushed onto the stack, ftop is first replaced by
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(ftop-1) & 7, and then F[ftop] is assigned the value.
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When a value is popped off the stack, the value is read from
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F[ftop], and then ftop is replaced by (ftop+1) & 7.
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In general, a reference to a register ST(i) actually references
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F[ (ftop+i) & 7 ].
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FTAG0 .. FTAG0+7 are the tags. Each is a byte, zero means empty,
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non-zero means non-empty.
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The general rule appears to be that a read or modify of a register
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gets a stack underflow fault if the register is empty. A write of
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a register (only a write, not a modify) gets a stack overflow fault
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if the register is full. Note that "over" vs "under" is pretty
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meaningless since the FP stack pointer can move around arbitrarily,
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so it's really just two different kinds of exceptions:
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register-empty and register full.
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Naturally Intel (in its infinite wisdom) has seen fit to throw in
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some ad-hoc inconsistencies to the fault-generation rules of the
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above para, just to complicate everything. Known inconsistencies:
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* fxam can read a register in any state without taking an underflow
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fault.
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* fst from st(0) to st(i) does not take an overflow fault even if the
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destination is already full.
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FPUCW[15:0] is the FPU's control word. FPUCW[31:16] is unused.
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FC3210 contains the C3, C2, C1 and C0 bits in the same place they
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are in the FPU's status word. (bits 14, 10, 9, 8 respectively).
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All other bits should be zero. The relevant mask to select just
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those bits is 0x4700. To select C3, C2 and C0 only, the mask is
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0x4500.
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*/
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typedef
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struct {
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UInt guest_EAX;
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UInt guest_ECX;
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UInt guest_EDX;
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UInt guest_EBX;
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UInt guest_ESP;
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UInt guest_EBP;
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UInt guest_ESI;
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UInt guest_EDI;
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/* 3-word thunk used to calculate O S Z A C P flags. */
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UInt guest_CC_OP;
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UInt guest_CC_SRC;
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UInt guest_CC_DST;
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/* The D flag is stored here, as either -1 or +1 */
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UInt guest_DFLAG;
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/* EIP */
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UInt guest_EIP;
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/* FPU */
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UInt guest_FTOP;
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ULong guest_FPREG[8];
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UChar guest_FPTAG[8];
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UInt guest_FPUCW;
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UInt guest_FC3210;
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}
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VexGuestX86State;
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/*---------------------------------------------------------------*/
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/*--- Utility functions for x86 guest stuff. ---*/
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/*---------------------------------------------------------------*/
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/* Convert a saved x87 FPU image (as created by fsave) into the
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equivalent vex representation.
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/* Convert a saved x87 FPU image (as created by fsave) and write it
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into the supplied VexGuestX86State structure. The non-FP parts of
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said structure are left unchanged.
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*/
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extern void x87_to_vex ( /*IN*/UChar* x87_state,
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/*OUT*/UChar* vex_state );
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extern
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void x87_to_vex ( /*IN*/UChar* x87_state,
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/*OUT*/VexGuestX86State* vex_state );
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/* Extract from the supplied VexGuestX86State structure, an x87 FPU
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image. */
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extern
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void vex_to_x87 ( /*IN*/VexGuestX86State* vex_state,
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/*OUT*/UChar* x87_state );
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/* Given a 32-bit word containing native x86 %eflags values, set the
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eflag-related fields in the supplied VexGuestX86State accordingly.
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All other fields are left unchanged. */
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extern
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void eflags_to_vex ( UInt eflags_native,
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/*OUT*/VexGuestX86State* vex_state );
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/* Extract from the supplied VexGuestX86State structure the
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corresponding native %eflags value. */
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extern
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UInt vex_to_eflags ( /*IN*/VexGuestX86State* vex_state );
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/* Extract from the vex representation, an x87 FPU image. */
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extern void vex_to_x87 ( /*IN*/UChar* vex_state,
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/*OUT*/UChar* x87_state );
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#endif /* ndef __LIBVEX_PUB_GUEST_X86_H */
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Reference in New Issue
Block a user