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https://github.com/Zenithsiz/dcb.git
synced 2026-02-16 22:43:58 +00:00
Fixed some wrong instructios in relation to their immediate's sign.
This commit is contained in:
@@ -262,7 +262,7 @@ impl FromRawIter for PseudoInstruction {
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Addiu { imm: imm_lo, rt, rs } if rt == prev_rt && rs == prev_rt => Self::La {
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rx: prev_rt,
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// Note: `imm_lo` is signed
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target: (u32::join(0, imm_hi).as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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target: (imm_hi.zero_extended::<u32>().as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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},
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Ori { imm: imm_lo, rt, rs } if rt == prev_rt && rs == prev_rt => Self::Li32 {
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rx: prev_rt,
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@@ -271,52 +271,52 @@ impl FromRawIter for PseudoInstruction {
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Lb { offset: imm_lo, rt, rs } if rt == prev_rt && rs == prev_rt => Self::LbImm {
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rx: prev_rt,
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offset: u32::join(imm_lo, imm_hi),
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offset: (imm_hi.zero_extended::<u32>().as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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},
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Lbu { offset: imm_lo, rt, rs } if rt == prev_rt && rs == prev_rt => Self::LbuImm {
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rx: prev_rt,
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offset: u32::join(imm_lo, imm_hi),
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offset: (imm_hi.zero_extended::<u32>().as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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},
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Lh { offset: imm_lo, rt, rs } if rt == prev_rt && rs == prev_rt => Self::LhImm {
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rx: prev_rt,
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offset: u32::join(imm_lo, imm_hi),
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offset: (imm_hi.zero_extended::<u32>().as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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},
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Lhu { offset: imm_lo, rt, rs } if rt == prev_rt && rs == prev_rt => Self::LhuImm {
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rx: prev_rt,
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offset: u32::join(imm_lo, imm_hi),
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offset: (imm_hi.zero_extended::<u32>().as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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},
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Lwl { offset: imm_lo, rt, rs } if rt == prev_rt && rs == prev_rt => Self::LwlImm {
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rx: prev_rt,
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offset: u32::join(imm_lo, imm_hi),
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offset: (imm_hi.zero_extended::<u32>().as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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},
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Lw { offset: imm_lo, rt, rs } if rt == prev_rt && rs == prev_rt => Self::LwImm {
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rx: prev_rt,
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offset: u32::join(imm_lo, imm_hi),
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offset: (imm_hi.zero_extended::<u32>().as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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},
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Lwr { offset: imm_lo, rt, rs } if rt == prev_rt && rs == prev_rt => Self::LwrImm {
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rx: prev_rt,
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offset: u32::join(imm_lo, imm_hi),
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offset: (imm_hi.zero_extended::<u32>().as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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},
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Sb { offset: imm_lo, rt, rs } if prev_rt == At && rs == At => Self::SbImm {
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rx: rt,
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offset: u32::join(imm_lo, imm_hi),
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offset: (imm_hi.zero_extended::<u32>().as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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},
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Sh { offset: imm_lo, rt, rs } if prev_rt == At && rs == At => Self::ShImm {
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rx: rt,
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offset: u32::join(imm_lo, imm_hi),
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offset: (imm_hi.zero_extended::<u32>().as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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},
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Swl { offset: imm_lo, rt, rs } if prev_rt == At && rs == At => Self::SwlImm {
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rx: rt,
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offset: u32::join(imm_lo, imm_hi),
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offset: (imm_hi.zero_extended::<u32>().as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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},
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Sw { offset: imm_lo, rt, rs } if prev_rt == At && rs == At => Self::SwImm {
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rx: rt,
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offset: u32::join(imm_lo, imm_hi),
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offset: (imm_hi.zero_extended::<u32>().as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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},
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Swr { offset: imm_lo, rt, rs } if prev_rt == At && rs == At => Self::SwrImm {
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rx: rt,
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offset: u32::join(imm_lo, imm_hi),
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offset: (imm_hi.zero_extended::<u32>().as_signed() + imm_lo.sign_extended::<i32>()).as_unsigned(),
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},
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// Since we don't use the value, reset the iterator to it's previous value.
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_ => {
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@@ -15,52 +15,52 @@ use int_conv::{SignExtended, Signed, Truncate, Truncated};
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#[allow(clippy::missing_docs_in_private_items)] // They're mostly register and immediate names.
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pub enum SimpleInstruction {
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/// Store byte
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#[display(fmt = "sb {rt}, {offset:#x}({rs})")]
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Sb { rt: Register, rs: Register, offset: u16 },
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#[display(fmt = "sb {rt}, {:#x}({rs})", "SignedHex(offset)")]
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Sb { rt: Register, rs: Register, offset: i16 },
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/// Store half-word
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#[display(fmt = "sh {rt}, {offset:#x}({rs})")]
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Sh { rt: Register, rs: Register, offset: u16 },
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#[display(fmt = "sh {rt}, {:#x}({rs})", "SignedHex(offset)")]
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Sh { rt: Register, rs: Register, offset: i16 },
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/// Store left word
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#[display(fmt = "swl {rt}, {offset:#x}({rs})")]
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Swl { rt: Register, rs: Register, offset: u16 },
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#[display(fmt = "swl {rt}, {:#x}({rs})", "SignedHex(offset)")]
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Swl { rt: Register, rs: Register, offset: i16 },
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/// Store word
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#[display(fmt = "sw {rt}, {offset:#x}({rs})")]
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Sw { rt: Register, rs: Register, offset: u16 },
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#[display(fmt = "sw {rt}, {:#x}({rs})", "SignedHex(offset)")]
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Sw { rt: Register, rs: Register, offset: i16 },
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/// Store right word
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#[display(fmt = "swr {rt}, {offset:#x}({rs})")]
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Swr { rt: Register, rs: Register, offset: u16 },
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#[display(fmt = "swr {rt}, {:#x}({rs})", "SignedHex(offset)")]
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Swr { rt: Register, rs: Register, offset: i16 },
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/// Load byte
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#[display(fmt = "lb {rt}, {offset:#x}({rs})")]
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Lb { rt: Register, rs: Register, offset: u16 },
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#[display(fmt = "lb {rt}, {:#x}({rs})", "SignedHex(offset)")]
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Lb { rt: Register, rs: Register, offset: i16 },
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/// Load byte unsigned
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#[display(fmt = "lbu {rt}, {offset:#x}({rs})")]
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Lbu { rt: Register, rs: Register, offset: u16 },
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#[display(fmt = "lbu {rt}, {:#x}({rs})", "SignedHex(offset)")]
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Lbu { rt: Register, rs: Register, offset: i16 },
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/// Load half-word
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#[display(fmt = "lh {rt}, {offset:#x}({rs})")]
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Lh { rt: Register, rs: Register, offset: u16 },
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#[display(fmt = "lh {rt}, {:#x}({rs})", "SignedHex(offset)")]
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Lh { rt: Register, rs: Register, offset: i16 },
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/// Load half-word unsigned
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#[display(fmt = "lhu {rt}, {offset:#x}({rs})")]
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Lhu { rt: Register, rs: Register, offset: u16 },
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#[display(fmt = "lhu {rt}, {:#x}({rs})", "SignedHex(offset)")]
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Lhu { rt: Register, rs: Register, offset: i16 },
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/// Load left word
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#[display(fmt = "lwl {rt}, {offset:#x}({rs})")]
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Lwl { rt: Register, rs: Register, offset: u16 },
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#[display(fmt = "lwl {rt}, {:#x}({rs})", "SignedHex(offset)")]
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Lwl { rt: Register, rs: Register, offset: i16 },
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/// Load word
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#[display(fmt = "lw {rt}, {offset:#x}({rs})")]
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Lw { rt: Register, rs: Register, offset: u16 },
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#[display(fmt = "lw {rt}, {:#x}({rs})", "SignedHex(offset)")]
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Lw { rt: Register, rs: Register, offset: i16 },
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/// Load right word
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#[display(fmt = "lwr {rt}, {offset:#x}({rs})")]
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Lwr { rt: Register, rs: Register, offset: u16 },
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#[display(fmt = "lwr {rt}, {:#x}({rs})", "SignedHex(offset)")]
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Lwr { rt: Register, rs: Register, offset: i16 },
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/// Add
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#[display(fmt = "add {rd}, {rs}, {rt}")]
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@@ -100,8 +100,8 @@ pub enum SimpleInstruction {
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Slti { rt: Register, rs: Register, imm: i16 },
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/// Set less than immediate unsigned
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#[display(fmt = "sltiu {rt}, {rs}, {imm:#x}")]
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Sltiu { rt: Register, rs: Register, imm: u16 },
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#[display(fmt = "sltiu {rt}, {rs}, {:#x}", "SignedHex(imm)")]
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Sltiu { rt: Register, rs: Register, imm: i16 },
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/// And
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#[display(fmt = "and {rd}, {rs}, {rt}")]
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@@ -356,7 +356,7 @@ impl SimpleInstruction {
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"001000_sssss_ttttt_iiiii_iiiii_iiiiii" => Addi { rt: reg(t)?, rs: reg(s)?, imm: i.truncated::<u16>().as_signed() },
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"001001_sssss_ttttt_iiiii_iiiii_iiiiii" => Addiu { rt: reg(t)?, rs: reg(s)?, imm: i.truncated::<u16>().as_signed() },
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"001010_sssss_ttttt_iiiii_iiiii_iiiiii" => Slti { rt: reg(t)?, rs: reg(s)?, imm: i.truncated::<u16>().as_signed() },
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"001011_sssss_ttttt_iiiii_iiiii_iiiiii" => Sltiu { rt: reg(t)?, rs: reg(s)?, imm: i.truncated() },
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"001011_sssss_ttttt_iiiii_iiiii_iiiiii" => Sltiu { rt: reg(t)?, rs: reg(s)?, imm: i.truncated::<u16>().as_signed() },
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"001100_sssss_ttttt_iiiii_iiiii_iiiiii" => Andi { rt: reg(t)?, rs: reg(s)?, imm: i.truncated() },
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"001101_sssss_ttttt_iiiii_iiiii_iiiiii" => Ori { rt: reg(t)?, rs: reg(s)?, imm: i.truncated() },
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"001110_sssss_ttttt_iiiii_iiiii_iiiiii" => Xori { rt: reg(t)?, rs: reg(s)?, imm: i.truncated() },
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@@ -371,19 +371,19 @@ impl SimpleInstruction {
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"0100nn_01000_00000_iiiii_iiiii_iiiiii" => BcNf { n: n.truncate(), target: i.truncate() },
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"0100nn_01000_00001_iiiii_iiiii_iiiiii" => BcNt { n: n.truncate(), target: i.truncate() },
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"100000_sssss_ttttt_iiiii_iiiii_iiiiii" => Lb { rt: reg(t)?, rs: reg(s)?, offset: i.truncated() },
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"100001_sssss_ttttt_iiiii_iiiii_iiiiii" => Lh { rt: reg(t)?, rs: reg(s)?, offset: i.truncated() },
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"100010_sssss_ttttt_iiiii_iiiii_iiiiii" => Lwl { rt: reg(t)?, rs: reg(s)?, offset: i.truncated() },
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"100011_sssss_ttttt_iiiii_iiiii_iiiiii" => Lw { rt: reg(t)?, rs: reg(s)?, offset: i.truncated() },
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"100100_sssss_ttttt_iiiii_iiiii_iiiiii" => Lbu { rt: reg(t)?, rs: reg(s)?, offset: i.truncated() },
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"100101_sssss_ttttt_iiiii_iiiii_iiiiii" => Lhu { rt: reg(t)?, rs: reg(s)?, offset: i.truncated() },
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"100110_sssss_ttttt_iiiii_iiiii_iiiiii" => Lwr { rt: reg(t)?, rs: reg(s)?, offset: i.truncated() },
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"100000_sssss_ttttt_iiiii_iiiii_iiiiii" => Lb { rt: reg(t)?, rs: reg(s)?, offset: i.truncated::<u16>().as_signed() },
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"100001_sssss_ttttt_iiiii_iiiii_iiiiii" => Lh { rt: reg(t)?, rs: reg(s)?, offset: i.truncated::<u16>().as_signed() },
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"100010_sssss_ttttt_iiiii_iiiii_iiiiii" => Lwl { rt: reg(t)?, rs: reg(s)?, offset: i.truncated::<u16>().as_signed() },
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"100011_sssss_ttttt_iiiii_iiiii_iiiiii" => Lw { rt: reg(t)?, rs: reg(s)?, offset: i.truncated::<u16>().as_signed() },
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"100100_sssss_ttttt_iiiii_iiiii_iiiiii" => Lbu { rt: reg(t)?, rs: reg(s)?, offset: i.truncated::<u16>().as_signed() },
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"100101_sssss_ttttt_iiiii_iiiii_iiiiii" => Lhu { rt: reg(t)?, rs: reg(s)?, offset: i.truncated::<u16>().as_signed() },
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"100110_sssss_ttttt_iiiii_iiiii_iiiiii" => Lwr { rt: reg(t)?, rs: reg(s)?, offset: i.truncated::<u16>().as_signed() },
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"101000_sssss_ttttt_iiiii_iiiii_iiiiii" => Sb { rt: reg(t)?, rs: reg(s)?, offset: i.truncated() },
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"101001_sssss_ttttt_iiiii_iiiii_iiiiii" => Sh { rt: reg(t)?, rs: reg(s)?, offset: i.truncated() },
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"101010_sssss_ttttt_iiiii_iiiii_iiiiii" => Swl { rt: reg(t)?, rs: reg(s)?, offset: i.truncated() },
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"101011_sssss_ttttt_iiiii_iiiii_iiiiii" => Sw { rt: reg(t)?, rs: reg(s)?, offset: i.truncated() },
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"101110_sssss_ttttt_iiiii_iiiii_iiiiii" => Swr { rt: reg(t)?, rs: reg(s)?, offset: i.truncated() },
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"101000_sssss_ttttt_iiiii_iiiii_iiiiii" => Sb { rt: reg(t)?, rs: reg(s)?, offset: i.truncated::<u16>().as_signed() },
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"101001_sssss_ttttt_iiiii_iiiii_iiiiii" => Sh { rt: reg(t)?, rs: reg(s)?, offset: i.truncated::<u16>().as_signed() },
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"101010_sssss_ttttt_iiiii_iiiii_iiiiii" => Swl { rt: reg(t)?, rs: reg(s)?, offset: i.truncated::<u16>().as_signed() },
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"101011_sssss_ttttt_iiiii_iiiii_iiiiii" => Sw { rt: reg(t)?, rs: reg(s)?, offset: i.truncated::<u16>().as_signed() },
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"101110_sssss_ttttt_iiiii_iiiii_iiiiii" => Swr { rt: reg(t)?, rs: reg(s)?, offset: i.truncated::<u16>().as_signed() },
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"1100nn_sssss_ttttt_iiiii_iiiii_iiiiii" => LwcN { n: n.truncate(), rs: reg(s)?, rt: reg(t)?, imm: i.truncate() },
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"1110nn_sssss_ttttt_iiiii_iiiii_iiiiii" => SwcN { n: n.truncate(), rs: reg(s)?, rt: reg(t)?, imm: i.truncate() },
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