mirror of
https://github.com/Zenithsiz/ftmemsim.git
synced 2026-02-14 14:48:09 +00:00
65 lines
1.7 KiB
Rust
65 lines
1.7 KiB
Rust
//! Filipe's Tiered Memory Simulator (`ftmemsim`)
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// Features
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#![feature(decl_macro, lint_reasons, get_many_mut, seek_stream_len)]
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// Modules
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mod args;
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mod classifiers;
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mod logger;
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mod pin_trace;
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mod sim;
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mod util;
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// Imports
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use {
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self::{args::Args, pin_trace::PinTrace},
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crate::{classifiers::hemem, sim::Simulator, util::FemtoDuration},
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anyhow::Context,
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clap::Parser,
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std::fs,
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};
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fn main() -> Result<(), anyhow::Error> {
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// Get arguments
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let args = Args::parse();
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logger::pre_init::debug(format!("Args: {args:?}"));
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// Initialize logging
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logger::init(args.log_file.as_deref(), args.log_file_append);
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// Read the trace file
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let pin_trace = {
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let mut pin_trace_file = fs::File::open(&args.trace_file).context("Unable to open trace file")?;
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PinTrace::from_reader(&mut pin_trace_file).context("Unable to parse pin trace")?
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};
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tracing::trace!(target: "ftmemsim::parse_pin_trace", ?pin_trace, "Parsed pin trace");
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// Run the simulator
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let mut sim = Simulator::new(0);
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let mut hemem = hemem::HeMem::new(
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hemem::Config {
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read_hot_threshold: 8,
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write_hot_threshold: 4,
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global_cooling_threshold: 18,
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},
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vec![
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hemem::Memory::new("ram", 100, hemem::memories::AccessLatencies {
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read: FemtoDuration::from_nanos_f64(1.5),
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write: FemtoDuration::from_nanos_f64(1.0),
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fault: FemtoDuration::from_nanos_f64(10.0),
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}),
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hemem::Memory::new("optane", 800, hemem::memories::AccessLatencies {
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read: FemtoDuration::from_nanos_f64(5.0),
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write: FemtoDuration::from_nanos_f64(4.0),
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fault: FemtoDuration::from_nanos_f64(50.0),
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}),
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],
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);
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sim.run(pin_trace.records.iter().copied(), &mut hemem)
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.context("Unable to run simulator")?;
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Ok(())
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}
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