mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-04 02:18:37 +00:00
ae8dfb4531
snapshots on ppc32-linux in the presence of functions subject to leaf-function optimisations. At the same time, simplify the stack unwinding logic by basically implementing it separately for each target. Having a single piece of logic for amd64 and x86 was tenable, but merging ppc32 into it is too confusing. So now there is an x86/amd64 unwinder and a ppc32 unwinder. This requires plumbing a link-register value into VG_(get_StackTrace2), and that in turn requires passing it around several other stack-trace-related functions. Hence 7 changed files. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@4464
246 lines
6.8 KiB
C
246 lines
6.8 KiB
C
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/*--------------------------------------------------------------------*/
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/*--- Machine-related stuff. m_machine.c ---*/
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/*--------------------------------------------------------------------*/
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/*
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This file is part of Valgrind, a dynamic binary instrumentation
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framework.
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Copyright (C) 2000-2005 Julian Seward
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jseward@acm.org
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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#include "pub_core_basics.h"
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#include "pub_core_threadstate.h"
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#include "pub_core_libcassert.h"
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#include "pub_core_libcbase.h"
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#include "pub_core_machine.h"
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#define INSTR_PTR(regs) ((regs).vex.VG_INSTR_PTR)
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#define STACK_PTR(regs) ((regs).vex.VG_STACK_PTR)
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#define FRAME_PTR(regs) ((regs).vex.VG_FRAME_PTR)
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Addr VG_(get_SP) ( ThreadId tid )
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{
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return STACK_PTR( VG_(threads)[tid].arch );
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}
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Addr VG_(get_IP) ( ThreadId tid )
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{
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return INSTR_PTR( VG_(threads)[tid].arch );
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}
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Addr VG_(get_FP) ( ThreadId tid )
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{
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return FRAME_PTR( VG_(threads)[tid].arch );
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}
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Addr VG_(get_LR) ( ThreadId tid )
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{
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# if defined(VGA_ppc32)
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return VG_(threads)[tid].arch.vex.guest_LR;
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# elif defined(VGA_x86) || defined(VGA_amd64)
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return 0;
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# else
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# error "Unknown arch"
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# endif
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}
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void VG_(set_SP) ( ThreadId tid, Addr sp )
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{
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STACK_PTR( VG_(threads)[tid].arch ) = sp;
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}
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void VG_(set_IP) ( ThreadId tid, Addr ip )
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{
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INSTR_PTR( VG_(threads)[tid].arch ) = ip;
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}
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void VG_(get_shadow_regs_area) ( ThreadId tid, OffT offset, SizeT size,
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UChar* area )
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{
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ThreadState* tst;
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vg_assert(VG_(is_valid_tid)(tid));
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tst = & VG_(threads)[tid];
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// Bounds check
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vg_assert(0 <= offset && offset < sizeof(VexGuestArchState));
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vg_assert(offset + size <= sizeof(VexGuestArchState));
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VG_(memcpy)( area, (void*)(((Addr)&(tst->arch.vex_shadow)) + offset), size);
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}
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void VG_(set_shadow_regs_area) ( ThreadId tid, OffT offset, SizeT size,
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const UChar* area )
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{
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ThreadState* tst;
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vg_assert(VG_(is_valid_tid)(tid));
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tst = & VG_(threads)[tid];
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// Bounds check
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vg_assert(0 <= offset && offset < sizeof(VexGuestArchState));
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vg_assert(offset + size <= sizeof(VexGuestArchState));
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VG_(memcpy)( (void*)(((Addr)(&tst->arch.vex_shadow)) + offset), area, size);
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}
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static void apply_to_GPs_of_tid(VexGuestArchState* vex, void (*f)(Addr))
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{
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#if defined(VGA_x86)
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(*f)(vex->guest_EAX);
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(*f)(vex->guest_ECX);
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(*f)(vex->guest_EDX);
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(*f)(vex->guest_EBX);
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(*f)(vex->guest_ESI);
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(*f)(vex->guest_EDI);
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(*f)(vex->guest_ESP);
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(*f)(vex->guest_EBP);
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#elif defined(VGA_amd64)
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(*f)(vex->guest_RAX);
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(*f)(vex->guest_RCX);
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(*f)(vex->guest_RDX);
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(*f)(vex->guest_RBX);
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(*f)(vex->guest_RSI);
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(*f)(vex->guest_RDI);
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(*f)(vex->guest_RSP);
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(*f)(vex->guest_RBP);
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(*f)(vex->guest_R8);
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(*f)(vex->guest_R9);
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(*f)(vex->guest_R10);
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(*f)(vex->guest_R11);
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(*f)(vex->guest_R12);
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(*f)(vex->guest_R13);
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(*f)(vex->guest_R14);
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(*f)(vex->guest_R15);
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#elif defined(VGA_ppc32)
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/* XXX ask tool about validity? */
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(*f)(vex->guest_GPR0);
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(*f)(vex->guest_GPR1);
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(*f)(vex->guest_GPR2);
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(*f)(vex->guest_GPR3);
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(*f)(vex->guest_GPR4);
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(*f)(vex->guest_GPR5);
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(*f)(vex->guest_GPR6);
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(*f)(vex->guest_GPR7);
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(*f)(vex->guest_GPR8);
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(*f)(vex->guest_GPR9);
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(*f)(vex->guest_GPR10);
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(*f)(vex->guest_GPR11);
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(*f)(vex->guest_GPR12);
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(*f)(vex->guest_GPR13);
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(*f)(vex->guest_GPR14);
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(*f)(vex->guest_GPR15);
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(*f)(vex->guest_GPR16);
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(*f)(vex->guest_GPR17);
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(*f)(vex->guest_GPR18);
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(*f)(vex->guest_GPR19);
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(*f)(vex->guest_GPR20);
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(*f)(vex->guest_GPR21);
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(*f)(vex->guest_GPR22);
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(*f)(vex->guest_GPR23);
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(*f)(vex->guest_GPR24);
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(*f)(vex->guest_GPR25);
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(*f)(vex->guest_GPR26);
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(*f)(vex->guest_GPR27);
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(*f)(vex->guest_GPR28);
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(*f)(vex->guest_GPR29);
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(*f)(vex->guest_GPR30);
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(*f)(vex->guest_GPR31);
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(*f)(vex->guest_CTR);
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(*f)(vex->guest_LR);
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#else
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# error Unknown arch
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#endif
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}
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void VG_(apply_to_GP_regs)(void (*f)(UWord))
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{
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ThreadId tid;
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for (tid = 1; tid < VG_N_THREADS; tid++) {
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if (VG_(is_valid_tid)(tid)) {
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ThreadState* tst = VG_(get_ThreadState)(tid);
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apply_to_GPs_of_tid(&(tst->arch.vex), f);
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}
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}
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}
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static ThreadId thread_stack_iter = VG_INVALID_THREADID;
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void VG_(thread_stack_reset_iter)(void)
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{
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thread_stack_iter = 1;
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}
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Bool VG_(thread_stack_next)(ThreadId* tid, Addr* stack_min, Addr* stack_max)
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{
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ThreadId i;
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for (i = thread_stack_iter; i < VG_N_THREADS; i++) {
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if (VG_(threads)[i].status != VgTs_Empty) {
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*tid = i;
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*stack_min = VG_(get_SP)(i);
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*stack_max = VG_(threads)[i].client_stack_highest_word;
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thread_stack_iter = i + 1;
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return True;
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}
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}
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return False;
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}
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//////////////////////////////////////////////////////////////////
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// Architecture specifics
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// PPC: what is the cache line size (for dcbz etc) ? This info is
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// harvested on Linux at startup from the AT_SYSINFO entries. 0 means
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// not-yet-set.
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#if defined(VGA_ppc32)
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Int VG_(cache_line_size_ppc32) = 0;
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#endif
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// X86: set to 1 if the host is able to do {ld,st}mxcsr (load/store
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// the SSE control/status register. For most modern CPUs this will be
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// 1. It is set to 1, if possible, by m_translate.getArchAndArchInfo.
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// The value is read by m_dispatch.dispatch-x86.S, which is why it
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// is an Int rather than a Bool.
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//
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// Ugly hack: this has to start as 0 and be set to 1 in the normal
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// case, rather than the other way round, because the dispatch
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// loop needs it, and it runs before the first translation is
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// made. Yet it is the act of making that first translation which
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// causes getArchAndArchInfo to set this value to its final value.
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// So it is necessary to start this value off at 0 as only that
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// guarantees that the dispatch loop will not SIGILL on its first
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// attempt.
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#if defined(VGA_x86)
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Int VG_(have_mxcsr_x86) = 0;
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#endif
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/*--------------------------------------------------------------------*/
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/*--- end ---*/
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/*--------------------------------------------------------------------*/
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