mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-09 05:10:23 +00:00
4b44d1df7d
- Moved all assembly files in coregrind/ into coregrind/x86/. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@2799
733 lines
13 KiB
ArmAsm
733 lines
13 KiB
ArmAsm
##--------------------------------------------------------------------##
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##--- Support routines for the JITter output. ---##
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##--- x86/helpers.S ---##
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##--------------------------------------------------------------------##
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/*
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This file is part of Valgrind, an extensible x86 protected-mode
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emulator for monitoring program execution on x86-Unixes.
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Copyright (C) 2000-2004 Julian Seward
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jseward@acm.org
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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#include "core_asm.h"
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/* ------------------ SIMULATED CPU HELPERS ------------------ */
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/* A stubs for a return which we want to catch: a signal return.
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returns and pthread returns. In the latter case, the thread's
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return value is in %EAX, so we pass this as the first argument
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to the request. In both cases we use the user request mechanism.
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You need to to read the definition of VALGRIND_MAGIC_SEQUENCE
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in valgrind.h to make sense of this.
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This isn't used in-place. It is copied into the client address space
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at an arbitary address. Therefore, this code must be completely
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position-independent.
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*/
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.global VG_(trampoline_code_start)
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.global VG_(trampoline_code_length)
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.global VG_(tramp_sigreturn_offset)
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.global VG_(tramp_syscall_offset)
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VG_(trampoline_code_start):
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sigreturn_start:
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subl $20, %esp # allocate arg block
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movl %esp, %edx # %edx == &_zzq_args[0]
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movl $VG_USERREQ__SIGNAL_RETURNS, 0(%edx) # request
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movl $0, 4(%edx) # arg1
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movl $0, 8(%edx) # arg2
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movl $0, 12(%edx) # arg3
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movl $0, 16(%edx) # arg4
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movl %edx, %eax
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# and now the magic sequence itself:
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roll $29, %eax
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roll $3, %eax
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rorl $27, %eax
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rorl $5, %eax
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roll $13, %eax
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roll $19, %eax
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# should never get here
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ud2
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# We can point our sysinfo stuff here
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.align 16
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syscall_start:
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int $0x80
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ret
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tramp_code_end:
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.data
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VG_(trampoline_code_length):
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.long tramp_code_end - VG_(trampoline_code_start)
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VG_(tramp_sigreturn_offset):
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.long sigreturn_start - VG_(trampoline_code_start)
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VG_(tramp_syscall_offset):
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.long syscall_start - VG_(trampoline_code_start)
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.text
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/* ------------------ REAL CPU HELPERS ------------------ */
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/* The rest of this lot run on the real CPU. */
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/* Various helper routines, for instructions which are just too
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darn tedious for the JITter to output code in-line:
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* integer division
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* integer multiplication
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* setting and getting obscure eflags
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* double-length shifts
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* eight byte compare and exchange
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All routines use a standard calling convention designed for
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calling from translations, in which the incoming args are
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underneath the return address, the callee saves _all_ registers,
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and the incoming parameters can be modified, to return results.
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*/
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/* Fetch the time-stamp-ctr reg.
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On entry:
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dummy, replaced by %EAX value
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dummy, replaced by %EDX value
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RA <- %esp
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*/
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.global VG_(helper_RDTSC)
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VG_(helper_RDTSC):
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pushl %eax
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pushl %edx
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rdtsc
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movl %edx, 12(%esp)
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movl %eax, 16(%esp)
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popl %edx
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popl %eax
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ret
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/*
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Fetch a byte/word/dword from given port
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On entry:
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size 1, 2 or 4
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port, replaced by result
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RA
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*/
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.global VG_(helper_IN)
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VG_(helper_IN):
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pushl %eax
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pushl %edx
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movl 16(%esp), %eax
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movl 12(%esp), %edx
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pushfl
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cmpl $4, %eax
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je in_dword
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cmpl $2, %eax
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je in_word
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in_byte:
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inb (%dx), %al
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jmp in_done
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in_word:
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in (%dx), %ax
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jmp in_done
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in_dword:
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inl (%dx),%eax
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in_done:
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popfl
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movl %eax,12(%esp)
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popl %edx
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popl %eax
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ret
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/*
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Write a byte/word/dword to given port
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On entry:
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size 1, 2 or 4
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port
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value
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RA
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*/
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.global VG_(helper_OUT)
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VG_(helper_OUT):
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pushl %eax
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pushl %edx
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movl 16(%esp), %edx
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movl 12(%esp), %eax
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pushfl
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cmpl $4, 20(%esp)
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je out_dword
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cmpl $2, 20(%esp)
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je out_word
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out_byte:
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outb %al,(%dx)
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jmp out_done
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out_word:
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out %ax,(%dx)
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jmp out_done
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out_dword:
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outl %eax,(%dx)
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out_done:
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popfl
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popl %edx
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popl %eax
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ret
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/* Do the CPUID instruction.
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On entry:
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dummy, replaced by %EAX value
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dummy, replaced by %EBX value
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dummy, replaced by %ECX value
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dummy, replaced by %EDX value
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RA <- %esp
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We save registers and package up the args so we can call a C helper
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for all this.
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*/
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.global VG_(helper_CPUID)
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VG_(helper_CPUID):
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pushl %ebp
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movl %esp,%ebp
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pushl %eax
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pushl %ebx
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pushl %ecx
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pushl %edx
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pushl %esi
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pushl %edi
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pushf
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lea 2*4(%ebp),%eax /* &edx */
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pushl %eax
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addl $4,%eax /* &ecx */
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pushl %eax
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addl $4,%eax /* &ebx */
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pushl %eax
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addl $4,%eax /* &eax */
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pushl %eax
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pushl (%eax) /* eax */
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call VG_(helperc_CPUID)
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addl $20,%esp
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popf
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popl %edi
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popl %esi
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popl %edx
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popl %ecx
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popl %ebx
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popl %eax
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popl %ebp
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ret
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/* Fetch the FPU status register.
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On entry:
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dummy, replaced by result
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RA <- %esp
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*/
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.global VG_(helper_fstsw_AX)
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VG_(helper_fstsw_AX):
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pushl %eax
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pushl %esi
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movl VGOFF_(m_ssestate), %esi
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pushfl
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cmpb $0, VG_(have_ssestate)
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jz aa1nosse
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fxrstor (%ebp, %esi, 4)
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jmp aa1merge
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aa1nosse:
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frstor (%ebp, %esi, 4)
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aa1merge:
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popfl
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fstsw %ax
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popl %esi
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movw %ax, 8(%esp)
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popl %eax
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ret
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/* Copy %ah into %eflags.
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On entry:
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value of %eax
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RA <- %esp
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*/
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.global VG_(helper_SAHF)
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VG_(helper_SAHF):
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pushl %eax
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movl 8(%esp), %eax
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sahf
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popl %eax
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ret
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/* Copy %eflags into %ah.
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On entry:
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value of %eax
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RA <- %esp
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*/
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.global VG_(helper_LAHF)
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VG_(helper_LAHF):
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pushl %eax
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movl 8(%esp), %eax
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lahf
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movl %eax, 8(%esp)
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popl %eax
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ret
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/* Do %al = DAS(%al). Note that the passed param has %AL as the least
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significant 8 bits, since it was generated with GETB %AL,
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some-temp. Fortunately %al is the least significant 8 bits of
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%eax anyway, which is why it's safe to work with %eax as a
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whole.
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On entry:
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value of %eax
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RA <- %esp
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*/
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.global VG_(helper_DAS)
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VG_(helper_DAS):
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pushl %eax
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movl 8(%esp), %eax
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das
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movl %eax, 8(%esp)
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popl %eax
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ret
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/* Similarly, do %al = DAA(%al). */
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.global VG_(helper_DAA)
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VG_(helper_DAA):
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pushl %eax
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movl 8(%esp), %eax
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daa
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movl %eax, 8(%esp)
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popl %eax
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ret
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/* Similarly, do %ax = AAS(%ax). */
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.global VG_(helper_AAS)
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VG_(helper_AAS):
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pushl %eax
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movl 8(%esp), %eax
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aas
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movl %eax, 8(%esp)
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popl %eax
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ret
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/* Similarly, do %ax = AAA(%ax). */
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.global VG_(helper_AAA)
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VG_(helper_AAA):
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pushl %eax
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movl 8(%esp), %eax
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aaa
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movl %eax, 8(%esp)
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popl %eax
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ret
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/* Similarly, do %ax = AAD(%ax). */
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.global VG_(helper_AAD)
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VG_(helper_AAD):
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pushl %eax
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movl 8(%esp), %eax
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aad
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movl %eax, 8(%esp)
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popl %eax
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ret
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/* Similarly, do %ax = AAM(%ax). */
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.global VG_(helper_AAM)
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VG_(helper_AAM):
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pushl %eax
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movl 8(%esp), %eax
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aam
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movl %eax, 8(%esp)
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popl %eax
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ret
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/* Bit scan forwards/reverse. Sets flags (??).
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On entry:
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value, replaced by result
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RA <- %esp
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*/
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.global VG_(helper_bsrw)
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VG_(helper_bsrw):
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pushl %eax
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movw 12(%esp), %ax
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bsrw 8(%esp), %ax
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movw %ax, 12(%esp)
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popl %eax
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ret
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.global VG_(helper_bsrl)
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VG_(helper_bsrl):
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pushl %eax
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movl 12(%esp), %eax
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bsrl 8(%esp), %eax
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movl %eax, 12(%esp)
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popl %eax
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ret
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.global VG_(helper_bsfw)
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VG_(helper_bsfw):
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pushl %eax
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movw 12(%esp), %ax
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bsfw 8(%esp), %ax
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movw %ax, 12(%esp)
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popl %eax
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ret
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.global VG_(helper_bsfl)
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VG_(helper_bsfl):
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pushl %eax
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movl 12(%esp), %eax
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bsfl 8(%esp), %eax
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movl %eax, 12(%esp)
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popl %eax
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ret
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/* 32-bit double-length shift left/right.
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On entry:
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amount
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src
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dst
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RA <- %esp
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*/
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.global VG_(helper_shldl)
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VG_(helper_shldl):
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pushl %eax
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pushl %ebx
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pushl %ecx
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movb 24(%esp), %cl
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movl 20(%esp), %ebx
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movl 16(%esp), %eax
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shldl %cl, %ebx, %eax
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movl %eax, 16(%esp)
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popl %ecx
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popl %ebx
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popl %eax
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ret
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.global VG_(helper_shldw)
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VG_(helper_shldw):
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pushl %eax
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pushl %ebx
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pushl %ecx
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movb 24(%esp), %cl
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movw 20(%esp), %bx
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movw 16(%esp), %ax
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shldw %cl, %bx, %ax
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movw %ax, 16(%esp)
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popl %ecx
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popl %ebx
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popl %eax
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ret
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.global VG_(helper_shrdl)
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VG_(helper_shrdl):
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pushl %eax
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pushl %ebx
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pushl %ecx
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movb 24(%esp), %cl
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movl 20(%esp), %ebx
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movl 16(%esp), %eax
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shrdl %cl, %ebx, %eax
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movl %eax, 16(%esp)
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popl %ecx
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popl %ebx
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popl %eax
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ret
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.global VG_(helper_shrdw)
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VG_(helper_shrdw):
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pushl %eax
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pushl %ebx
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pushl %ecx
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movb 24(%esp), %cl
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movw 20(%esp), %bx
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movw 16(%esp), %ax
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shrdw %cl, %bx, %ax
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movw %ax, 16(%esp)
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popl %ecx
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popl %ebx
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popl %eax
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ret
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/* Get the direction flag, and return either 1 or -1. */
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.global VG_(helper_get_dirflag)
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VG_(helper_get_dirflag):
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pushl %eax
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movl VGOFF_(m_dflag), %eax
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movl (%ebp, %eax, 4), %eax
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movl %eax, 8(%esp)
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popl %eax
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ret
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/* Clear/set the direction flag. */
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.global VG_(helper_CLD)
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VG_(helper_CLD):
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pushl %eax
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movl VGOFF_(m_dflag), %eax
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movl $1, (%ebp, %eax, 4)
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popl %eax
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ret
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.global VG_(helper_STD)
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VG_(helper_STD):
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pushl %eax
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movl VGOFF_(m_dflag), %eax
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movl $-1, (%ebp, %eax, 4)
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popl %eax
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ret
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/* Clear/set/complement the carry flag. */
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.global VG_(helper_CLC)
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VG_(helper_CLC):
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clc
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ret
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.global VG_(helper_STC)
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VG_(helper_STC):
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stc
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ret
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.global VG_(helper_CMC)
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VG_(helper_CMC):
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cmc
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ret
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|
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|
/* Signed 32-to-64 multiply. */
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|
.globl VG_(helper_imul_32_64)
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VG_(helper_imul_32_64):
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pushl %eax
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pushl %edx
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movl 16(%esp), %eax
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imull 12(%esp)
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movl %eax, 16(%esp)
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movl %edx, 12(%esp)
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popl %edx
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popl %eax
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ret
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|
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|
/* Signed 16-to-32 multiply. */
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|
.globl VG_(helper_imul_16_32)
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|
VG_(helper_imul_16_32):
|
|
pushl %eax
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pushl %edx
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movw 16(%esp), %ax
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imulw 12(%esp)
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|
movw %ax, 16(%esp)
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movw %dx, 12(%esp)
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popl %edx
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popl %eax
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ret
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|
/* Signed 8-to-16 multiply. */
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|
.globl VG_(helper_imul_8_16)
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VG_(helper_imul_8_16):
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pushl %eax
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pushl %edx
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movb 16(%esp), %al
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imulb 12(%esp)
|
|
movw %ax, 16(%esp)
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popl %edx
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popl %eax
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ret
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|
|
/* Unsigned 32-to-64 multiply. */
|
|
.globl VG_(helper_mul_32_64)
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|
VG_(helper_mul_32_64):
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pushl %eax
|
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pushl %edx
|
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movl 16(%esp), %eax
|
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mull 12(%esp)
|
|
movl %eax, 16(%esp)
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|
movl %edx, 12(%esp)
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|
popl %edx
|
|
popl %eax
|
|
ret
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|
|
/* Unsigned 16-to-32 multiply. */
|
|
.globl VG_(helper_mul_16_32)
|
|
VG_(helper_mul_16_32):
|
|
pushl %eax
|
|
pushl %edx
|
|
movw 16(%esp), %ax
|
|
mulw 12(%esp)
|
|
movw %ax, 16(%esp)
|
|
movw %dx, 12(%esp)
|
|
popl %edx
|
|
popl %eax
|
|
ret
|
|
|
|
/* Unsigned 8-to-16 multiply. */
|
|
.globl VG_(helper_mul_8_16)
|
|
VG_(helper_mul_8_16):
|
|
pushl %eax
|
|
pushl %edx
|
|
movb 16(%esp), %al
|
|
mulb 12(%esp)
|
|
movw %ax, 16(%esp)
|
|
popl %edx
|
|
popl %eax
|
|
ret
|
|
|
|
|
|
|
|
|
|
/* Unsigned 64-into-32 divide. */
|
|
.globl VG_(helper_div_64_32)
|
|
VG_(helper_div_64_32):
|
|
pushl %eax
|
|
pushl %edx
|
|
movl 16(%esp),%eax
|
|
movl 12(%esp),%edx
|
|
divl 20(%esp)
|
|
movl %eax,16(%esp)
|
|
movl %edx,12(%esp)
|
|
popl %edx
|
|
popl %eax
|
|
ret
|
|
|
|
/* Signed 64-into-32 divide. */
|
|
.globl VG_(helper_idiv_64_32)
|
|
VG_(helper_idiv_64_32):
|
|
pushl %eax
|
|
pushl %edx
|
|
movl 16(%esp),%eax
|
|
movl 12(%esp),%edx
|
|
idivl 20(%esp)
|
|
movl %eax,16(%esp)
|
|
movl %edx,12(%esp)
|
|
popl %edx
|
|
popl %eax
|
|
ret
|
|
|
|
/* Unsigned 32-into-16 divide. */
|
|
.globl VG_(helper_div_32_16)
|
|
VG_(helper_div_32_16):
|
|
pushl %eax
|
|
pushl %edx
|
|
movw 16(%esp),%ax
|
|
movw 12(%esp),%dx
|
|
divw 20(%esp)
|
|
movw %ax,16(%esp)
|
|
movw %dx,12(%esp)
|
|
popl %edx
|
|
popl %eax
|
|
ret
|
|
|
|
/* Signed 32-into-16 divide. */
|
|
.globl VG_(helper_idiv_32_16)
|
|
VG_(helper_idiv_32_16):
|
|
pushl %eax
|
|
pushl %edx
|
|
movw 16(%esp),%ax
|
|
movw 12(%esp),%dx
|
|
idivw 20(%esp)
|
|
movw %ax,16(%esp)
|
|
movw %dx,12(%esp)
|
|
popl %edx
|
|
popl %eax
|
|
ret
|
|
|
|
/* Unsigned 16-into-8 divide. */
|
|
.globl VG_(helper_div_16_8)
|
|
VG_(helper_div_16_8):
|
|
pushl %eax
|
|
movw 12(%esp),%ax
|
|
divb 16(%esp)
|
|
movb %ah,12(%esp)
|
|
movb %al,8(%esp)
|
|
popl %eax
|
|
ret
|
|
|
|
/* Signed 16-into-8 divide. */
|
|
.globl VG_(helper_idiv_16_8)
|
|
VG_(helper_idiv_16_8):
|
|
pushl %eax
|
|
movw 12(%esp),%ax
|
|
idivb 16(%esp)
|
|
movb %ah,12(%esp)
|
|
movb %al,8(%esp)
|
|
popl %eax
|
|
ret
|
|
|
|
|
|
/* Eight byte compare and exchange. */
|
|
.globl VG_(helper_cmpxchg8b)
|
|
VG_(helper_cmpxchg8b):
|
|
pushl %eax
|
|
pushl %ebx
|
|
pushl %ecx
|
|
pushl %edx
|
|
movl 20(%esp), %eax
|
|
movl 24(%esp), %edx
|
|
movl 28(%esp), %ebx
|
|
movl 32(%esp), %ecx
|
|
cmpxchg8b 36(%esp)
|
|
movl %eax, 20(%esp)
|
|
movl %edx, 24(%esp)
|
|
movl %ebx, 28(%esp)
|
|
movl %ecx, 32(%esp)
|
|
popl %edx
|
|
popl %ecx
|
|
popl %ebx
|
|
popl %eax
|
|
ret
|
|
|
|
|
|
/* Undefined instruction (generates SIGILL) */
|
|
.globl VG_(helper_undefined_instruction)
|
|
VG_(helper_undefined_instruction):
|
|
1: ud2
|
|
jmp 1b
|
|
|
|
/* Let the linker know we don't need an executable stack */
|
|
.section .note.GNU-stack,"",@progbits
|
|
|
|
##--------------------------------------------------------------------##
|
|
##--- end ---##
|
|
##--------------------------------------------------------------------##
|