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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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b05a2a18d7
following improvements: - Arch/OS/platform-specific files are now included/excluded via the preprocessor, rather than via the build system. This is more consistent (we use the pre-processor for small arch/OS/platform-specific chunks within files) and makes the build system much simpler, as the sources for all programs are the same on all platforms. - Vast amounts of cut+paste Makefile.am code has been factored out. If a new platform is implemented, you need to add 11 extra Makefile.am lines. Previously it was over 100 lines. - Vex has been autotoolised. Dependency checking now works in Vex (no more incomplete builds). Parallel builds now also work. --with-vex no longer works; it's little use and a pain to support. VEX/Makefile is still in the Vex repository and gets overwritten at configure-time; it should probably be renamed Makefile-gcc to avoid possible problems, such as accidentally committing a generated Makefile. There's a bunch of hacky copying to deal with the fact that autotools don't handle same-named files in different directories. Julian plans to rename the files to avoid this problem. - Various small Makefile.am things have been made more standard automake style, eg. the use of pkginclude/pkglib prefixes instead of rolling our own. - The existing five top-level Makefile.am include files have been consolidated into three. - Most Makefile.am files now are structured more clearly, with comment headers separating sections, declarations relating to the same things next to each other, better spacing and layout, etc. - Removed the unused exp-ptrcheck/tests/x86 directory. - Renamed some XML files. - Factored out some duplicated dSYM handling code. - Split auxprogs/ into auxprogs/ and mpi/, which allowed the resulting Makefile.am files to be much more standard. - Cleaned up m_coredump by merging a bunch of files that had been overzealously separated. The net result is 630 fewer lines of Makefile.am code, or 897 if you exclude the added Makefile.vex.am, or 997 once the hacky file copying for Vex is removed. And the build system is much simpler. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@10364
655 lines
21 KiB
ArmAsm
655 lines
21 KiB
ArmAsm
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/*--------------------------------------------------------------------*/
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/*--- The core dispatch loop, for jumping to a code address. ---*/
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/*--- dispatch-ppc64-aix5.S ---*/
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/*--------------------------------------------------------------------*/
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/*
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This file is part of Valgrind, a dynamic binary instrumentation
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framework.
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Copyright (C) 2006-2009 OpenWorks LLP
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info@open-works.co.uk
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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Neither the names of the U.S. Department of Energy nor the
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University of California nor the names of its contributors may be
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used to endorse or promote products derived from this software
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without prior written permission.
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*/
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#if defined(VGP_ppc64_aix5)
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#include "pub_core_basics_asm.h"
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#include "pub_core_dispatch_asm.h"
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#include "pub_core_transtab_asm.h"
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#include "libvex_guest_offsets.h" /* for OFFSET_ppc64_CIA */
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/*------------------------------------------------------------*/
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/*--- ---*/
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/*--- The dispatch loop. VG_(run_innerloop) is used to ---*/
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/*--- run all translations except no-redir ones. ---*/
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/*--- ---*/
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/*------------------------------------------------------------*/
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/*----------------------------------------------------*/
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/*--- Incomprehensible TOC mumbo-jumbo nonsense. ---*/
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/*----------------------------------------------------*/
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/* No, I don't have a clue either. I just compiled a bit of
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C with gcc and copied the assembly code it produced. */
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/* Basically "ld rd, tocent__foo(2)" gets &foo into rd. */
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.file "dispatch-ppc64-aix5.S"
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.machine "ppc64"
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.toc
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.csect .text[PR]
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.toc
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tocent__vgPlain_dispatch_ctr:
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.tc vgPlain_dispatch_ctr[TC],vgPlain_dispatch_ctr[RW]
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tocent__vgPlain_machine_ppc64_has_VMX:
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.tc vgPlain_machine_ppc64_has_VMX[TC],vgPlain_machine_ppc64_has_VMX[RW]
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tocent__vgPlain_tt_fast:
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.tc vgPlain_tt_fast[TC],vgPlain_tt_fast[RW]
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tocent__vgPlain_tt_fastN:
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.tc vgPlain_tt_fast[TC],vgPlain_tt_fastN[RW]
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.csect .text[PR]
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.align 2
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.globl vgPlain_run_innerloop
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.globl .vgPlain_run_innerloop
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.csect vgPlain_run_innerloop[DS]
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vgPlain_run_innerloop:
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.llong .vgPlain_run_innerloop, TOC[tc0], 0
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.csect .text[PR]
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/*----------------------------------------------------*/
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/*--- Preamble (set everything up) ---*/
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/*----------------------------------------------------*/
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/* signature:
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UWord VG_(run_innerloop) ( void* guest_state, UWord do_profiling );
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*/
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.vgPlain_run_innerloop:
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/* r3 holds guest_state */
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/* r4 holds do_profiling */
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/* Rather than attempt to make sense of the AIX ABI, just
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drop r1 by 512 (to get away from the caller's frame), then
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1024 (to give ourselves a 1024-byte save area), and then
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another 512 (to clear our save area). In all, drop r1 by 2048
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and dump stuff on the stack at 512(1)..1536(1). */
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/* ----- entry point to VG_(run_innerloop) ----- */
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/* For AIX/ppc64 we do: LR-> +16(parent_sp), CR-> +8(parent_sp) */
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/* Save lr and cr*/
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mflr 0
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std 0,16(1)
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mfcr 0
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std 0,8(1)
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/* New stack frame */
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stdu 1,-2048(1) /* sp should maintain 16-byte alignment */
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/* Save callee-saved registers... */
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/* r3, r4 are live here, so use r5 */
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/* Floating-point reg save area : 144 bytes at r1[256+256..256+399] */
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stfd 31,256+392(1)
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stfd 30,256+384(1)
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stfd 29,256+376(1)
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stfd 28,256+368(1)
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stfd 27,256+360(1)
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stfd 26,256+352(1)
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stfd 25,256+344(1)
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stfd 24,256+336(1)
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stfd 23,256+328(1)
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stfd 22,256+320(1)
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stfd 21,256+312(1)
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stfd 20,256+304(1)
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stfd 19,256+296(1)
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stfd 18,256+288(1)
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stfd 17,256+280(1)
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stfd 16,256+272(1)
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stfd 15,256+264(1)
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stfd 14,256+256(1)
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/* General reg save area : 76 bytes at r1[256+400 .. 256+543] */
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std 31,256+544(1)
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std 30,256+536(1)
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std 29,256+528(1)
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std 28,256+520(1)
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std 27,256+512(1)
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std 26,256+504(1)
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std 25,256+496(1)
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std 24,256+488(1)
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std 23,256+480(1)
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std 22,256+472(1)
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std 21,256+464(1)
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std 20,256+456(1)
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std 19,256+448(1)
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std 18,256+440(1)
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std 17,256+432(1)
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std 16,256+424(1)
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std 15,256+416(1)
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std 14,256+408(1)
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/* Probably not necessary to save r13 (thread-specific ptr),
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as VEX stays clear of it... but what the hell. */
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std 13,256+400(1)
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/* It's necessary to save/restore VRSAVE in the AIX / Darwin ABI.
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The Linux kernel might not actually use VRSAVE for its intended
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purpose, but it should be harmless to preserve anyway. */
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/* r3, r4 are live here, so use r5 */
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ld 5,tocent__vgPlain_machine_ppc64_has_VMX(2)
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ld 5,0(5)
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cmpldi 5,0
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beq LafterVMX1
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// Sigh. AIX 5.2 has no idea that Altivec exists.
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// /* VRSAVE save word : 4 bytes at r1[476 .. 479] */
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// mfspr 5,256 /* vrsave reg is spr number 256 */
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// stw 5,476(1)
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//
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// /* Vector reg save area (quadword aligned):
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// 192 bytes at r1[480 .. 671] */
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// li 5,656
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// stvx 31,5,1
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// li 5,640
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// stvx 30,5,1
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// li 5,624
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// stvx 29,5,1
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// li 5,608
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// stvx 28,5,1
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// li 5,592
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// stvx 27,5,1
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// li 5,576
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// stvx 26,5,1
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// li 5,560
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// stvx 25,5,1
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// li 5,544
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// stvx 25,5,1
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// li 5,528
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// stvx 23,5,1
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// li 5,512
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// stvx 22,5,1
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// li 5,496
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// stvx 21,5,1
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// li 5,480
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// stvx 20,5,1
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LafterVMX1:
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/* Local variable space... */
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/* Put the original guest state pointer at r1[256]. We
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will need to refer to it each time round the dispatch loop.
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Apart from that, we can use r1[0 .. 255] and r1[264 .. 511]
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as scratch space. */
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/* r3 holds guest_state */
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/* r4 holds do_profiling */
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mr 31,3 /* r31 (generated code gsp) = r3 */
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std 3,256(1) /* stash orig guest_state ptr */
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/* hold dispatch_ctr (NOTE: 32-bit value) in r29 */
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ld 5,tocent__vgPlain_dispatch_ctr(2)
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lwz 29,0(5) /* 32-bit zero-extending load */
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/* set host FPU control word to the default mode expected
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by VEX-generated code. See comments in libvex.h for
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more info. */
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/* get zero into f3 (tedious) */
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/* note: fsub 3,3,3 is not a reliable way to do this,
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since if f3 holds a NaN or similar then we don't necessarily
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wind up with zero. */
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li 5,0
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std 5,128(1) /* r1[128] is scratch */
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lfd 3,128(1)
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mtfsf 0xFF,3 /* fpscr = f3 */
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/* set host AltiVec control word to the default mode expected
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by VEX-generated code. */
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ld 5,tocent__vgPlain_machine_ppc64_has_VMX(2)
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ld 5,0(5)
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cmpldi 5,0
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beq LafterVMX2
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// Sigh. AIX 5.2 has no idea that Altivec exists.
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// vspltisw 3,0x0 /* generate zero */
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// mtvscr 3
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LafterVMX2:
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/* fetch %CIA into r3 */
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ld 3,OFFSET_ppc64_CIA(31)
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/* fall into main loop (the right one) */
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/* r4 = do_profiling. It's probably trashed after here,
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but that's OK: we don't need it after here. */
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cmpldi 4,0
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beq VG_(run_innerloop__dispatch_unprofiled)
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b VG_(run_innerloop__dispatch_profiled)
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/*NOTREACHED*/
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/*----------------------------------------------------*/
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/*--- NO-PROFILING (standard) dispatcher ---*/
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/*----------------------------------------------------*/
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.globl VG_(run_innerloop__dispatch_unprofiled)
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VG_(run_innerloop__dispatch_unprofiled):
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/* At entry: Live regs:
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r1 (=sp)
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r3 (=CIA = next guest address)
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r29 (=dispatch_ctr)
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r31 (=guest_state)
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Stack state:
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256(r1) (=orig guest_state)
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*/
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/* Has the guest state pointer been messed with? If yes, exit. */
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ld 5,256(1) /* original guest_state ptr */
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cmpd 5,31
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ld 5,tocent__vgPlain_tt_fast(2) /* &VG_(tt_fast) */
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bne gsp_changed
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/* save the jump address in the guest state */
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std 3,OFFSET_ppc64_CIA(31)
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/* Are we out of timeslice? If yes, defer to scheduler. */
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addi 29,29,-1
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cmplwi 29,0 /* yes, lwi - is 32-bit */
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beq counter_is_zero
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/* try a fast lookup in the translation cache */
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/* r4 = VG_TT_FAST_HASH(addr) * sizeof(FastCacheEntry)
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= ((r3 >>u 2) & VG_TT_FAST_MASK) << 4 */
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rldicl 4,3, 62, 64-VG_TT_FAST_BITS /* entry# */
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sldi 4,4,4 /* entry# * sizeof(FastCacheEntry) */
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add 5,5,4 /* &VG_(tt_fast)[entry#] */
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ld 6,0(5) /* .guest */
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ld 7,8(5) /* .host */
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cmpd 3,6
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bne fast_lookup_failed
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/* Found a match. Call .host. */
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mtctr 7
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bctrl
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/* On return from guest code:
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r3 holds destination (original) address.
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r31 may be unchanged (guest_state), or may indicate further
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details of the control transfer requested to *r3.
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*/
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/* start over */
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b VG_(run_innerloop__dispatch_unprofiled)
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/*NOTREACHED*/
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/*----------------------------------------------------*/
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/*--- PROFILING dispatcher (can be much slower) ---*/
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/*----------------------------------------------------*/
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.globl VG_(run_innerloop__dispatch_profiled)
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VG_(run_innerloop__dispatch_profiled):
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/* At entry: Live regs:
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r1 (=sp)
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r3 (=CIA = next guest address)
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r29 (=dispatch_ctr)
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r31 (=guest_state)
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Stack state:
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256(r1) (=orig guest_state)
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*/
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/* Has the guest state pointer been messed with? If yes, exit. */
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ld 5,256(1) /* original guest_state ptr */
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cmpd 5,31
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ld 5,tocent__vgPlain_tt_fast(2) /* &VG_(tt_fast) */
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bne gsp_changed
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/* save the jump address in the guest state */
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std 3,OFFSET_ppc64_CIA(31)
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/* Are we out of timeslice? If yes, defer to scheduler. */
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addi 29,29,-1
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cmplwi 29,0 /* yes, lwi - is 32-bit */
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beq counter_is_zero
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/* try a fast lookup in the translation cache */
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/* r4 = VG_TT_FAST_HASH(addr) * sizeof(FastCacheEntry)
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= ((r3 >>u 2) & VG_TT_FAST_MASK) << 4 */
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rldicl 4,3, 62, 64-VG_TT_FAST_BITS /* entry# */
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sldi 4,4,4 /* entry# * sizeof(FastCacheEntry) */
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add 5,5,4 /* &VG_(tt_fast)[entry#] */
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ld 6,0(5) /* .guest */
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ld 7,8(5) /* .host */
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cmpd 3,6
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bne fast_lookup_failed
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/* increment bb profile counter */
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ld 9,tocent__vgPlain_tt_fastN(2) /* r9 = &tt_fastN */
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srdi 4,4,1 /* entry# * sizeof(UInt*) */
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ldx 8,9,4 /* r7 = tt_fastN[r4] */
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lwz 10,0(8)
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addi 10,10,1
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stw 10,0(8)
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/* Found a match. Call .host. */
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mtctr 7
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bctrl
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/* On return from guest code:
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r3 holds destination (original) address.
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r31 may be unchanged (guest_state), or may indicate further
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details of the control transfer requested to *r3.
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*/
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/* start over */
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b VG_(run_innerloop__dispatch_profiled)
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/*NOTREACHED*/
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/*----------------------------------------------------*/
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/*--- exit points ---*/
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/*----------------------------------------------------*/
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gsp_changed:
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/* Someone messed with the gsp (in r31). Have to
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defer to scheduler to resolve this. dispatch ctr
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is not yet decremented, so no need to increment. */
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/* %CIA is NOT up to date here. First, need to write
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%r3 back to %CIA, but without trashing %r31 since
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that holds the value we want to return to the scheduler.
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Hence use %r5 transiently for the guest state pointer. */
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ld 5,256(1) /* original guest_state ptr */
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std 3,OFFSET_ppc64_CIA(5)
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mr 3,31 /* r3 = new gsp value */
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b run_innerloop_exit
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/*NOTREACHED*/
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counter_is_zero:
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/* %CIA is up to date */
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/* back out decrement of the dispatch counter */
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addi 29,29,1
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li 3,VG_TRC_INNER_COUNTERZERO
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b run_innerloop_exit
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fast_lookup_failed:
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/* %CIA is up to date */
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/* back out decrement of the dispatch counter */
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addi 29,29,1
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li 3,VG_TRC_INNER_FASTMISS
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b run_innerloop_exit
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/* All exits from the dispatcher go through here.
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r3 holds the return value.
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*/
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run_innerloop_exit:
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/* We're leaving. Check that nobody messed with
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VSCR or FPSCR. */
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/* Set fpscr back to a known state, since vex-generated code
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may have messed with fpscr[rm]. */
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li 5,0
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std 5,128(1) /* r1[128] is scratch */
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lfd 3,128(1)
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mtfsf 0xFF,3 /* fpscr = f3 */
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/* Using r11 - value used again further on, so don't trash! */
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ld 11,tocent__vgPlain_machine_ppc64_has_VMX(2)
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ld 11,0(11)
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cmpldi 11,0
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beq LafterVMX8
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// Sigh. AIX 5.2 has no idea that Altivec exists.
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// /* Check VSCR[NJ] == 1 */
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// /* first generate 4x 0x00010000 */
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// vspltisw 4,0x1 /* 4x 0x00000001 */
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// vspltisw 5,0x0 /* zero */
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// vsldoi 6,4,5,0x2 /* <<2*8 => 4x 0x00010000 */
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// /* retrieve VSCR and mask wanted bits */
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// mfvscr 7
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// vand 7,7,6 /* gives NJ flag */
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// vspltw 7,7,0x3 /* flags-word to all lanes */
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// vcmpequw. 8,6,7 /* CR[24] = 1 if v6 == v7 */
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// bt 24,invariant_violation /* branch if all_equal */
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LafterVMX8:
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/* otherwise we're OK */
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b run_innerloop_exit_REALLY
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invariant_violation:
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li 3,VG_TRC_INVARIANT_FAILED
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b run_innerloop_exit_REALLY
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run_innerloop_exit_REALLY:
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/* r3 holds VG_TRC_* value to return */
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/* Write ctr to VG(dispatch_ctr) */
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ld 5,tocent__vgPlain_dispatch_ctr(2)
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stw 29,0(5) /* yes, really stw */
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/* Restore callee-saved registers... */
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|
|
/* Floating-point regs */
|
|
lfd 31,256+392(1)
|
|
lfd 30,256+384(1)
|
|
lfd 29,256+376(1)
|
|
lfd 28,256+368(1)
|
|
lfd 27,256+360(1)
|
|
lfd 26,256+352(1)
|
|
lfd 25,256+344(1)
|
|
lfd 24,256+336(1)
|
|
lfd 23,256+328(1)
|
|
lfd 22,256+320(1)
|
|
lfd 21,256+312(1)
|
|
lfd 20,256+304(1)
|
|
lfd 19,256+296(1)
|
|
lfd 18,256+288(1)
|
|
lfd 17,256+280(1)
|
|
lfd 16,256+272(1)
|
|
lfd 15,256+264(1)
|
|
lfd 14,256+256(1)
|
|
|
|
/* General regs */
|
|
ld 31,256+544(1)
|
|
ld 30,256+536(1)
|
|
ld 29,256+528(1)
|
|
ld 28,256+520(1)
|
|
ld 27,256+512(1)
|
|
ld 26,256+504(1)
|
|
ld 25,256+496(1)
|
|
ld 24,256+488(1)
|
|
ld 23,256+480(1)
|
|
ld 22,256+472(1)
|
|
ld 21,256+464(1)
|
|
ld 20,256+456(1)
|
|
ld 19,256+448(1)
|
|
ld 18,256+440(1)
|
|
ld 17,256+432(1)
|
|
ld 16,256+424(1)
|
|
ld 15,256+416(1)
|
|
ld 14,256+408(1)
|
|
ld 13,256+400(1)
|
|
|
|
/* r11 already holds VG_(machine_ppc64_has_VMX) value */
|
|
cmpldi 11,0
|
|
beq LafterVMX9
|
|
|
|
// Sigh. AIX 5.2 has no idea that Altivec exists.
|
|
// /* VRSAVE */
|
|
// lwz 4,476(1)
|
|
// mtspr 4,256 /* VRSAVE reg is spr number 256 */
|
|
//
|
|
// /* Vector regs */
|
|
// li 4,656
|
|
// lvx 31,4,1
|
|
// li 4,640
|
|
// lvx 30,4,1
|
|
// li 4,624
|
|
// lvx 29,4,1
|
|
// li 4,608
|
|
// lvx 28,4,1
|
|
// li 4,592
|
|
// lvx 27,4,1
|
|
// li 4,576
|
|
// lvx 26,4,1
|
|
// li 4,560
|
|
// lvx 25,4,1
|
|
// li 4,544
|
|
// lvx 24,4,1
|
|
// li 4,528
|
|
// lvx 23,4,1
|
|
// li 4,512
|
|
// lvx 22,4,1
|
|
// li 4,496
|
|
// lvx 21,4,1
|
|
// li 4,480
|
|
// lvx 20,4,1
|
|
LafterVMX9:
|
|
|
|
/* r3 is live here; don't trash it */
|
|
/* restore lr,cr,sp */
|
|
addi 4,1,2048 /* r4 = old SP */
|
|
ld 0,16(4)
|
|
mtlr 0
|
|
ld 0,8(4)
|
|
mtcr 0
|
|
mr 1,4
|
|
blr
|
|
|
|
LT..vgPlain_run_innerloop:
|
|
.long 0
|
|
.byte 0,0,32,64,0,0,1,0
|
|
.long 0
|
|
.long LT..vgPlain_run_innerloop-.vgPlain_run_innerloop
|
|
.short 3
|
|
.byte "vgPlain_run_innerloop"
|
|
.align 2
|
|
_section_.text:
|
|
.csect .data[RW],3
|
|
.llong _section_.text
|
|
|
|
/*------------------------------------------------------------*/
|
|
/*--- ---*/
|
|
/*--- A special dispatcher, for running no-redir ---*/
|
|
/*--- translations. Just runs the given translation once. ---*/
|
|
/*--- ---*/
|
|
/*------------------------------------------------------------*/
|
|
|
|
/* signature:
|
|
void VG_(run_a_noredir_translation) ( UWord* argblock );
|
|
*/
|
|
|
|
/* Run a no-redir translation. argblock points to 4 UWords, 2 to carry args
|
|
and 2 to carry results:
|
|
0: input: ptr to translation
|
|
1: input: ptr to guest state
|
|
2: output: next guest PC
|
|
3: output: guest state pointer afterwards (== thread return code)
|
|
*/
|
|
.csect .text[PR]
|
|
.align 2
|
|
.globl .VG_(run_a_noredir_translation)
|
|
.VG_(run_a_noredir_translation):
|
|
/* Rather than attempt to make sense of the AIX ABI, just
|
|
drop r1 by 512 (to get away from the caller's frame), then
|
|
1024 (to give ourselves a 1024-byte save area), and then
|
|
another 1024 (to clear our save area). In all, drop r1 by 2048
|
|
and dump stuff on the stack at 512(1)..1536(1). */
|
|
/* At entry, r3 points to argblock */
|
|
|
|
/* ----- entry point to VG_(run_innerloop) ----- */
|
|
/* For AIX/ppc64 we do: LR-> +16(parent_sp), CR-> +8(parent_sp) */
|
|
|
|
/* Save lr and cr*/
|
|
mflr 0
|
|
std 0,16(1)
|
|
mfcr 0
|
|
std 0,8(1)
|
|
|
|
/* New stack frame */
|
|
stdu 1,-2048(1) /* sp should maintain 16-byte alignment */
|
|
|
|
/* General reg save area : 160 bytes at r1[512 .. 671] */
|
|
std 31,664(1)
|
|
std 30,656(1)
|
|
std 29,648(1)
|
|
std 28,640(1)
|
|
std 27,632(1)
|
|
std 26,624(1)
|
|
std 25,616(1)
|
|
std 24,608(1)
|
|
std 23,600(1)
|
|
std 22,592(1)
|
|
std 21,584(1)
|
|
std 20,576(1)
|
|
std 19,568(1)
|
|
std 18,560(1)
|
|
std 17,552(1)
|
|
std 16,544(1)
|
|
std 15,536(1)
|
|
std 14,528(1)
|
|
std 13,520(1)
|
|
std 3,512(1) /* will need it later */
|
|
|
|
ld 31,8(3) /* rd argblock[1] */
|
|
ld 30,0(3) /* rd argblock[0] */
|
|
mtlr 30 /* run translation */
|
|
blrl
|
|
|
|
ld 4,512(1) /* &argblock */
|
|
std 3, 16(4) /* wr argblock[2] */
|
|
std 31,24(4) /* wr argblock[3] */
|
|
|
|
/* General regs */
|
|
ld 31,664(1)
|
|
ld 30,656(1)
|
|
ld 29,648(1)
|
|
ld 28,640(1)
|
|
ld 27,632(1)
|
|
ld 26,624(1)
|
|
ld 25,616(1)
|
|
ld 24,608(1)
|
|
ld 23,600(1)
|
|
ld 22,592(1)
|
|
ld 21,584(1)
|
|
ld 20,576(1)
|
|
ld 19,568(1)
|
|
ld 18,560(1)
|
|
ld 17,552(1)
|
|
ld 16,544(1)
|
|
ld 15,536(1)
|
|
ld 14,528(1)
|
|
ld 13,520(1)
|
|
|
|
/* restore lr,cr,sp */
|
|
addi 4,1,2048 /* r4 = old SP */
|
|
ld 0,16(4)
|
|
mtlr 0
|
|
ld 0,8(4)
|
|
mtcr 0
|
|
mr 1,4
|
|
blr
|
|
|
|
#endif // defined(VGP_ppc64_aix5)
|
|
|
|
/*--------------------------------------------------------------------*/
|
|
/*--- end ---*/
|
|
/*--------------------------------------------------------------------*/
|