ftmemsim-valgrind/drd/tests/unit_vc.stderr.exp
Bart Van Assche e34229bd49 svn merge -r9818:10278 svn://svn.valgrind.org/valgrind/branches/DRDDEV
git-svn-id: svn://svn.valgrind.org/valgrind/trunk@10279
2009-06-08 18:20:42 +00:00

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vc1: [ 3: 7, 5: 8 ]
vc2: [ 1: 4, 3: 9 ]
vc3: [ 1: 4, 3: 9, 5: 8 ]
vc_lte(vc1, vc2) = 0, vc_lte(vc1, vc3) = 1, vc_lte(vc2, vc3) = 1
vc_lte([ 1: 3, 2: 1 ], [ 1: 4 ]) = 0 sw 0