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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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95d8477491
The IBM Power ISA 2.07 has been published on power.org, and IBM's new POWER8 processor is under development to implement that ISA. This patch provides initial runtime and testsuite support for running Valgrind on POWER8 systems running a soon-to-be released Linux distribution. This Linux distro will include a POWER8-tuned libc that uses a subset of the new instructions from ISA 2.07. Since virtually all applications link with libc, it would be impossible to run an application under Valgrind on this distro without adding support for these new instructions to Valgrind, so that's the intent of this patch. Note that applications built on this distro will *not* employ new POWER8 instructions by default. There are roughly 150 new instructions in the Power ISA 2.07, including hardware transaction management (HTM). Support for these new instructions (modulo the subset included in this bug) will be added to Valgrind in a phased approach, similar to what we did for Power ISA 2.06. Bugzilla 322294, VEX commit 2740 git-svn-id: svn://svn.valgrind.org/valgrind/trunk@13494
104 lines
3.6 KiB
Makefile
104 lines
3.6 KiB
Makefile
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include $(top_srcdir)/Makefile.tool-tests.am
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dist_noinst_SCRIPTS = filter_stderr
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EXTRA_DIST = \
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jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
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jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest \
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jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
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jm-vmx.vgtest \
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lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
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std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp \
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round.stderr.exp round.stdout.exp round.vgtest \
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twi_tdi.stderr.exp twi_tdi.stdout.exp twi_tdi.vgtest \
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tw_td.stderr.exp tw_td.stdout.exp tw_td.vgtest \
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power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \
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power6_mf_gpr.stderr.exp power6_mf_gpr.stdout.exp power6_mf_gpr.vgtest \
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test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
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test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
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test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
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test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
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test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
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test_dfp2.stdout.exp_Without_dcffix \
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test_dfp3.stderr.exp test_dfp3.stdout.exp test_dfp3.vgtest \
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test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \
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test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \
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jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.vgtest \
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test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest
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check_PROGRAMS = \
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allexec \
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jm-insns lsw round std_reg_imm twi_tdi tw_td power6_bcmp \
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power6_mf_gpr test_isa_2_06_part1 test_isa_2_06_part2 \
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test_isa_2_06_part3 test_dfp1 test_dfp2 test_dfp3 test_dfp4 \
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test_dfp5 test_isa_2_07_part1 test_isa_2_07_part2
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AM_CFLAGS += @FLAG_M64@
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AM_CXXFLAGS += @FLAG_M64@
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AM_CCASFLAGS += @FLAG_M64@
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allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
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if HAS_ALTIVEC
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ALTIVEC_FLAG = -DHAS_ALTIVEC
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else
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ALTIVEC_FLAG =
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endif
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if HAS_VSX
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BUILD_FLAG_VSX = -mvsx
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VSX_FLAG = -DHAS_VSX
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else
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VSX_FLAG =
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BUILD_FLAG_VSX =
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endif
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if HAS_DFP
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BUILD_FLAGS_DFP = -mhard-dfp -mcpu=power6
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DFP_FLAG = -DHAS_DFP
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else
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BUILD_FLAGS_DFP =
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DFP_FLAG =
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endif
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if HAS_ISA_2_07
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BUILD_FLAGS_ISA_2_07 = -mcpu=power8
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ISA_2_07_FLAG = -DHAS_ISA_2_07
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else
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BUILD_FLAGS_ISA_2_07 =
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ISA_2_07_FLAG =
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endif
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test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
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@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
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test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
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@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
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test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \
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@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
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jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \
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@FLAG_M64@ $(ALTIVEC_FLAG)
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test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_DFP)
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test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_DFP)
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test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_DFP)
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test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_DFP)
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test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_DFP)
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test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
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test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
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