mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-05 19:13:46 +00:00
70a543e5a1
- move some asm things into x86/ - also added a check at the start of init_tt_tc() to make sure that VG_CODE_OFFSET is correct. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@2846
138 lines
5.2 KiB
C
138 lines
5.2 KiB
C
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/*--------------------------------------------------------------------*/
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/*--- Asm-specific core stuff. core_asm.h ---*/
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/*--------------------------------------------------------------------*/
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/*
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This file is part of Valgrind, an extensible x86 protected-mode
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emulator for monitoring program execution on x86-Unixes.
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Copyright (C) 2000-2004 Julian Seward
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jseward@acm.org
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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#ifndef __CORE_ASM_H
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#define __CORE_ASM_H
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#include "tool_asm.h" // tool asm stuff
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#include "core_arch_asm.h" // arch-specific asm stuff
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/* This file is included in all Valgrind source files, including
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assembly ones. */
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/* Magic values that %ebp might be set to when returning to the
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dispatcher. The only other legitimate value is to point to the
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start of VG_(baseBlock). These also are return values from
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VG_(run_innerloop) to the scheduler.
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EBP means %ebp can legitimately have this value when a basic block
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returns to the dispatch loop. TRC means that this value is a valid
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thread return code, which the dispatch loop may return to the
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scheduler. */
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#define VG_TRC_EBP_JMP_SYSCALL 19 /* EBP and TRC */
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#define VG_TRC_EBP_JMP_CLIENTREQ 23 /* EBP and TRC */
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#define VG_TRC_EBP_JMP_YIELD 27 /* EBP and TRC */
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#define VG_TRC_INNER_FASTMISS 31 /* TRC only; means fast-cache miss. */
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#define VG_TRC_INNER_COUNTERZERO 29 /* TRC only; means bb ctr == 0 */
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#define VG_TRC_UNRESUMABLE_SIGNAL 37 /* TRC only; got sigsegv/sigbus */
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/* Constants for the fast translation lookup cache. */
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#define VG_TT_FAST_BITS 15
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#define VG_TT_FAST_SIZE (1 << VG_TT_FAST_BITS)
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#define VG_TT_FAST_MASK ((VG_TT_FAST_SIZE) - 1)
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/* Constants for the fast original-code-write check cache. */
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/* Assembly code stubs make this request */
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#define VG_USERREQ__SIGNAL_RETURNS 0x4001
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// XXX: all this will go into x86/ eventually...
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/*
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0 - standard feature flags
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1 - Intel extended flags
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2 - Valgrind internal flags
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3 - AMD-specific flags
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*/
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#define VG_N_FEATURE_WORDS 4
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#define VG_X86_FEAT 0
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#define VG_EXT_FEAT 1
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#define VG_INT_FEAT 2
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#define VG_AMD_FEAT 3
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/* CPU features (generic) */
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#define VG_X86_FEAT_FPU (VG_X86_FEAT*32 + 0)
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#define VG_X86_FEAT_VME (VG_X86_FEAT*32 + 1)
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#define VG_X86_FEAT_DE (VG_X86_FEAT*32 + 2)
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#define VG_X86_FEAT_PSE (VG_X86_FEAT*32 + 3)
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#define VG_X86_FEAT_TSC (VG_X86_FEAT*32 + 4)
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#define VG_X86_FEAT_MSR (VG_X86_FEAT*32 + 5)
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#define VG_X86_FEAT_PAE (VG_X86_FEAT*32 + 6)
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#define VG_X86_FEAT_MCE (VG_X86_FEAT*32 + 7)
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#define VG_X86_FEAT_CX8 (VG_X86_FEAT*32 + 8)
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#define VG_X86_FEAT_APIC (VG_X86_FEAT*32 + 9)
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#define VG_X86_FEAT_SEP (VG_X86_FEAT*32 + 11)
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#define VG_X86_FEAT_MTRR (VG_X86_FEAT*32 + 12)
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#define VG_X86_FEAT_PGE (VG_X86_FEAT*32 + 13)
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#define VG_X86_FEAT_MCA (VG_X86_FEAT*32 + 14)
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#define VG_X86_FEAT_CMOV (VG_X86_FEAT*32 + 15)
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#define VG_X86_FEAT_PAT (VG_X86_FEAT*32 + 16)
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#define VG_X86_FEAT_PSE36 (VG_X86_FEAT*32 + 17)
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#define VG_X86_FEAT_CLFSH (VG_X86_FEAT*32 + 19)
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#define VG_X86_FEAT_DS (VG_X86_FEAT*32 + 21)
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#define VG_X86_FEAT_ACPI (VG_X86_FEAT*32 + 22)
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#define VG_X86_FEAT_MMX (VG_X86_FEAT*32 + 23)
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#define VG_X86_FEAT_FXSR (VG_X86_FEAT*32 + 24)
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#define VG_X86_FEAT_SSE (VG_X86_FEAT*32 + 25)
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#define VG_X86_FEAT_SSE2 (VG_X86_FEAT*32 + 26)
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#define VG_X86_FEAT_SS (VG_X86_FEAT*32 + 27)
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#define VG_X86_FEAT_HT (VG_X86_FEAT*32 + 28)
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#define VG_X86_FEAT_TM (VG_X86_FEAT*32 + 29)
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#define VG_X86_FEAT_IA64 (VG_X86_FEAT*32 + 30)
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#define VG_X86_FEAT_PBE (VG_X86_FEAT*32 + 31)
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/* Intel extended feature word */
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#define VG_X86_FEAT_SSE3 (VG_EXT_FEAT*32 + 0)
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#define VG_X86_FEAT_MON (VG_EXT_FEAT*32 + 3)
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#define VG_X86_FEAT_DSCPL (VG_EXT_FEAT*32 + 4)
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#define VG_X86_FEAT_EST (VG_EXT_FEAT*32 + 7)
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#define VG_X86_FEAT_TM2 (VG_EXT_FEAT*32 + 8)
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#define VG_X86_FEAT_CNXTID (VG_EXT_FEAT*32 + 10)
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/* Used internally to mark whether CPUID is even implemented */
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#define VG_X86_FEAT_CPUID (VG_INT_FEAT*32 + 0)
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/* AMD special features */
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#define VG_AMD_FEAT_SYSCALL (VG_AMD_FEAT*32 + 11)
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#define VG_AMD_FEAT_NXP (VG_AMD_FEAT*32 + 20)
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#define VG_AMD_FEAT_MMXEXT (VG_AMD_FEAT*32 + 22)
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#define VG_AMD_FEAT_FFXSR (VG_AMD_FEAT*32 + 25)
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#define VG_AMD_FEAT_LONGMODE (VG_AMD_FEAT*32 + 29)
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#define VG_AMD_FEAT_3DNOWEXT (VG_AMD_FEAT*32 + 30)
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#define VG_AMD_FEAT_3DNOW (VG_AMD_FEAT*32 + 31)
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#endif /* __CORE_ASM_H */
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/*--------------------------------------------------------------------*/
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/*--- end ---*/
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/*--------------------------------------------------------------------*/
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