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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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d2ca761361
instruction support -- VEX side changes. See #295221. This patch adds test cases. Also adds some minor Memcheck instrumentation tweaks necessitated by the IR changes. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@12476
92 lines
2.9 KiB
Makefile
92 lines
2.9 KiB
Makefile
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include $(top_srcdir)/Makefile.tool-tests.am
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dist_noinst_SCRIPTS = filter_stderr
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EXTRA_DIST = \
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bug129390-ppc32.stdout.exp bug129390-ppc32.stderr.exp \
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bug129390-ppc32.vgtest \
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bug139050-ppc32.stdout.exp bug139050-ppc32.stderr.exp \
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bug139050-ppc32.vgtest \
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ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \
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lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
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jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
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jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest \
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jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
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jm-vmx.vgtest \
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mftocrf.stderr.exp mftocrf.stdout.exp mftocrf.vgtest \
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mcrfs.stderr.exp mcrfs.stdout.exp mcrfs.vgtest \
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round.stderr.exp round.stdout.exp round.vgtest \
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test_fx.stderr.exp test_fx.stdout.exp test_fx.stdout.exp_Minus_nan \
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test_fx.vgtest \
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test_gx.stderr.exp test_gx.stdout.exp test_gx.stdout.exp_Minus_nan \
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test_gx.vgtest \
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testVMX.stderr.exp testVMX.stdout.exp testVMX.vgtest \
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twi.stderr.exp twi.stdout.exp twi.vgtest \
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tw.stderr.exp tw.stdout.exp tw.vgtest \
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xlc_dbl_u32.stderr.exp xlc_dbl_u32.stdout.exp xlc_dbl_u32.vgtest \
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power5+_round.stderr.exp power5+_round.stdout.exp power5+_round.vgtest \
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power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \
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test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
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test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
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test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
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test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest
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check_PROGRAMS = \
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allexec \
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bug129390-ppc32 \
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bug139050-ppc32 \
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ldstrev lsw jm-insns mftocrf mcrfs round test_fx test_gx \
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testVMX twi tw xlc_dbl_u32 power5+_round power6_bcmp \
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test_isa_2_06_part1 \
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test_isa_2_06_part2 \
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test_isa_2_06_part3 \
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test_dfp1
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AM_CFLAGS += @FLAG_M32@
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AM_CXXFLAGS += @FLAG_M32@
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AM_CCASFLAGS += @FLAG_M32@
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allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
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if HAS_ALTIVEC
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ALTIVEC_FLAG = -DHAS_ALTIVEC
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else
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ALTIVEC_FLAG =
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endif
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if HAS_VSX
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BUILD_FLAG_VSX = -mvsx
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VSX_FLAG = -DHAS_VSX
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else
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BUILD_FLAG_VSX =
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VSX_FLAG =
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endif
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if HAS_DFP
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BUILD_FLAGS_DFP = -mhard-dfp -mcpu=power6
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DFP_FLAG = -DHAS_DFP
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else
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BUILD_FLAGS_DFP =
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DFP_FLAG =
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endif
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jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \
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@FLAG_M32@ $(ALTIVEC_FLAG)
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testVMX_CFLAGS = $(AM_CFLAGS) -O -g -Wall -maltivec -mabi=altivec -DALTIVEC \
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-DGCC_COMPILER @FLAG_M32@
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test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
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@FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
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test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
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@FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
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test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \
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@FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
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test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
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@FLAG_M32@ $(BUILD_FLAGS_DFP)
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