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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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ec0778f110
They should have been part of the previous commit 15106. -------------------------------------------------------------------- Add support for the lbarx, lharx, stbcx and sthcs instructions. The instructions are part of the ISA 2.06 but were not implemented in all versions of hardware. The four instructions are all supported in ISA 2.07. The instructions were put under the ISA 2.07 category of supported instructions in this patch. The VEX commit for this fix is r3137. The bugzilla for this issue is 346324. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15107
48 lines
1.3 KiB
C
48 lines
1.3 KiB
C
#include <stdio.h>
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#include <config.h>
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double foo = -1.0;
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double FRT1;
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double FRT2;
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#ifdef HAS_ISA_2_07
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/* b0 may be non-zero in lwarx/ldarx Power6 instrs */
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void test_reservation()
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{
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unsigned long RT;
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unsigned long base;
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unsigned long offset;
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unsigned arrB[] = { 0x00112233U, 0x44556677U, 0x8899aabbU, 0xccddeeffU };
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int arrH[] __attribute__ ((aligned (2))) = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
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/* The lbarx and lharx instructions were "phased in" in ISA 2.06. That
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* means it they may show up in some implementations but not others. They
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* are in all ISA 2.08 implementations.
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*/
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base = (unsigned long) &arrB;
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offset = ((unsigned long) &arrB[1]) - base;
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__asm__ volatile ("ori 20, %0, 0"::"r" (base));
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__asm__ volatile ("ori 21, %0, 0"::"r" (offset));
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__asm__ volatile ("lbarx %0, 20, 21, 1":"=r" (RT));
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printf("lbarx => 0x%lx\n", RT);
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base = (unsigned long) &arrH;
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offset = ((unsigned long) &arrH[1]) - base;
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__asm__ volatile ("ori 20, %0, 0"::"r" (base));
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__asm__ volatile ("ori 21, %0, 0"::"r" (offset));
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__asm__ volatile ("lharx %0, 20, 21, 1":"=r" (RT));
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printf("lharx => 0x%lx\n", RT);
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}
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#endif
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int main(void)
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{
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#ifdef HAS_ISA_2_07
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(void) test_reservation();
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#endif
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return 0;
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}
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