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0d3d66a4ac
- client stack setup - init_thread1state: set TOC ptr git-svn-id: svn://svn.valgrind.org/valgrind/trunk@5314
486 lines
15 KiB
ArmAsm
486 lines
15 KiB
ArmAsm
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##--------------------------------------------------------------------##
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##--- The core dispatch loop, for jumping to a code address. ---##
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##--- dispatch-ppc64.S ---##
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##--------------------------------------------------------------------##
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/*
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This file is part of Valgrind, a dynamic binary instrumentation
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framework.
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Copyright (C) 2005 Cerion Armour-Brown <cerion@open-works.co.uk>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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#include "pub_core_basics_asm.h"
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#include "pub_core_dispatch_asm.h"
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#include "pub_core_transtab_asm.h"
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#include "libvex_guest_offsets.h" /* for OFFSET_ppc64_CIA */
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/* References to globals via the TOC */
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/*
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.globl vgPlain_tt_fast
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.lcomm vgPlain_tt_fast,4,4
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.type vgPlain_tt_fast, @object
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*/
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.section ".toc","aw"
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.tocent__vgPlain_tt_fast:
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.tc vgPlain_tt_fast[TC],vgPlain_tt_fast
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.tocent__vgPlain_dispatch_ctr:
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.tc vgPlain_dispatch_ctr[TC],vgPlain_dispatch_ctr
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.tocent__vgPlain_machine_ppc64_has_VMX:
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.tc vgPlain_machine_ppc64_has_VMX[TC],vgPlain_machine_ppc64_has_VMX
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/*------------------------------------------------------------*/
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/*--- The dispatch loop. ---*/
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/*------------------------------------------------------------*/
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/* signature: UWord VG_(run_innerloop) ( void* guest_state ) */
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.section ".text"
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.align 2
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.globl VG_(run_innerloop)
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.section ".opd","aw"
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.align 3
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VG_(run_innerloop):
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.quad .VG_(run_innerloop),.TOC.@tocbase,0
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.previous
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.type .VG_(run_innerloop),@function
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.globl .VG_(run_innerloop)
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.VG_(run_innerloop):
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/* ----- entry point to VG_(run_innerloop) ----- */
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/* PPC64 ABI saves LR->16(prt_sp), CR->8(prt_sp)) */
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/* Save lr, cr */
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mflr 0
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std 0,16(1)
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mfcr 0
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std 0,8(1)
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/* New stack frame */
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stdu 1,-624(1) /* sp should maintain 16-byte alignment */
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/* Save callee-saved registers... */
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/* Floating-point reg save area : 144 bytes */
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stfd 31,616(1)
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stfd 30,608(1)
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stfd 29,600(1)
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stfd 28,592(1)
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stfd 27,584(1)
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stfd 26,576(1)
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stfd 25,568(1)
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stfd 24,560(1)
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stfd 23,552(1)
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stfd 22,544(1)
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stfd 21,536(1)
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stfd 20,528(1)
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stfd 19,520(1)
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stfd 18,512(1)
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stfd 17,504(1)
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stfd 16,496(1)
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stfd 15,488(1)
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stfd 14,480(1)
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/* General reg save area : 144 bytes */
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std 31,472(1)
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std 30,464(1)
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std 29,456(1)
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std 28,448(1)
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std 27,440(1)
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std 26,432(1)
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std 25,424(1)
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std 24,416(1)
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std 23,408(1)
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std 22,400(1)
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std 21,392(1)
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std 20,384(1)
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std 19,376(1)
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std 18,368(1)
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std 17,360(1)
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std 16,352(1)
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std 15,344(1)
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std 14,336(1)
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/* Probably not necessary to save r13 (thread-specific ptr),
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as VEX stays clear of it... but what the hey. */
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std 13,328(1)
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/* It's necessary to save/restore VRSAVE in the AIX / Darwin ABI.
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The Linux kernel might not actually use VRSAVE for its intended
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purpose, but it should be harmless to preserve anyway. */
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/* r3 is live here (guest state ptr), so use r4 */
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lis 4,.tocent__vgPlain_machine_ppc64_has_VMX@ha
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ld 4,.tocent__vgPlain_machine_ppc64_has_VMX@l(4)
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cmpldi 4,0
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beq .LafterVMX1
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/* VRSAVE save word : 32 bytes */
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mfspr 4,256 /* vrsave reg is spr number 256 */
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stw 4,324(1)
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/* Alignment padding : 4 bytes */
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/* Vector reg save area (quadword aligned) : 192 bytes */
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li 4,304
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stvx 31,4,1
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li 4,288
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stvx 30,4,1
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li 4,272
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stvx 29,4,1
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li 4,256
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stvx 28,4,1
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li 4,240
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stvx 27,4,1
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li 4,224
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stvx 26,4,1
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li 4,208
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stvx 25,4,1
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li 4,192
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stvx 24,4,1
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li 4,176
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stvx 23,4,1
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li 4,160
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stvx 22,4,1
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li 4,144
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stvx 21,4,1
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li 4,128
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stvx 20,4,1
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.LafterVMX1:
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/* Local variable space... */
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/* r3 holds guest_state */
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mr 31,3
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std 3,104(1) /* spill orig guest_state ptr */
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/* 96(sp) used later to check FPSCR[RM] */
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/* 88(sp) used later to stop ctr reg being clobbered */
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/* 80(sp) used later to load fpscr with zero */
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/* 48:79(sp) free */
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/* Linkage Area (reserved)
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40(sp) : TOC
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32(sp) : link editor doubleword
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24(sp) : compiler doubleword
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16(sp) : LR
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8(sp) : CR
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0(sp) : back-chain
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*/
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// CAB TODO: Use a caller-saved reg for orig guest_state ptr
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// - rem to set non-allocateable in isel.c
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/* hold VG_(dispatch_ctr) (=32bit value) in ctr reg */
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lis 17,.tocent__vgPlain_dispatch_ctr@ha
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lwz 17,.tocent__vgPlain_dispatch_ctr@l(17)
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mtctr 17
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/* fetch %CIA into r30 */
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ld 30,OFFSET_ppc64_CIA(31)
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/* set host FPU control word to the default mode expected
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by VEX-generated code. See comments in libvex.h for
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more info. */
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/* => get zero into f3 (tedious)
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fsub 3,3,3 is not a reliable way to do this, since if
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f3 holds a NaN or similar then we don't necessarily
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wind up with zero. */
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li 3,0
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stw 3,80(1)
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lfs 3,80(1)
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mtfsf 0xFF,3 /* fpscr = lo32 of f3 */
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/* set host AltiVec control word to the default mode expected
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by VEX-generated code. */
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lis 3,.tocent__vgPlain_machine_ppc64_has_VMX@ha
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ld 3,.tocent__vgPlain_machine_ppc64_has_VMX@l(3)
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cmpldi 3,0
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beq .LafterVMX2
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vspltisw 3,0x0 /* generate zero */
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mtvscr 3
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.LafterVMX2:
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/* make a stack frame for the code we are calling */
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stdu 1,-48(1)
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/* fall into main loop */
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/* Live regs:
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r1 (=sp)
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r2 (toc pointer)
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r30 (=guest CIA = jump address)
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r31 (=guest_state)
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ctr (=dispatch_ctr)
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Stack state:
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104 (r1) (=guest_state ptr)
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96 (r1) (=var space for FPSCR[RM])
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88 (r1) (=var space for CTR)
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44:87 (r1) (=free)
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0:43 (r1) (=stack frame header)
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*/
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.dispatch_boring:
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/* save the jump address in the guest state */
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std 30,OFFSET_ppc64_CIA(31)
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/* Are we out of timeslice? If yes, defer to scheduler. */
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bdz .counter_is_zero /* decrements ctr reg */
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/* try a fast lookup in the translation cache */
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/* r4=((r30<<3) & (VG_TT_FAST_MASK<<3)) */
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rldic 4,30, 3,64-3-VG_TT_FAST_BITS
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// CAB: use a caller-saved reg for this ?
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/* r5 = & VG_(tt_fast) */
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ld 5, .tocent__vgPlain_tt_fast@toc(2)
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/* r5 = VG_(tt_fast)[r30 & VG_TT_FAST_MASK] */
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ldx 5, 5,4
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/* r6 = VG_(tt_fast)[r30 & VG_TT_FAST_MASK]->orig_addr */
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ld 6, 0(5)
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cmpd 30,6
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bne .fast_lookup_failed
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/* increment bb profile counter VG_(tt_fastN)[x] (=32bit val) */
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// CAB: use a caller-saved reg for this ?
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/* r7 = & VG_(tt_fastN) */
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ld 7, .tocent__vgPlain_tt_fast@toc(2)
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/* r7 = VG_(tt_fastN)[r30 & VG_TT_FAST_MASK] */
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srdi 4, 4,1
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lwzx 6, 7,4
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addi 6, 6,1
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stwx 6, 7,4
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/* Found a match. Call tce[1], which is 8 bytes along, since
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each tce element is a 64-bit int. */
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addi 8,5,8
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mtlr 8
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/* stop ctr being clobbered */
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// CAB: use a caller-saved reg for this ?
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// but then (bdz) => (decr, cmp, bc)... still better than a std?
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mfctr 9
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std 9,136(1) /* => 88(parent_sp) */
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blrl
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/* On return from guest code:
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r3 holds destination (original) address.
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r31 may be unchanged (guest_state), or may indicate further
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details of the control transfer requested to *r3.
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If r31 is unchanged, just jump next to r3.
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Otherwise fall out, back to the scheduler, and let it
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figure out what to do next.
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*/
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/* reinstate clobbered ctr */
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ld 9,136(1) /* => 88(parent_sp) */
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mtctr 9
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mr 30,3 /* put CIA (=r3) in r30 */
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ld 16,152(1) /* gst_state ptr => 104(prnt_sp) */
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cmpd 16,31
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beq .dispatch_boring /* r31 unchanged... */
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mr 3,31 /* put return val (=r31) in r3 */
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b .dispatch_exceptional
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/* All exits from the dispatcher go through here.
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r3 holds the return value.
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*/
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.run_innerloop_exit:
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/* We're leaving. Check that nobody messed with
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VSCR or FPSCR. */
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/* This check avoidance may be removable if stfiwx is implemented. */
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#if !defined(ENABLE_INNER)
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/* Check FPSCR & 0xFF == 0 (lowest 8bits are controls) */
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mffs 4 /* fpscr -> fpr */
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li 5,144 /* => 96(parent_sp) */
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stfiwx 4,5,1 /* fpr to stack */
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lwzx 6,5,1 /* load to gpr */
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andi. 6,6,0xFF /* mask wanted bits */
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cmplwi 6,0x0 /* cmp with zero */
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bne .invariant_violation /* branch if not zero */
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#endif
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/* Using r11 - value used again further on, so don't trash! */
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lis 11,.tocent__vgPlain_machine_ppc64_has_VMX@ha
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ld 11,.tocent__vgPlain_machine_ppc64_has_VMX@l(11)
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cmpldi 11,0
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beq .LafterVMX8
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/* Check VSCR[NJ] == 1 */
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/* first generate 4x 0x00010000 */
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vspltisw 4,0x1 /* 4x 0x00000001 */
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vspltisw 5,0x0 /* zero */
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vsldoi 6,4,5,0x2 /* <<2*8 => 4x 0x00010000 */
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/* retrieve VSCR and mask wanted bits */
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mfvscr 7
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vand 7,7,6 /* gives NJ flag */
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vspltw 7,7,0x3 /* flags-word to all lanes */
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vcmpequw. 8,6,7 /* CR[24] = 1 if v6 == v7 */
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bt 24,.invariant_violation /* branch if all_equal */
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.LafterVMX8:
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/* otherwise we're OK */
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b .run_innerloop_exit_REALLY
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.invariant_violation:
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li 3,VG_TRC_INVARIANT_FAILED
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b .run_innerloop_exit_REALLY
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.run_innerloop_exit_REALLY:
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/* r3 holds VG_TRC_* value to return */
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/* Return to parent stack */
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addi 1,1,48
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/* Write ctr to VG_(dispatch_ctr) (=32bit value) */
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mfctr 17
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lis 18,.tocent__vgPlain_dispatch_ctr@ha
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stw 17,.tocent__vgPlain_dispatch_ctr@l(18)
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/* Restore callee-saved registers... */
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/* Floating-point regs */
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lfd 31,616(1)
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lfd 30,608(1)
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lfd 29,600(1)
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lfd 28,592(1)
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lfd 27,584(1)
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lfd 26,576(1)
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lfd 25,568(1)
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lfd 24,560(1)
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lfd 23,552(1)
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lfd 22,544(1)
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lfd 21,536(1)
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lfd 20,528(1)
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lfd 19,520(1)
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lfd 18,512(1)
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lfd 17,504(1)
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lfd 16,496(1)
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lfd 15,488(1)
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lfd 14,480(1)
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/* General regs */
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ld 31,472(1)
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ld 30,464(1)
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ld 29,456(1)
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ld 28,448(1)
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ld 27,440(1)
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ld 26,432(1)
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ld 25,424(1)
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ld 24,416(1)
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ld 23,408(1)
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ld 22,400(1)
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ld 21,392(1)
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ld 20,384(1)
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ld 19,376(1)
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ld 18,368(1)
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ld 17,360(1)
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ld 16,352(1)
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ld 15,344(1)
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ld 14,336(1)
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ld 13,328(1)
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/* r11 already holds VG_(machine_ppc64_has_VMX) value */
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cmpldi 11,0
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beq .LafterVMX9
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/* VRSAVE */
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lwz 4,324(1)
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mfspr 4,256 /* VRSAVE reg is spr number 256 */
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/* Vector regs */
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li 4,304
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lvx 31,4,1
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li 4,288
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lvx 30,4,1
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li 4,272
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lvx 29,4,1
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li 4,256
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lvx 28,4,1
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li 4,240
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lvx 27,4,1
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li 4,224
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lvx 26,4,1
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li 4,208
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lvx 25,4,1
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li 4,192
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lvx 24,4,1
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li 4,176
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lvx 23,4,1
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li 4,160
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lvx 22,4,1
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li 4,144
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lvx 21,4,1
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li 4,128
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lvx 20,4,1
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.LafterVMX9:
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/* reset cr, lr, sp */
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ld 0,632(1) /* stack_size + 8 */
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mtcr 0
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ld 0,640(1) /* stack_size + 16 */
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mtlr 0
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addi 1,1,624 /* stack_size */
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blr
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/* Other ways of getting out of the inner loop. Placed out-of-line to
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make it look cleaner.
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*/
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.dispatch_exceptional:
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/* this is jumped to only, not fallen-through from above */
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/* save r30 in %CIA and defer to sched */
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ld 16,152(1)
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std 30,OFFSET_ppc64_CIA(16)
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b .run_innerloop_exit
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.fast_lookup_failed:
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/* %CIA is up to date here since dispatch_boring dominates */
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mfctr 17
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addi 17,17,1
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mtctr 17
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li 3,VG_TRC_INNER_FASTMISS
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b .run_innerloop_exit
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.counter_is_zero:
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/* %CIA is up to date here since dispatch_boring dominates */
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mfctr 17
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addi 17,17,1
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mtctr 17
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li 3,VG_TRC_INNER_COUNTERZERO
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b .run_innerloop_exit
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/* Let the linker know we don't need an executable stack */
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.section .note.GNU-stack,"",@progbits
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##--------------------------------------------------------------------##
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##--- end ---##
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##--------------------------------------------------------------------##
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