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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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5e6d4577de
"insn_address >> 1". The former is appropriate for ARM code, where all insns are 4-sized and 4-aligned, but not for Thumb code, where the minimum size and alignment is 2. The old scheme happened to work for Thumb (indeed, any hash function would), but caused huge amounts of conflict misses in the fast cache for some programs. The change has been observed to reduce conflict misses by up to 100 times, and in some cases, improves performance significantly for Thumb code. Performance of ARM code is unchanged or possibly a bit worse. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@11716
76 lines
2.8 KiB
C
76 lines
2.8 KiB
C
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/*--------------------------------------------------------------------*/
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/*--- Asm-only TransTab stuff. pub_core_transtab_asm.h ---*/
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/*--------------------------------------------------------------------*/
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/*
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This file is part of Valgrind, a dynamic binary instrumentation
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framework.
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Copyright (C) 2000-2010 Julian Seward
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jseward@acm.org
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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#ifndef __PUB_CORE_TRANSTAB_ASM_H
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#define __PUB_CORE_TRANSTAB_ASM_H
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/* Constants for the fast translation lookup cache. It is a direct
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mapped cache, with 2^VG_TT_FAST_BITS entries.
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On x86/amd64, the cache index is computed as
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'address[VG_TT_FAST_BITS-1 : 0]'.
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On ppc32/ppc64, the bottom two bits of instruction addresses are
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zero, which means that function causes only 1/4 of the entries to
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ever be used. So instead the function is '(address >>u
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2)[VG_TT_FAST_BITS-1 : 0]' on those targets.
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On ARM we do like ppc32/ppc64, although that will have to be
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revisited when we come to implement Thumb.
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On s390x the rightmost bit of an instruction address is zero.
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For best table utilization shift the address to the right by 1 bit. */
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#define VG_TT_FAST_BITS 15
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#define VG_TT_FAST_SIZE (1 << VG_TT_FAST_BITS)
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#define VG_TT_FAST_MASK ((VG_TT_FAST_SIZE) - 1)
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/* This macro isn't usable in asm land; nevertheless this seems
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like a good place to put it. */
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#if defined(VGA_x86) || defined(VGA_amd64)
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# define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) ) & VG_TT_FAST_MASK)
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#elif defined(VGA_s390x) || defined(VGA_arm)
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# define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 1) & VG_TT_FAST_MASK)
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#elif defined(VGA_ppc32) || defined(VGA_ppc64)
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# define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 2) & VG_TT_FAST_MASK)
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#else
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# error "VG_TT_FAST_HASH: unknown platform"
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#endif
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#endif // __PUB_CORE_TRANSTAB_ASM_H
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/*--------------------------------------------------------------------*/
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/*--- end ---*/
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/*--------------------------------------------------------------------*/
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