mirror of
https://github.com/Zenithsiz/ftmemsim-valgrind.git
synced 2026-02-11 14:01:48 +00:00
68a17eeb24
attempts to patch instructions as it deals with the ppc64 (BE) function descriptor. This is actually due to the RELRO option being enabled by default for the ppc64 (BE) platform, per an upstream binutils change. Bugzilla 365912 reported by Will Schmidt, Will supplied the patch to fix the make file none/tests/ppc64/Makefile.a Patch tested on Power 7 and Power 8. git-svn-id: svn://svn.valgrind.org/valgrind/trunk@15917
153 lines
5.5 KiB
Makefile
153 lines
5.5 KiB
Makefile
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include $(top_srcdir)/Makefile.tool-tests.am
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dist_noinst_SCRIPTS = filter_stderr
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EXTRA_DIST = \
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jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest jm-int.stdout.exp-LE \
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jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-LE jm-fp.stdout.exp-LE2 jm-fp.stdout.exp-BE2 \
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jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan jm-vmx.stdout.exp-LE \
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jm-vmx.vgtest \
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jm-misc.stderr.exp jm-misc.stdout.exp jm-misc.vgtest \
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lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
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std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp std_reg_imm.stdout.exp-LE \
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round.stderr.exp round.stdout.exp round.vgtest \
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twi_tdi.stderr.exp twi_tdi.stdout.exp twi_tdi.vgtest \
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tw_td.stderr.exp tw_td.stdout.exp tw_td.vgtest \
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opcodes.h \
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power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \
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power6_mf_gpr.stderr.exp power6_mf_gpr.stdout.exp power6_mf_gpr.vgtest \
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test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
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test_isa_2_06_part1.stdout.exp-LE \
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test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
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test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
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test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
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test_dfp2.stderr.exp test_dfp2.stdout.exp test_dfp2.vgtest \
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test_dfp2.stdout.exp_Without_dcffix \
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test_dfp3.stderr.exp test_dfp3.stdout.exp test_dfp3.vgtest \
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test_dfp4.stderr.exp test_dfp4.stdout.exp test_dfp4.vgtest \
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test_dfp5.stderr.exp test_dfp5.stdout.exp test_dfp5.vgtest \
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jm_vec_isa_2_07.stderr.exp jm_vec_isa_2_07.stdout.exp jm_vec_isa_2_07.vgtest \
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jm_fp_isa_2_07.stderr.exp jm_fp_isa_2_07.stdout.exp jm_fp_isa_2_07.vgtest \
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jm_int_isa_2_07.stderr.exp jm_int_isa_2_07.vgtest \
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jm_int_isa_2_07.stdout.exp jm_int_isa_2_07.stdout.exp-LE \
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test_isa_2_07_part2.stderr.exp test_isa_2_07_part2.stdout.exp test_isa_2_07_part2.vgtest \
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test_tm.stderr.exp test_tm.stdout.exp test_tm.vgtest \
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test_touch_tm.stderr.exp test_touch_tm.stdout.exp test_touch_tm.vgtest \
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ldst_multiple.stderr.exp ldst_multiple.stdout.exp ldst_multiple.vgtest \
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data-cache-instructions.stderr.exp data-cache-instructions.stdout.exp data-cache-instructions.vgtest \
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test_isa_3_0_altivec.stderr.exp test_isa_3_0_altivec.stdout.exp test_isa_3_0_altivec.vgtest \
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test_isa_3_0_other.stderr.exp test_isa_3_0_other.stdout.exp test_isa_3_0_other.vgtest
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check_PROGRAMS = \
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allexec \
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lsw jm-insns round \
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test_isa_2_06_part1 test_isa_2_06_part2 test_isa_2_06_part3 \
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test_dfp1 test_dfp2 test_dfp3 test_dfp4 test_dfp5 \
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test_isa_2_07_part1 test_isa_2_07_part2 \
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test_isa_3_0 \
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test_tm test_touch_tm ldst_multiple data-cache-instructions \
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power6_mf_gpr std_reg_imm \
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twi_tdi tw_td power6_bcmp
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AM_CFLAGS += @FLAG_M64@
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AM_CXXFLAGS += @FLAG_M64@
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AM_CCASFLAGS += @FLAG_M64@
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allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@
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if HAS_ALTIVEC
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BUILD_FLAG_ALTIVEC = -maltivec
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ALTIVEC_FLAG = -DHAS_ALTIVEC
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else
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BUILD_FLAG_ALTIVEC =
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ALTIVEC_FLAG =
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endif
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if HAS_VSX
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BUILD_FLAG_VSX = -mvsx
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VSX_FLAG = -DHAS_VSX
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else
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VSX_FLAG =
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BUILD_FLAG_VSX =
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endif
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if HAS_DFP
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BUILD_FLAGS_DFP = -mhard-dfp -mcpu=power6
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DFP_FLAG = -DHAS_DFP
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else
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BUILD_FLAGS_DFP =
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DFP_FLAG =
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endif
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if HAS_ISA_2_07
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BUILD_FLAGS_ISA_2_07 = -mcpu=power8
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ISA_2_07_FLAG = -DHAS_ISA_2_07
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else
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BUILD_FLAGS_ISA_2_07 =
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ISA_2_07_FLAG =
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endif
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if SUPPORTS_HTM
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HTM_FLAG = -mhtm -DSUPPORTS_HTM
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else
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HTM_FLAG =
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endif
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jm_insns_CFLAGS = $(AM_CFLAGS) -Wl,-z,norelro -Winline -Wall -O -g -mregnames \
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@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_ALTIVEC)
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if HAS_ISA_3_0
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BUILD_FLAGS_ISA_3_0 = -mcpu=power8
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ISA_3_0_FLAG = -DHAS_ISA_3_0
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else
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BUILD_FLAGS_ISA_3_0 =
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ISA_3_0_FLAG =
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endif
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test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
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@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
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test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
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@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
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test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
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@FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
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test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_DFP)
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test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_DFP)
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test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_DFP)
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test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_DFP)
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test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_DFP)
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test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
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test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
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test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_2_07_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
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test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_2_07_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
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test_isa_3_0_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(HTM_FLAG) $(ISA_3_0_FLAG) \
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@FLAG_M64@ $(BUILD_FLAGS_ISA_3_0)
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test_isa_2_06_part3_LDADD = -lm
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test_dfp1_LDADD = -lm
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test_dfp2_LDADD = -lm
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test_dfp3_LDADD = -lm
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test_dfp4_LDADD = -lm
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test_dfp5_LDADD = -lm
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test_isa_2_07_part1_LDADD = -lm
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test_isa_2_07_part2_LDADD = -lm
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test_tm_LDADD = -lm
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test_touch_tm_LDADD = -lm
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test_isa_3_0_LDADD = -lm
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