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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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50bb127b1d
[This commit contains an implementation for all targets except amd64-solaris and x86-solaris, which will be completed shortly.] In the baseline simulator, jumps to guest code addresses that are not known at JIT time have to be looked up in a guest->host mapping table. That means: indirect branches, indirect calls and most commonly, returns. Since there are huge numbers of these (often 10+ million/second) the mapping mechanism needs to be extremely cheap. Currently, this is implemented using a direct-mapped cache, VG_(tt_fast), with 2^15 (guest_addr, host_addr) pairs. This is queried in handwritten assembly in VG_(disp_cp_xindir) in dispatch-<arch>-<os>.S. If there is a miss in the cache then we fall back out to C land, and do a slow lookup using VG_(search_transtab). Given that the size of the translation table(s) in recent years has expanded significantly in order to keep pace with increasing application sizes, two bad things have happened: (1) the cost of a miss in the fast cache has risen significantly, and (2) the miss rate on the fast cache has also increased significantly. This means that large (~ one-million-basic-blocks-JITted) applications that run for a long time end up spending a lot of time in VG_(search_transtab). The proposed fix is to increase associativity of the fast cache, from 1 (direct mapped) to 4. Simulations of various cache configurations using indirect-branch traces from a large application show that is the best of various configurations. In an extreme case with 5.7 billion indirect branches: * The increase of associativity from 1 way to 4 way, whilst keeping the overall cache size the same (32k guest/host pairs), reduces the miss rate by around a factor of 3, from 4.02% to 1.30%. * The use of a slightly better hash function than merely slicing off the bottom 15 bits of the address, reduces the miss rate further, from 1.30% to 0.53%. Overall the VG_(tt_fast) miss rate is almost unchanged on small workloads, but reduced by a factor of up to almost 8 on large workloads. By implementing each (4-entry) cache set using a move-to-front scheme in the case of hits in ways 1, 2 or 3, the vast majority of hits can be made to happen in way 0. Hence the cost of having this extra associativity is almost zero in the case of a hit. The improved hash function costs an extra 2 ALU shots (a shift and an xor) but overall this seems performance neutral to a win.
590 lines
18 KiB
ArmAsm
590 lines
18 KiB
ArmAsm
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/*--------------------------------------------------------------------*/
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/*--- The core dispatch loop, for jumping to a code address. ---*/
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/*--- dispatch-ppc32-linux.S ---*/
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/*--------------------------------------------------------------------*/
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/*
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This file is part of Valgrind, a dynamic binary instrumentation
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framework.
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Copyright (C) 2005-2017 Cerion Armour-Brown <cerion@open-works.co.uk>
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
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02111-1307, USA.
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The GNU General Public License is contained in the file COPYING.
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*/
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#include "pub_core_basics_asm.h"
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#if defined(VGP_ppc32_linux)
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#include "pub_core_dispatch_asm.h"
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#include "pub_core_transtab_asm.h"
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#include "libvex_guest_offsets.h" /* for OFFSET_ppc32_CIA */
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/*------------------------------------------------------------*/
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/*--- ---*/
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/*--- The dispatch loop. VG_(disp_run_translations) is ---*/
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/*--- used to run all translations, ---*/
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/*--- including no-redir ones. ---*/
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/*--- ---*/
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/*------------------------------------------------------------*/
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/*----------------------------------------------------*/
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/*--- Entry and preamble (set everything up) ---*/
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/*----------------------------------------------------*/
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/* signature:
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void VG_(disp_run_translations)( UWord* two_words,
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void* guest_state,
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Addr host_addr );
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*/
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.text
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.globl VG_(disp_run_translations)
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.type VG_(disp_run_translations), @function
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VG_(disp_run_translations):
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/* r3 holds two_words */
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/* r4 holds guest_state */
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/* r5 holds host_addr */
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/* ----- entry point to VG_(disp_run_translations) ----- */
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/* For Linux/ppc32 we need the SysV ABI, which uses
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LR->4(parent_sp), CR->anywhere.
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(The AIX ABI, used on Darwin,
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uses LR->8(prt_sp), CR->4(prt_sp))
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*/
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/* Save lr */
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mflr 6
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stw 6,4(1)
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/* New stack frame */
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stwu 1,-496(1) /* sp should maintain 16-byte alignment */
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/* Save callee-saved registers... */
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/* r3, r4, r5 are live here, so use r6 */
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lis 6,VG_(machine_ppc32_has_FP)@ha
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lwz 6,VG_(machine_ppc32_has_FP)@l(6)
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cmplwi 6,0
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beq LafterFP1
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/* Floating-point reg save area : 144 bytes */
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stfd 31,488(1)
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stfd 30,480(1)
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stfd 29,472(1)
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stfd 28,464(1)
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stfd 27,456(1)
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stfd 26,448(1)
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stfd 25,440(1)
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stfd 24,432(1)
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stfd 23,424(1)
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stfd 22,416(1)
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stfd 21,408(1)
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stfd 20,400(1)
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stfd 19,392(1)
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stfd 18,384(1)
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stfd 17,376(1)
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stfd 16,368(1)
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stfd 15,360(1)
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stfd 14,352(1)
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LafterFP1:
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/* General reg save area : 76 bytes */
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stw 31,348(1)
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stw 30,344(1)
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stw 29,340(1)
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stw 28,336(1)
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stw 27,332(1)
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stw 26,328(1)
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stw 25,324(1)
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stw 24,320(1)
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stw 23,316(1)
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stw 22,312(1)
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stw 21,308(1)
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stw 20,304(1)
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stw 19,300(1)
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stw 18,296(1)
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stw 17,292(1)
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stw 16,288(1)
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stw 15,284(1)
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stw 14,280(1)
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stw 13,276(1)
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stw 3,272(1) /* save two_words for later */
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/* It's necessary to save/restore VRSAVE in the AIX / Darwin ABI.
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The Linux kernel might not actually use VRSAVE for its intended
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purpose, but it should be harmless to preserve anyway. */
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/* r3, r4, r5 are live here, so use r6 */
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lis 6,VG_(machine_ppc32_has_VMX)@ha
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lwz 6,VG_(machine_ppc32_has_VMX)@l(6)
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cmplwi 6,0
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beq LafterVMX1
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#ifdef HAS_ALTIVEC
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/* VRSAVE save word : 32 bytes */
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mfspr 6,256 /* vrsave reg is spr number 256 */
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stw 6,244(1)
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/* Alignment padding : 4 bytes */
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/* Vector reg save area (quadword aligned) : 192 bytes */
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li 6,224
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stvx 31,6,1
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li 6,208
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stvx 30,6,1
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li 6,192
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stvx 29,6,1
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li 6,176
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stvx 28,6,1
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li 6,160
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stvx 27,6,1
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li 6,144
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stvx 26,6,1
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li 6,128
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stvx 25,6,1
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li 6,112
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stvx 24,6,1
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li 6,96
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stvx 23,6,1
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li 6,80
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stvx 22,6,1
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li 6,64
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stvx 21,6,1
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li 6,48
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stvx 20,6,1
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#endif
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LafterVMX1:
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/* Save cr */
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mfcr 6
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stw 6,44(1)
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/* Local variable space... */
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/* 32(sp) used later to check FPSCR[RM] */
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/* r3 holds two_words */
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/* r4 holds guest_state */
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/* r5 holds host_addr */
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/* 24(sp) used later to stop ctr reg being clobbered */
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/* 20(sp) used later to load fpscr with zero */
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/* 8:16(sp) free */
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/* Linkage Area (reserved)
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4(sp) : LR
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0(sp) : back-chain
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*/
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/* set host FPU control word to the default mode expected
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by VEX-generated code. See comments in libvex.h for
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more info. */
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lis 6,VG_(machine_ppc32_has_FP)@ha
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lwz 6,VG_(machine_ppc32_has_FP)@l(6)
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cmplwi 6,0
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beq LafterFP2
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/* get zero into f3 (tedious) */
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/* note: fsub 3,3,3 is not a reliable way to do this,
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since if f3 holds a NaN or similar then we don't necessarily
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wind up with zero. */
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li 6,0
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stw 6,20(1)
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lfs 3,20(1)
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mtfsf 0xFF,3 /* fpscr = f3 */
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LafterFP2:
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/* set host AltiVec control word to the default mode expected
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by VEX-generated code. */
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lis 6,VG_(machine_ppc32_has_VMX)@ha
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lwz 6,VG_(machine_ppc32_has_VMX)@l(6)
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cmplwi 6,0
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beq LafterVMX2
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#ifdef HAS_ALTIVEC
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vspltisw 3,0x0 /* generate zero */
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mtvscr 3
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#endif
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LafterVMX2:
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/* make a stack frame for the code we are calling */
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stwu 1,-16(1)
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/* Set up the guest state ptr */
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mr 31,4 /* r31 (generated code gsp) = r4 */
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/* and jump into the code cache. Chained translations in
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the code cache run, until for whatever reason, they can't
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continue. When that happens, the translation in question
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will jump (or call) to one of the continuation points
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VG_(cp_...) below. */
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mtctr 5
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bctr
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/*NOTREACHED*/
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/*----------------------------------------------------*/
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/*--- Postamble and exit. ---*/
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/*----------------------------------------------------*/
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postamble:
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/* At this point, r6 and r7 contain two
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words to be returned to the caller. r6
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holds a TRC value, and r7 optionally may
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hold another word (for CHAIN_ME exits, the
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address of the place to patch.) */
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/* We're leaving. Check that nobody messed with
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VSCR or FPSCR in ways we don't expect. */
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/* Using r10 - value used again further on, so don't trash! */
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lis 10,VG_(machine_ppc32_has_FP)@ha
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lwz 10,VG_(machine_ppc32_has_FP)@l(10)
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/* Using r11 - value used again further on, so don't trash! */
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lis 11,VG_(machine_ppc32_has_VMX)@ha
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lwz 11,VG_(machine_ppc32_has_VMX)@l(11)
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cmplwi 10,0 /* Do we have FP ? */
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beq LafterFP8
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/* Set fpscr back to a known state, since vex-generated code
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may have messed with fpscr[rm]. */
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li 5,0
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addi 1,1,-16
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stw 5,0(1)
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lfs 3,0(1)
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addi 1,1,16
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mtfsf 0xFF,3 /* fpscr = f3 */
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LafterFP8:
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cmplwi 11,0 /* Do we have altivec? */
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beq LafterVMX8
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#ifdef HAS_ALTIVEC
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/* Check VSCR[NJ] == 1 */
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/* first generate 4x 0x00010000 */
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vspltisw 4,0x1 /* 4x 0x00000001 */
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vspltisw 5,0x0 /* zero */
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vsldoi 6,4,5,0x2 /* <<2*8 => 4x 0x00010000 */
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/* retrieve VSCR and mask wanted bits */
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mfvscr 7
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vand 7,7,6 /* gives NJ flag */
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vspltw 7,7,0x3 /* flags-word to all lanes */
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vcmpequw. 8,6,7 /* CR[24] = 1 if v6 == v7 */
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bt 24,invariant_violation /* branch if all_equal */
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#endif
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LafterVMX8:
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/* otherwise we're OK */
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b remove_frame
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invariant_violation:
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li 6,VG_TRC_INVARIANT_FAILED
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li 7,0
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/* fall through */
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remove_frame:
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/* Restore FP regs */
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/* r10 already holds VG_(machine_ppc32_has_FP) value */
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cmplwi 10,0
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beq LafterFP9
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/* Floating-point regs */
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lfd 31,488(1)
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lfd 30,480(1)
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lfd 29,472(1)
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lfd 28,464(1)
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lfd 27,456(1)
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lfd 26,448(1)
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lfd 25,440(1)
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lfd 24,432(1)
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lfd 23,424(1)
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lfd 22,416(1)
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lfd 21,408(1)
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lfd 20,400(1)
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lfd 19,392(1)
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lfd 18,384(1)
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lfd 17,376(1)
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lfd 16,368(1)
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lfd 15,360(1)
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lfd 14,352(1)
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LafterFP9:
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/* r11 already holds VG_(machine_ppc32_has_VMX) value */
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cmplwi 11,0
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beq LafterVMX9
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/* Restore Altivec regs */
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#ifdef HAS_ALTIVEC
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/* VRSAVE */
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lwz 4,244(1)
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mfspr 4,256 /* VRSAVE reg is spr number 256 */
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/* Vector regs */
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li 4,224
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lvx 31,4,1
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li 4,208
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lvx 30,4,1
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li 4,192
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lvx 29,4,1
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li 4,176
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lvx 28,4,1
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li 4,160
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lvx 27,4,1
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li 4,144
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lvx 26,4,1
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li 4,128
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lvx 25,4,1
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li 4,112
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lvx 24,4,1
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li 4,96
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lvx 23,4,1
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li 4,80
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lvx 22,4,1
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li 4,64
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lvx 21,4,1
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li 4,48
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lvx 20,4,1
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#endif
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LafterVMX9:
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/* restore int regs, including importantly r3 (two_words) */
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addi 1,1,16
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lwz 31,348(1)
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lwz 30,344(1)
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lwz 29,340(1)
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lwz 28,336(1)
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lwz 27,332(1)
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lwz 26,328(1)
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lwz 25,324(1)
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lwz 24,320(1)
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lwz 23,316(1)
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lwz 22,312(1)
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lwz 21,308(1)
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lwz 20,304(1)
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lwz 19,300(1)
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lwz 18,296(1)
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lwz 17,292(1)
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lwz 16,288(1)
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lwz 15,284(1)
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lwz 14,280(1)
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lwz 13,276(1)
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lwz 3,272(1)
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/* Stash return values */
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stw 6,0(3)
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stw 7,4(3)
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/* restore lr & sp, and leave */
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lwz 0,500(1) /* stack_size + 4 */
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mtlr 0
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addi 1,1,496 /* stack_size */
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blr
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/*----------------------------------------------------*/
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/*--- Continuation points ---*/
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/*----------------------------------------------------*/
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/* ------ Chain me to slow entry point ------ */
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.global VG_(disp_cp_chain_me_to_slowEP)
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VG_(disp_cp_chain_me_to_slowEP):
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/* We got called. The return address indicates
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where the patching needs to happen. Collect
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the return address and, exit back to C land,
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handing the caller the pair (Chain_me_S, RA) */
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li 6, VG_TRC_CHAIN_ME_TO_SLOW_EP
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mflr 7
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/* 8 = imm32-fixed2 r30, disp_cp_chain_me_to_slowEP
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4 = mtctr r30
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4 = btctr
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*/
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subi 7,7,8+4+4
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b postamble
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/* ------ Chain me to fast entry point ------ */
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.global VG_(disp_cp_chain_me_to_fastEP)
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VG_(disp_cp_chain_me_to_fastEP):
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/* We got called. The return address indicates
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where the patching needs to happen. Collect
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the return address and, exit back to C land,
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handing the caller the pair (Chain_me_S, RA) */
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li 6, VG_TRC_CHAIN_ME_TO_FAST_EP
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mflr 7
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/* 8 = imm32-fixed2 r30, disp_cp_chain_me_to_fastEP
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4 = mtctr r30
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4 = btctr
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*/
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subi 7,7,8+4+4
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b postamble
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/* ------ Indirect but boring jump ------ */
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.global VG_(disp_cp_xindir)
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VG_(disp_cp_xindir):
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/* Where are we going? */
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lwz 20, OFFSET_ppc32_CIA(31)
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/* stats only */
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lis 24, VG_(stats__n_xIndirs_32)@ha
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addi 24, 24, VG_(stats__n_xIndirs_32)@l
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lwz 25, 0(24)
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addi 25, 25, 1
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stw 25, 0(24)
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// LIVE: r31 (guest state ptr), r20 (guest address to go to).
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// We use 6 temporaries:
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// r26 (to point at the relevant FastCacheSet),
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// r21, r22, r23 (scratch, for swapping entries within a set)
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// r24, r25 (other scratch)
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/* Try a fast lookup in the translation cache. This is pretty much
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a handcoded version of VG_(lookupInFastCache). */
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// Compute r26 = VG_TT_FAST_HASH(guest)
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srwi 26, 20, 2 // g2 = guest >> 2
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srwi 25, 20, (VG_TT_FAST_BITS + 2) // (g2 >> VG_TT_FAST_BITS)
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xor 26, 26, 25 // (g2 >> VG_TT_FAST_BITS) ^ g2
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andi. 26, 26, VG_TT_FAST_MASK // setNo
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// Compute r6 = &VG_(tt_fast)[r6]
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lis 25, VG_(tt_fast)@ha
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addi 25, 25, VG_(tt_fast)@l
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slwi 26, 26, VG_FAST_CACHE_SET_BITS
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add 26, 26, 25
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// LIVE: r31 (guest state ptr), r20 (guest addr), r26 (cache set)
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// try way 0
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lwz 24, FCS_g0(26) // .guest0
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lwz 25, FCS_h0(26) // .host0
|
|
cmpw 24, 20 // cmp against .guest0
|
|
bne 1f
|
|
// hit at way 0
|
|
// goto .host0
|
|
mtctr 25
|
|
bctr
|
|
/*NOTREACHED*/
|
|
|
|
1: // try way 1
|
|
lwz 24, FCS_g1(26)
|
|
cmpw 24, 20 // cmp against .guest1
|
|
bne 2f
|
|
// hit at way 1; swap upwards
|
|
lwz 21, FCS_g0(26) // 21 = old .guest0
|
|
lwz 22, FCS_h0(26) // 22 = old .host0
|
|
lwz 23, FCS_h1(26) // 23 = old .host1
|
|
stw 20, FCS_g0(26) // new .guest0 = guest
|
|
stw 23, FCS_h0(26) // new .host0 = old .host1
|
|
stw 21, FCS_g1(26) // new .guest1 = old .guest0
|
|
stw 22, FCS_h1(26) // new .host1 = old .host0
|
|
// stats only
|
|
lis 24, VG_(stats__n_xIndir_hits1_32)@ha
|
|
addi 24, 24, VG_(stats__n_xIndir_hits1_32)@l
|
|
lwz 25, 0(24)
|
|
addi 25, 25, 1
|
|
stw 25, 0(24)
|
|
// goto old .host1 a.k.a. new .host0
|
|
mtctr 23
|
|
bctr
|
|
/*NOTREACHED*/
|
|
|
|
2: // try way 2
|
|
lwz 24, FCS_g2(26)
|
|
cmpw 24, 20 // cmp against .guest2
|
|
bne 3f
|
|
// hit at way 2; swap upwards
|
|
lwz 21, FCS_g1(26)
|
|
lwz 22, FCS_h1(26)
|
|
lwz 23, FCS_h2(26)
|
|
stw 20, FCS_g1(26)
|
|
stw 23, FCS_h1(26)
|
|
stw 21, FCS_g2(26)
|
|
stw 22, FCS_h2(26)
|
|
// stats only
|
|
lis 24, VG_(stats__n_xIndir_hits2_32)@ha
|
|
addi 24, 24, VG_(stats__n_xIndir_hits2_32)@l
|
|
lwz 25, 0(24)
|
|
addi 25, 25, 1
|
|
stw 25, 0(24)
|
|
// goto old .host2 a.k.a. new .host1
|
|
mtctr 23
|
|
bctr
|
|
/*NOTREACHED*/
|
|
|
|
3: // try way 3
|
|
lwz 24, FCS_g3(26)
|
|
cmpw 24, 20 // cmp against .guest3
|
|
bne 4f
|
|
// hit at way 3; swap upwards
|
|
lwz 21, FCS_g2(26)
|
|
lwz 22, FCS_h2(26)
|
|
lwz 23, FCS_h3(26)
|
|
stw 20, FCS_g2(26)
|
|
stw 23, FCS_h2(26)
|
|
stw 21, FCS_g3(26)
|
|
stw 22, FCS_h3(26)
|
|
// stats only
|
|
lis 24, VG_(stats__n_xIndir_hits3_32)@ha
|
|
addi 24, 24, VG_(stats__n_xIndir_hits3_32)@l
|
|
lwz 25, 0(24)
|
|
addi 25, 25, 1
|
|
stw 25, 0(24)
|
|
// goto old .host3 a.k.a. new .host2
|
|
mtctr 23
|
|
bctr
|
|
/*NOTREACHED*/
|
|
|
|
4: // fast lookup failed:
|
|
/* stats only */
|
|
lis 24, VG_(stats__n_xIndir_misses_32)@ha
|
|
addi 24, 24, VG_(stats__n_xIndir_misses_32)@l
|
|
lwz 25, 0(24)
|
|
addi 25, 25, 1
|
|
stw 25, 0(24)
|
|
|
|
li 6, VG_TRC_INNER_FASTMISS
|
|
li 7, 0
|
|
b postamble
|
|
/*NOTREACHED*/
|
|
|
|
/* ------ Assisted jump ------ */
|
|
.global VG_(disp_cp_xassisted)
|
|
VG_(disp_cp_xassisted):
|
|
/* r31 contains the TRC */
|
|
mr 6,31
|
|
li 7,0
|
|
b postamble
|
|
|
|
/* ------ Event check failed ------ */
|
|
.global VG_(disp_cp_evcheck_fail)
|
|
VG_(disp_cp_evcheck_fail):
|
|
li 6,VG_TRC_INNER_COUNTERZERO
|
|
li 7,0
|
|
b postamble
|
|
|
|
|
|
.size VG_(disp_run_translations), .-VG_(disp_run_translations)
|
|
|
|
#endif // defined(VGP_ppc32_linux)
|
|
|
|
/* Let the linker know we don't need an executable stack */
|
|
MARK_STACK_NO_EXEC
|
|
|
|
/*--------------------------------------------------------------------*/
|
|
/*--- end ---*/
|
|
/*--------------------------------------------------------------------*/
|