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https://github.com/Zenithsiz/ftmemsim-valgrind.git
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20976f432d
This implements various z/Architecture instructions that conditionally
yield a data exception ("trap"). The condition is either based on a
comparison being true ("compare and trap") or on a loaded value being
zero ("load and trap"). These instructions haven't been widely used in
the past, but may now be emitted by newer compilers. Note that the
resulting signal for a data exception is SIGFPE, not SIGTRAP. Thus this
patch also adds a new jump kind Ijk_SigFPE.
47 lines
1.0 KiB
Plaintext
47 lines
1.0 KiB
Plaintext
lat ffffffff12345678 ffffffffedcba988 ffffffff80000000 [FPE 0] ffffffff00000000
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lgat 0000000012345678 ffffffffedcba988 0000000080000000 [FPE 0] 0000000000000000
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lfhat 12345678ffffffff edcba988ffffffff 80000000ffffffff [FPE 0] 00000000ffffffff
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llgfat 0000000012345678 00000000edcba988 0000000080000000 [FPE 0] 0000000000000000
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llgtat 0000000012345678 000000006dcba988 [FPE 0] 0000000000000000 [FPE 0] 0000000000000000
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crt:
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0 Y 0 [FPE 0]
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1 < -1
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2147483647 > -2147483648 [FPE 0]
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clrt:
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0 Y 0 [FPE 0]
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1 < 4294967295 [FPE 0]
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2147483647 > 2147483648
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cgrt:
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0 Y 0 [FPE 0]
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1 < -1
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2147483647 > 2147483648
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clgrt:
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0 Y 0 [FPE 0]
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1 < 18446744073709551615 [FPE 0]
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2147483647 > 2147483648
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cit:
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0 N 0
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-1 != -1
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-2147483648 <= 41 [FPE 0]
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clfit:
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0 N 0
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4294967295 != 65535 [FPE 0]
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2147483648 <= 41
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cgit:
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0 N 0
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-1 != -1
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2147483648 <= 41
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clgit:
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0 N 0
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18446744073709551615 != 65535 [FPE 0]
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2147483648 <= 41
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clt:
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1 >= 4294967295
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4294967295 == 4294967295 [FPE 0]
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clgt:
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1 >= 18446744073709551615
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4294967295 == 18446744073709551615
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